- flashrom-gerrit - mail.coreboot.org

[M] Change in flashrom[main]: ch347_spi: Add spi clock frequency selection
by ZhiYuanNJ (Code Review) 02 Jul '24

02 Jul '24

Attention is currently required from: Anastasia Klimchuk, Nicholas Chin. ZhiYuanNJ has posted comments on this change by ZhiYuanNJ. ( https://review.coreboot.org/c/flashrom/+/82776?usp=email ) Change subject: ch347_spi: Add spi clock frequency selection ...................................................................... Patch Set 9: (1 comment) File ch347_spi.c: https://review.coreboot.org/c/flashrom/+/82776/comment/1244260d_7031174f?us… : PS7, Line 355: arg = extract_programmer_param_str(cfg, "spispeed"); > Since you are adding a param, this needs to be explained on manpage for the programmer. […] Done -- To view, visit https://review.coreboot.org/c/flashrom/+/82776?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: If2be48929db540a6598ac0b60b37e64597156db7 Gerrit-Change-Number: 82776 Gerrit-PatchSet: 9 Gerrit-Owner: ZhiYuanNJ Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Attention: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Comment-Date: Tue, 02 Jul 2024 02:17:26 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Anastasia Klimchuk <aklm(a)chromium.org>

1 0

[S] Change in flashrom[main]: ch347_spi: Add spi clock frequency selection
by ZhiYuanNJ (Code Review) 01 Jul '24

01 Jul '24

Attention is currently required from: Anastasia Klimchuk, Nicholas Chin. ZhiYuanNJ has posted comments on this change by ZhiYuanNJ. ( https://review.coreboot.org/c/flashrom/+/82776?usp=email ) Change subject: ch347_spi: Add spi clock frequency selection ...................................................................... Patch Set 7: (4 comments) File ch347_spi.c: https://review.coreboot.org/c/flashrom/+/82776/comment/a8b52623_5481dab5?us… : PS7, Line 357: index = 0 > Let's use different variable name, index is already used for indexing the device table. […] Done https://review.coreboot.org/c/flashrom/+/82776/comment/cfc81251_9587a9e8?us… : PS7, Line 365: 30MHz > I don't mind changing the default if it generally works at 30 MHz. […] What is the CH347T device revision that can reproduce this phenomenon? https://review.coreboot.org/c/flashrom/+/82776/comment/309c527c_1c462d2e?us… : PS7, Line 365: Invalid SPI speed > It would be invalid value if you would throw an error and exit, however you do not, but instead cont […] Done https://review.coreboot.org/c/flashrom/+/82776/comment/ca2bf3af_a5217846?us… : PS7, Line 372: clock spi > "clock spi" is redundant here as clock is already mentioned earlier. […] Done -- To view, visit https://review.coreboot.org/c/flashrom/+/82776?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: If2be48929db540a6598ac0b60b37e64597156db7 Gerrit-Change-Number: 82776 Gerrit-PatchSet: 7 Gerrit-Owner: ZhiYuanNJ Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Attention: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Comment-Date: Mon, 01 Jul 2024 06:34:53 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Anastasia Klimchuk <aklm(a)chromium.org> Comment-In-Reply-To: Nicholas Chin <nic.c3.14(a)gmail.com>

1 0

[S] Change in flashrom[main]: ch347_spi: Add spi clock frequency selection
by Nicholas Chin (Code Review) 29 Jun '24

29 Jun '24

Attention is currently required from: Anastasia Klimchuk, ZhiYuanNJ. Nicholas Chin has posted comments on this change by ZhiYuanNJ. ( https://review.coreboot.org/c/flashrom/+/82776?usp=email ) Change subject: ch347_spi: Add spi clock frequency selection ...................................................................... Patch Set 7: (1 comment) File ch347_spi.c: https://review.coreboot.org/c/flashrom/+/82776/comment/5aea48e4_45ce6a7b?us… : PS7, Line 365: 30MHz > It seems you are changing the default, why? […] I don't mind changing the default if it generally works at 30 MHz. I had set it to 15 MHz before as a fairly conservative value as you couldn't easily change it, but that's less of a concern with the ability to change it. That said, I just did some testing and found that a few of my flash chips (Winbond W25Q128JV, Eon EN25QH128A) don't seem to work reliably with the CH347T at 30 MHz, so it might be good to keep it at 15 MHz. The only one that seemed to work reliably was the Macronix MX25L1606E. Sometimes the Winbond chip would work, but when trying to verify it, it would fail, and the differences seemed to be single bit flips. All of those should work at that frequency according to the datasheet, so it's probably some setup/hold time violation. These chips do work with an FT232H programmer I have with a divisor of 2 (30 MHz). -- To view, visit https://review.coreboot.org/c/flashrom/+/82776?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: If2be48929db540a6598ac0b60b37e64597156db7 Gerrit-Change-Number: 82776 Gerrit-PatchSet: 7 Gerrit-Owner: ZhiYuanNJ Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Attention: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Attention: ZhiYuanNJ Gerrit-Comment-Date: Sat, 29 Jun 2024 13:10:53 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Anastasia Klimchuk <aklm(a)chromium.org>

1 0

[XS] Change in flashrom[main]: tests/selfcheck.c: Include the missing header lifecycle.h
by Anastasia Klimchuk (Code Review) 29 Jun '24

29 Jun '24

Attention is currently required from: Hsuan Ting Chen, Hsuan-ting Chen. Anastasia Klimchuk has posted comments on this change by Hsuan-ting Chen. ( https://review.coreboot.org/c/flashrom/+/83219?usp=email ) Change subject: tests/selfcheck.c: Include the missing header lifecycle.h ...................................................................... Patch Set 1: Code-Review-1 (3 comments) Patchset: PS1: I believe you that the issue is real, but I think the solution is not correct. We need to find the right solution. PS1: > as long as we need it, we should include it We don't need lifecycle.h here :) Let's debug the issue properly. I am super suspicious of this: > error: type of ‘selfcheck_board_matches_table’ defaults to ‘int’ [-Werror=implicit-int] First of all , which options did you use for compiling? CHROMIUM repository might have slightly different compiler options set up. Also, was CONFIG_INTERNAL enabled? Commit Message: https://review.coreboot.org/c/flashrom/+/83219/comment/35a145f0_6dc67b75?us… : PS1, Line 9: selfcheck.c is using the macro SKIP_TEST, so we should include the : header lifecycle.h SKIP_TEST is defined in `include/test.h` , which is already included. `lifecycle.h` is not relevant to SKIP_TEST neither to selfcheck. If you look into lifecycle.h you can see it has functions for programmer lifecycle, this is why all programmer tests have it. Here it is not needed. I believe you that you see an error on your environment, but lifecycle.h is not the solution. We need to figure out why exactly the error is happening. -- To view, visit https://review.coreboot.org/c/flashrom/+/83219?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: Ifc07ac66320712fdbf31504b9a980354c1883f40 Gerrit-Change-Number: 83219 Gerrit-PatchSet: 1 Gerrit-Owner: Hsuan-ting Chen <roccochen(a)google.com> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Hsuan Ting Chen <roccochen(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hsuan Ting Chen <roccochen(a)chromium.org> Gerrit-Attention: Hsuan-ting Chen <roccochen(a)google.com> Gerrit-Comment-Date: Sat, 29 Jun 2024 09:23:59 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Hsuan-ting Chen <roccochen(a)google.com>

1 0

[S] Change in flashrom[main]: ch347_spi: Add spi clock frequency selection
by Anastasia Klimchuk (Code Review) 29 Jun '24

29 Jun '24

Attention is currently required from: ZhiYuanNJ. Anastasia Klimchuk has posted comments on this change by ZhiYuanNJ. ( https://review.coreboot.org/c/flashrom/+/82776?usp=email ) Change subject: ch347_spi: Add spi clock frequency selection ...................................................................... Patch Set 7: (5 comments) Patchset: PS7: Thanks for adding new feature! I gave some comments. File ch347_spi.c: https://review.coreboot.org/c/flashrom/+/82776/comment/52b187d8_ca5593e1?us… : PS7, Line 355: arg = extract_programmer_param_str(cfg, "spispeed"); Since you are adding a param, this needs to be explained on manpage for the programmer. Manpage source code is located here: doc/classic_cli_manpage.rst (on the website it looks like this https://flashrom.org/classic_cli_manpage.html#ch347-spi-programmer) You need to update the section for ch347_spi You can test your changes locally, the information is here: https://flashrom.org/how_to_add_docs.html (or you can view the same doc in the tree in your repo) https://review.coreboot.org/c/flashrom/+/82776/comment/448ec752_e54e847e?us… : PS7, Line 357: index = 0 Let's use different variable name, index is already used for indexing the device table. `speed_index` or something like that, but not the same variable name. As a concrete example how things will go wrong: if spispeed param is not provided, you won't even reach this line of code (because arg is NULL). So your index will be whatever is initialized from device table - which is completely different table. You need its own variable for spispeed index, give it default value, and use the same default value on line 366 for the case when spispeed param is unknown value. https://review.coreboot.org/c/flashrom/+/82776/comment/7421829d_502fefb5?us… : PS7, Line 365: Invalid SPI speed It would be invalid value if you would throw an error and exit, however you do not, but instead continue with default value. So I think the better name is "unknown" instead of "invalid". I suggest > Unknown value of spispeed parameter, using default XXX clock spi https://review.coreboot.org/c/flashrom/+/82776/comment/5537ffa6_defad3df?us… : PS7, Line 365: 30MHz It seems you are changing the default, why? Previously the divisor was fixed to 2, which corresponds to 15M with index=2 Now it will be 1, when spispeed value is not recognized? -- To view, visit https://review.coreboot.org/c/flashrom/+/82776?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: If2be48929db540a6598ac0b60b37e64597156db7 Gerrit-Change-Number: 82776 Gerrit-PatchSet: 7 Gerrit-Owner: ZhiYuanNJ Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Attention: ZhiYuanNJ Gerrit-Comment-Date: Sat, 29 Jun 2024 08:56:59 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

1 0

[S] Change in flashrom[main]: ch347_spi: Add spi clock frequency selection
by Nicholas Chin (Code Review) 29 Jun '24

29 Jun '24

Attention is currently required from: ZhiYuanNJ. Nicholas Chin has posted comments on this change by ZhiYuanNJ. ( https://review.coreboot.org/c/flashrom/+/82776?usp=email ) Change subject: ch347_spi: Add spi clock frequency selection ...................................................................... Patch Set 7: (1 comment) File ch347_spi.c: https://review.coreboot.org/c/flashrom/+/82776/comment/df88a6ff_14ffc34a?us… : PS7, Line 372: clock spi "clock spi" is redundant here as clock is already mentioned earlier. ```suggestion msg_pinfo("CH347 SPI clock set to %sHz.\n", spispeeds[index].name); ``` -- To view, visit https://review.coreboot.org/c/flashrom/+/82776?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: If2be48929db540a6598ac0b60b37e64597156db7 Gerrit-Change-Number: 82776 Gerrit-PatchSet: 7 Gerrit-Owner: ZhiYuanNJ Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: ZhiYuanNJ Gerrit-Comment-Date: Sat, 29 Jun 2024 01:55:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

1 0

[XS] Change in flashrom[main]: dummyflasher: assign address of function for LLVM
by Fabian Groffen (Code Review) 28 Jun '24

28 Jun '24

Fabian Groffen has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/83262?usp=email ) Change subject: dummyflasher: assign address of function for LLVM ...................................................................... dummyflasher: assign address of function for LLVM ../flashrom-v1.3.0/dummyflasher.c:933:18: error: incompatible function pointer types initializing 'bool (*)(const struct flashrom_flashctx *, uint8_t)' (aka 'bool (*)(const struct flashrom_flashctx *, unsigned char)') with an expression of type 'bool (struct flashrom_flashctx *, uint8_t)' (aka 'bool (struct flashrom_flashctx *, unsigned char)') [-Wincompatible-function-pointer-types] https://bugs.gentoo.org/915617 Change-Id: I8e5c9ea014d40a2e9e0621b25f8c404e80a79952 Signed-off-by: Fabian Groffen <grobian(a)gentoo.org> --- M dummyflasher.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/62/83262/1 diff --git a/dummyflasher.c b/dummyflasher.c index cf4ca03..cbf1e49 100644 --- a/dummyflasher.c +++ b/dummyflasher.c @@ -969,7 +969,7 @@ .read = default_spi_read, .write_256 = dummy_spi_write_256, .shutdown = dummy_shutdown, - .probe_opcode = dummy_spi_probe_opcode, + .probe_opcode = &dummy_spi_probe_opcode, .delay = dummy_nop_delay, }; -- To view, visit https://review.coreboot.org/c/flashrom/+/83262?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: I8e5c9ea014d40a2e9e0621b25f8c404e80a79952 Gerrit-Change-Number: 83262 Gerrit-PatchSet: 1 Gerrit-Owner: Fabian Groffen <grobian(a)gentoo.org>

1 0

[XS] Change in flashrom[main]: libflashrom.map: remove non-existant functions
by Fabian Groffen (Code Review) 28 Jun '24

28 Jun '24

Fabian Groffen has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/83261?usp=email ) Change subject: libflashrom.map: remove non-existant functions ...................................................................... libflashrom.map: remove non-existant functions Remove symbol names from the map that do not exist in the code. https://bugs.gentoo.org/928955 Change-Id: I30bab842d9cbd2daaa9902fd3223f47145cb0e7f Signed-off-by: Fabian Groffen <grobian(a)gentoo.org> --- M libflashrom.map 1 file changed, 0 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/61/83261/1 diff --git a/libflashrom.map b/libflashrom.map index 77abf72..e1cdfa6 100644 --- a/libflashrom.map +++ b/libflashrom.map @@ -1,7 +1,5 @@ LIBFLASHROM_1.0 { global: - flashrom_board_info; - flashrom_chipset_info; flashrom_data_free; flashrom_flag_get; flashrom_flag_set; @@ -9,7 +7,6 @@ flashrom_flash_getsize; flashrom_flash_probe; flashrom_flash_release; - flashrom_flashchip_info; flashrom_image_read; flashrom_image_verify; flashrom_image_write; -- To view, visit https://review.coreboot.org/c/flashrom/+/83261?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: I30bab842d9cbd2daaa9902fd3223f47145cb0e7f Gerrit-Change-Number: 83261 Gerrit-PatchSet: 1 Gerrit-Owner: Fabian Groffen <grobian(a)gentoo.org>

1 0

[S] Change in flashrom[main]: how_to_add_new_chip: Add a section for feature bits and WRSR handling
by Hsuan-ting Chen (Code Review) 28 Jun '24

28 Jun '24

Attention is currently required from: Anastasia Klimchuk, Thomas Heijligen. Hsuan-ting Chen has posted comments on this change by Hsuan-ting Chen. ( https://review.coreboot.org/c/flashrom/+/82908?usp=email ) Change subject: how_to_add_new_chip: Add a section for feature bits and WRSR handling ...................................................................... Patch Set 2: (10 comments) Patchset: PS2: Thanks for the suggestions! File doc/contrib_howtos/how_to_add_new_chip.rst: https://review.coreboot.org/c/flashrom/+/82908/comment/0085c63d_1e94e19b?us… : PS1, Line 105: Feature Bits : ------------- > This can be on the same level as "Properties", especially because you have future plans to gradually […] Done https://review.coreboot.org/c/flashrom/+/82908/comment/57b8609c_1770d64c?us… : PS1, Line 108: The ``.feature_bits`` field in a chip definition encodes various features using a bitmask. : Here are some of the selected feature bits that need to be highlighted: > With this, we don't need an item in a list inside Properties. […] Done https://review.coreboot.org/c/flashrom/+/82908/comment/1a3333b7_a079cd5e?us… : PS1, Line 111: Write-Status-Register (WRSR) Handling : ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ > This header also goes on level up, use `-` Done https://review.coreboot.org/c/flashrom/+/82908/comment/c2b4d574_a09e6bf8?us… : PS1, Line 113: : ``FEATURE_WRSR_EWSR``, ``FEATURE_WRSR_WREN``, and ``FEATURE_WRSR_EITHER``. These bits used for **SPI only**. > I think this sentence is not needed. […] Done AFAIK it should be SPI only. Move the "SPI only" hints into the next section instead. https://review.coreboot.org/c/flashrom/+/82908/comment/98d08826_969aedc1?us… : PS1, Line 120: This > Delete "This", start with "Indicates that" Done I noticed that it actually doesn't jump to a newline after EWSR, e.g. ``` FEATURE_WRSR_EWSR indicates that we need an Enable-Write-Status-Register (EWSR) instruction which opens the status register for the immediately-followed next WRSR instruction. Usually, the opcode is 0x50. ``` So I used the "indicates" with lowercase and remove the ":" https://review.coreboot.org/c/flashrom/+/82908/comment/c85d39c7_8982b7d3?us… : PS1, Line 124: This > same Done https://review.coreboot.org/c/flashrom/+/82908/comment/74fae8b8_7f28dc8b?us… : PS1, Line 125: priort > typo, prior Done https://review.coreboot.org/c/flashrom/+/82908/comment/cef552ed_32a04ace?us… : PS1, Line 128: This > same Done https://review.coreboot.org/c/flashrom/+/82908/comment/09a6fb9b_ea72a571?us… : PS1, Line 110: : Write-Status-Register (WRSR) Handling : ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ : : ``FEATURE_WRSR_EWSR``, ``FEATURE_WRSR_WREN``, and ``FEATURE_WRSR_EITHER``. These bits used for **SPI only**. : : The Write Status Register (WRSR) is used to configure various settings within the flash chip, including write protection and : other features. The way WRSR is accessed varies between SPI flash chips, leading to the need for these feature bits. : : * ``FEATURE_WRSR_EWSR``: : This indicates that we need an **Enable-Write-Status-Register** (EWSR) instruction which opens the status register for the : immediately-followed next WRSR instruction. Usually, the opcode is **0x50**. : : * ``FEATURE_WRSR_WREN``: : This indicates that we need an **Write-Enable** (WREN) instruction to set the Write Enable Latch (WEL) bit. The WEL bit : must be set priort to every WRSR command. Usually, the opcode is **0x06**. : : * ``FEATURE_WRSR_EITHER``: : This indicates that either EWSR or WREN is supported in this chip. > Thank you for explaining! It's really good that I know your future plans. […] Done -- To view, visit https://review.coreboot.org/c/flashrom/+/82908?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: I34c20933a375380c8702f79ac637595cd3466000 Gerrit-Change-Number: 82908 Gerrit-PatchSet: 2 Gerrit-Owner: Hsuan-ting Chen <roccochen(a)google.com> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Hsuan Ting Chen <roccochen(a)chromium.org> Gerrit-Attention: Thomas Heijligen <src(a)posteo.de> Gerrit-Attention: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Comment-Date: Fri, 28 Jun 2024 10:12:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Hsuan-ting Chen <roccochen(a)google.com> Comment-In-Reply-To: Anastasia Klimchuk <aklm(a)chromium.org>

1 0

[S] Change in flashrom[main]: how_to_add_new_chip: Add a section for feature bits and WRSR handling
by Hsuan-ting Chen (Code Review) 28 Jun '24

28 Jun '24

Attention is currently required from: Hsuan-ting Chen, Thomas Heijligen. Hello Anastasia Klimchuk, Hsuan Ting Chen, Thomas Heijligen, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/flashrom/+/82908?usp=email to look at the new patch set (#2). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: how_to_add_new_chip: Add a section for feature bits and WRSR handling ...................................................................... how_to_add_new_chip: Add a section for feature bits and WRSR handling Feature bits are too complicated to understand if we only read the codes/datasheets. Add a new section in how_to_add_new_chip to add more details about each feature bits. Add the detailed explanation for WRSR handling first. If this new section looks good, I'll try to add some more sections in further commits. BUG=b:345154585 TEST=meson compile -C builddir and view the doc. Change-Id: I34c20933a375380c8702f79ac637595cd3466000 Signed-off-by: Hsuan Ting Chen <roccochen(a)chromium.org> --- M doc/contrib_howtos/how_to_add_new_chip.rst 1 file changed, 25 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/08/82908/2 -- To view, visit https://review.coreboot.org/c/flashrom/+/82908?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: I34c20933a375380c8702f79ac637595cd3466000 Gerrit-Change-Number: 82908 Gerrit-PatchSet: 2 Gerrit-Owner: Hsuan-ting Chen <roccochen(a)google.com> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Hsuan Ting Chen <roccochen(a)chromium.org> Gerrit-Attention: Hsuan-ting Chen <roccochen(a)google.com> Gerrit-Attention: Thomas Heijligen <src(a)posteo.de>

1 0

2025

2024

2023

2022

2021

2020

2019

2018

2017

flashrom-gerrit