flashrom-gerrit January 2025

flashrom-gerrit@flashrom.org

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[XS] Change in flashrom[main]: Update glasgow info on hardware overview
by Anastasia Klimchuk (Code Review) 11 Jan '25

11 Jan '25

Attention is currently required from: Cattus QQ. Anastasia Klimchuk has posted comments on this change by Cattus QQ. ( https://review.coreboot.org/c/flashrom/+/85929?usp=email ) Change subject: Update glasgow info on hardware overview ...................................................................... Patch Set 1: (5 comments) Patchset: PS1: thanks for the patch! I have few comments, below Commit Message: https://review.coreboot.org/c/flashrom/+/85929/comment/94ac167e_b367691d?us… : PS1, Line 6: : Update glasgow info on hardware overview We usually add a prefix to commit message, to give an idea which part of the code is changed, in this case the prefix would be `doc:` The title itself is all good, so the end result can be: `doc: Update glasgow info on hardware overview` File doc/supported_hw/supported_prog/serprog/overview.rst: https://review.coreboot.org/c/flashrom/+/85929/comment/9a7ea107_9858f8a8?us… : PS1, Line 98: ============== The underline only need to last for as long as the title last, so the remaining `=` can be removed. It doesn't change how webpage looks, but that's redundant chars https://review.coreboot.org/c/flashrom/+/85929/comment/5fad957c_424d7a15?us… : PS1, Line 105: The official website can be found here: `glasgow-embedded.org <https://glasgow-embedded.org>`_. It's up to you, but I just wanted to say: single new line in source .rst file does not produce a new line in html. So currently, the text from lines 103 to 107 is generated as one paragraph without new lines. If you would like to frame official website info, sources and examples with new lines (which is I think they deserve), you need to add 2 (two) new lines in the .rst source. File util/git-hooks/commit-msg: https://review.coreboot.org/c/flashrom/+/85929/comment/50f671d6_51fcdcf0?us… : PS1, Line 203: #exit 1 This shouldn't be in the patch? probably by mistake? did you have issues with git hook checker for sign off line? (I can see the patch has sign off line, good :) ) -- To view, visit https://review.coreboot.org/c/flashrom/+/85929?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: I8ac347d6061e354f249223e6fc26b86670e37be6 Gerrit-Change-Number: 85929 Gerrit-PatchSet: 1 Gerrit-Owner: Cattus QQ <cattusqq(a)gmail.com> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Cattus QQ <cattusqq(a)gmail.com> Gerrit-Comment-Date: Sat, 11 Jan 2025 07:50:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XS] Change in flashrom[main]: flashchips/micron: Not all N25QL256 support 4BA_WRITE
by Anastasia Klimchuk (Code Review) 09 Jan '25

09 Jan '25

Attention is currently required from: Nikolai Artemiev, Stefan Reinauer, garyodernichts(a)gmail.com. Anastasia Klimchuk has posted comments on this change by garyodernichts(a)gmail.com. ( https://review.coreboot.org/c/flashrom/+/85869?usp=email ) Change subject: flashchips/micron: Not all N25QL256 support 4BA_WRITE ...................................................................... Patch Set 1: (3 comments) Patchset: PS1: > Looking at this again, it might be better to add a separate flashchip entry for the N25Q256A, instea […] Thank you for your work! I agree with your idea, it is better to split. Those models which do support 4ba can take advantage of it, and the one who doesn't will have a separate chip definition. It seems to me, the new definition will go to `micron_numonyx_st.c` right? The thing to take care about is, eraseblocks ordering. If the new definition does not support 4ba, then first eraseblock for a given size should be 3ba (for example, 20h should be first and then 21h). I know this is not ideal and I want to fix, so that flashrom knows which erase opcodes correspond to 4ba vs 3ba - but at the moment it is what it is. Commit Message: https://review.coreboot.org/c/flashrom/+/85869/comment/9d2a30d6_64800319?us… : PS1, Line 13: Since there are other chips with the N25Q256 rdid (0xBA19), it is not safe to assume that all chips support 4BA_WRITE. : When testing this on a 25Q256, the 4BA_WRITE command behaved more like an erase by writing all 0xFFs. : With the patch, which is now using the default page program operation, it works fine. We wrap commit message by 72 chars width, could you please wrap the lines? https://flashrom.org/dev_guide/development_guide.html#commit-message-1 https://review.coreboot.org/c/flashrom/+/85869/comment/aec62b7e_2e4b1715?us… : PS1, Line 16: You can mention in commit message that the patch splits an entry into two (that was in the other comment thread), and also if you could add link to datasheet into a commit message, thanks! -- To view, visit https://review.coreboot.org/c/flashrom/+/85869?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: I3af103a99139705f6549369ed5af76a6197c3362 Gerrit-Change-Number: 85869 Gerrit-PatchSet: 1 Gerrit-Owner: garyodernichts(a)gmail.com Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Attention: garyodernichts(a)gmail.com Gerrit-Comment-Date: Thu, 09 Jan 2025 09:12:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: garyodernichts(a)gmail.com

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[XS] Change in flashrom[main]: flashchips/winbond: Update test status for Winbond W25Q256JV_M
by Anastasia Klimchuk (Code Review) 09 Jan '25

09 Jan '25

Attention is currently required from: Matt DeVillier, Nikolai Artemiev, Stefan Reinauer. Anastasia Klimchuk has posted comments on this change by Matt DeVillier. ( https://review.coreboot.org/c/flashrom/+/85896?usp=email ) Change subject: flashchips/winbond: Update test status for Winbond W25Q256JV_M ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/flashrom/+/85896?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: I48f37665c9578c4fdb360111f20958fbccc51a37 Gerrit-Change-Number: 85896 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Comment-Date: Thu, 09 Jan 2025 00:54:32 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in flashrom[main]: flashchips/winbond: Update test status for Winbond W25Q256JV_M
by Matt DeVillier (Code Review) 08 Jan '25

08 Jan '25

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/85896?usp=email ) Change subject: flashchips/winbond: Update test status for Winbond W25Q256JV_M ...................................................................... flashchips/winbond: Update test status for Winbond W25Q256JV_M Tested probe, read, erase, write, and WP operations on a Winbond W25Q256JV_M chip using internal and raiden_debug_spi programmers. Change-Id: I48f37665c9578c4fdb360111f20958fbccc51a37 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M flashchips/winbond.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/96/85896/1 diff --git a/flashchips/winbond.c b/flashchips/winbond.c index 6d46dcc..973bf2c 100644 --- a/flashchips/winbond.c +++ b/flashchips/winbond.c @@ -601,7 +601,7 @@ /* supports SFDP */ /* OTP: 1024B total, 256B reserved; read 0x48; write 0x42, erase 0x44, read ID 0x4B */ .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_4BA | FEATURE_WRSR2, - .tested = TEST_OK_PREW, + .tested = TEST_OK_PREWB, .probe = PROBE_SPI_RDID, .probe_timing = TIMING_ZERO, .block_erasers = -- To view, visit https://review.coreboot.org/c/flashrom/+/85896?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: I48f37665c9578c4fdb360111f20958fbccc51a37 Gerrit-Change-Number: 85896 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com>

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[M] Change in flashrom[main]: flashchips: Add Spansion S25FS512S
by Anastasia Klimchuk (Code Review) 08 Jan '25

08 Jan '25

Anastasia Klimchuk has submitted this change. ( https://review.coreboot.org/c/flashrom/+/85585?usp=email ) Change subject: flashchips: Add Spansion S25FS512S ...................................................................... flashchips: Add Spansion S25FS512S Tested probe, read, erase, write on FS512SAIF01 chips using Linux SPI and DediProg SF100 programmers. This change affects S25FL512S identification as well, so that both chips can be unambiguously detected by probing. Datasheets used: * Infineon-S25FS512S_512_Mb_1-DataSheet-v16_00-EN.pdf at https://www.infineon.com/dgdl/?fileId=8ac78c8c7d0d8da4017d0ed681a356fe * Infineon-S25FL512S_512_Mb_64_MB_FL-S_Flash_SPI_Multi-I_O_3-DataSheet-v21_00-EN.pdf at https://www.infineon.com/dgdl/?fileId=8ac78c8c7d0d8da4017d0ed046ae4b53 Change-Id: I40b6c081ec7d57eac4f6d2b69cea3878bc92bb47 Signed-off-by: Anton Samsonov <devel(a)zxlab.ru> Reviewed-on: https://review.coreboot.org/c/flashrom/+/85585 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm(a)chromium.org> --- M flashchips/spansion.c M include/flashchips.h M s25f.c 3 files changed, 52 insertions(+), 7 deletions(-) Approvals: build bot (Jenkins): Verified Anastasia Klimchuk: Looks good to me, approved diff --git a/flashchips/spansion.c b/flashchips/spansion.c index 09b2a4e..1a3c4cc 100644 --- a/flashchips/spansion.c +++ b/flashchips/spansion.c @@ -935,14 +935,14 @@ .name = "S25FL512S", .bustype = BUS_SPI, .manufacture_id = SPANSION_ID, - .model_id = SPANSION_S25FL512, + .model_id = SPANSION_S25FL512S_UL, .total_size = 65536, /* 512 Mb (=> 64 MB)) */ .page_size = 256, /* OTP: 1024B total, 32B reserved; read 0x4B; write 0x42 */ .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_4BA_NATIVE | FEATURE_4BA_ENTER_EAR7 | FEATURE_4BA_EAR_1716, .tested = TEST_UNTESTED, - .probe = PROBE_SPI_RDID, + .probe = PROBE_SPI_BIG_SPANSION, .probe_timing = TIMING_ZERO, .block_erasers = { @@ -1028,3 +1028,49 @@ .read = SPI_CHIP_READ, .voltage = {1700, 2000}, }, + + { + .vendor = "Spansion", + .name = "S25FS512S", + .bustype = BUS_SPI, + .manufacture_id = SPANSION_ID, + .model_id = SPANSION_S25FS512S_UL, + .total_size = 65536, + .page_size = 256, /* 256 or 512 bytes page programming buffer */ + /* OTP: 1024B total, 32B reserved; read 0x4B; write 0x42 */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_QPI | + FEATURE_4BA_NATIVE | FEATURE_4BA_ENTER, + /* Note on FEATURE_4BA_ENTER: the command set only defines command 0xB7 + to enter 4BA mode, but there is no counterpart command "Exit 4BA mode", + and the code 0xE9 is assigned to another command ("Password unlock"). */ + /* Note on FEATURE_4BA_ENTER_EAR7 (not set): the "Extended address mode" bit + is stored in configuration register CR2V[7], which can only be read / written + by generic commands ("Read any register" / "Write any register"), that itself + expect a 3- or 4-byte address of register in question, which in turn depends on + the same register, that is initially set from non-volatile register CR2NV[7] + that defaults to 0, but can be programmed to 1 for starting in 32-bit mode. */ + .tested = TEST_OK_PREW, + .probe = PROBE_SPI_BIG_SPANSION, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { { 256 * 1024, 256} }, + .block_erase = SPI_BLOCK_ERASE_DC, + }, { + .eraseblocks = { { 256 * 1024, 256} }, + .block_erase = SPI_BLOCK_ERASE_D8, + }, { + .eraseblocks = { { 65536 * 1024, 1} }, + .block_erase = SPI_BLOCK_ERASE_60, + }, { + .eraseblocks = { { 65536 * 1024, 1} }, + .block_erase = SPI_BLOCK_ERASE_C7, + } + }, + .printlock = SPI_PRETTYPRINT_STATUS_REGISTER_BP2_EP_SRWD, /* TODO: SR2 and many others */ + .unlock = SPI_DISABLE_BLOCKPROTECT_BP2_SRWD, /* TODO: various other locks */ + .write = SPI_CHIP_WRITE256, + .read = SPI_CHIP_READ, + .voltage = {1700, 2000}, + }, diff --git a/include/flashchips.h b/include/flashchips.h index 0fea690..556729c 100644 --- a/include/flashchips.h +++ b/include/flashchips.h @@ -701,7 +701,6 @@ #define SPANSION_S25FL064A 0x0216 /* Same as S25FL064P, but the latter supports EDI and CFI */ #define SPANSION_S25FL128 0x2018 /* Same ID for various S25FL127S, S25FL128P, S25FL128S and S25FL129P (including dual-die S70FL256P) variants (EDI supported) */ #define SPANSION_S25FL256 0x0219 -#define SPANSION_S25FL512 0x0220 #define SPANSION_S25FL204 0x4013 #define SPANSION_S25FL208 0x4014 #define SPANSION_S25FL216 0x4015 /* Same as S25FL216K, but the latter supports OTP, 3 status regs, quad I/O, SFDP etc. */ @@ -710,6 +709,7 @@ #define SPANSION_S25FL164K 0x4017 #define SPANSION_S25FL128L 0x6018 #define SPANSION_S25FL256L 0x6019 +#define SPANSION_S25FL512S_UL 0x02200080 /* Uniform Large (256kB) sectors */ #define SPANSION_S25FS128S_L 0x20180081 /* Large sectors. */ #define SPANSION_S25FS128S_S 0x20180181 /* Small sectors. */ #define SPANSION_S25FS256S_L 0x02190081 /* Large sectors. */ @@ -718,6 +718,7 @@ #define SPANSION_S25FL128S_US 0x20180180 /* Uniform Small (64kB) sectors */ #define SPANSION_S25FL256S_UL 0x02190080 /* Uniform Large (128kB) sectors */ #define SPANSION_S25FL256S_US 0x02190180 /* Uniform Small (64kB) sectors */ +#define SPANSION_S25FS512S_UL 0x02200081 /* Uniform Large (256kB) sectors */ /* Spansion 29GL families got a suffix indicating the process technology but share the same 3-Byte IDs. They can * however be differentiated by CFI byte 45h. Some versions exist which have special top or bottom boot sectors diff --git a/s25f.c b/s25f.c index b0f2438..dc90dc4 100644 --- a/s25f.c +++ b/s25f.c @@ -371,10 +371,8 @@ * * offset value meaning * 00h 01h Manufacturer ID for Spansion - * 01h 20h 128 Mb capacity - * 01h 02h 256 Mb capacity - * 02h 18h 128 Mb capacity - * 02h 19h 256 Mb capacity + * 01h * Memory interface type (02h, 20h, 40h, 60h) + * 02h * Memory capacity (18h = 128 Mb, 19h = 256 Mb, 20h = 512 Mb) * 03h 4Dh Full size of the RDID output (ignored) * 04h 00h FS: 256-kB physical sectors * 04h 01h FS: 64-kB physical sectors -- To view, visit https://review.coreboot.org/c/flashrom/+/85585?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: I40b6c081ec7d57eac4f6d2b69cea3878bc92bb47 Gerrit-Change-Number: 85585 Gerrit-PatchSet: 4 Gerrit-Owner: Anton Samsonov <avscomputing(a)gmail.com> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Anton Samsonov <devel(a)zxlab.ru> Gerrit-Reviewer: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in flashrom[main]: flashchips/micron: Not all N25QL256 support 4BA_WRITE
by Name of user not set (Code Review) 06 Jan '25

06 Jan '25

Attention is currently required from: Anastasia Klimchuk, Nikolai Artemiev, Stefan Reinauer. garyodernichts(a)gmail.com has posted comments on this change by garyodernichts(a)gmail.com. ( https://review.coreboot.org/c/flashrom/+/85869?usp=email ) Change subject: flashchips/micron: Not all N25QL256 support 4BA_WRITE ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: Looking at this again, it might be better to add a separate flashchip entry for the N25Q256A, instead of removing 4BA_WRITE for the MT25Q256A. Even though as far as I know they're drop-in replacements for each other. For the record this is the datasheet I was referencing: https://mm.digikey.com/Volume0/opasdata/d220001/medias/docus/789/N25Q256A.p… -- To view, visit https://review.coreboot.org/c/flashrom/+/85869?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: I3af103a99139705f6549369ed5af76a6197c3362 Gerrit-Change-Number: 85869 Gerrit-PatchSet: 1 Gerrit-Owner: garyodernichts(a)gmail.com Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Attention: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Comment-Date: Mon, 06 Jan 2025 20:48:20 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XS] Change in flashrom[main]: flashchips/micron: Not all N25QL256 support 4BA_WRITE
by Name of user not set (Code Review) 06 Jan '25

06 Jan '25

garyodernichts(a)gmail.com has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/85869?usp=email ) Change subject: flashchips/micron: Not all N25QL256 support 4BA_WRITE ...................................................................... flashchips/micron: Not all N25QL256 support 4BA_WRITE According to the Micron N25Q256A 3V datasheet: > This command is only for part numbers N25Q256A83ESF40x, N25Q256A83E1240x, and N25Q256A83ESFA0F. Since there are other chips with the N25Q256 rdid (0xBA19), it is not safe to assume that all chips support 4BA_WRITE. When testing this on a 25Q256, the 4BA_WRITE command behaved more like an erase by writing all 0xFFs. With the patch, which is now using the default page program operation, it works fine. Change-Id: I3af103a99139705f6549369ed5af76a6197c3362 Signed-off-by: GaryOderNichts <garyodernichts(a)gmail.com> --- M flashchips/micron.c 1 file changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/69/85869/1 diff --git a/flashchips/micron.c b/flashchips/micron.c index 5b49892..08b3521 100644 --- a/flashchips/micron.c +++ b/flashchips/micron.c @@ -292,7 +292,8 @@ .page_size = 256, /* supports SFDP */ /* OTP: 64B total; read 0x4B, write 0x42 */ - .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_4BA_WREN, + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_4BA_ENTER_WREN | + FEATURE_4BA_EAR_C5C8 | FEATURE_4BA_READ | FEATURE_4BA_FAST_READ, .tested = TEST_OK_PREW, .probe = PROBE_SPI_RDID, .probe_timing = TIMING_ZERO, -- To view, visit https://review.coreboot.org/c/flashrom/+/85869?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: I3af103a99139705f6549369ed5af76a6197c3362 Gerrit-Change-Number: 85869 Gerrit-PatchSet: 1 Gerrit-Owner: garyodernichts(a)gmail.com

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