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Change subject: Provide an option to use PCI_ACCESS_ECAM to access pci register
......................................................................
Patch Set 3:
(1 comment)
File meson_options.txt:
https://review.coreboot.org/c/flashrom/+/83896/comment/d341e2b2_0241c83c?us… :
PS3, Line 9: option('use_libpci_ecam', type : 'boolean', value : false)
> It looks like this is only used for 100-series PCHs which presumably always support ECAM, so is this […]
My original thought is to avoid any potential impact since i only have chromebooks to verify.
if it's ok to use ECAM directly, i can remove this option.
thank you
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Change subject: Provide an option to use PCI_ACCESS_ECAM to access pci register
......................................................................
Patch Set 3:
(1 comment)
File meson_options.txt:
https://review.coreboot.org/c/flashrom/+/83896/comment/e7d5df65_be4f737e?us… :
PS3, Line 9: option('use_libpci_ecam', type : 'boolean', value : false)
It looks like this is only used for 100-series PCHs which presumably always support ECAM, so is this option needed?
It seems like if we can assume ECAM is always available on the relevant systems and it's less prone to bugs caused by libpci interacting poorly with OS-level drivers accessing the same hardware, then we should use ECAM as long as it's supported by the version of libpci in use and don't need this option.
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Miklós Márton has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/83921?usp=email )
Change subject: [stlinkv3_spi]Mark STLinkV3-Mini not working
......................................................................
[stlinkv3_spi]Mark STLinkV3-Mini not working
The STLinkV3 Mini does not support the bridge API,
it return LIBUSB_IO_ERROR when querying
the bridge version. The official ST updater does
not lists the bridge version in the info screen.
Due to it's construction (additional connector on the
bottom) it is likely that ST disabled the bridge functions
on the castellated pads.
Change-Id: Ic1ea4ca7acedca5d374cff8fcef450c18e55a9e8
Signed-off-by: Miklos Marton <martonmiklosqdev(a)gmail.com>
---
M stlinkv3_spi.c
1 file changed, 7 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/21/83921/1
diff --git a/stlinkv3_spi.c b/stlinkv3_spi.c
index f9046df..d1de1dd 100644
--- a/stlinkv3_spi.c
+++ b/stlinkv3_spi.c
@@ -115,7 +115,7 @@
#define USB_TIMEOUT_IN_MS 5000
static const struct dev_entry devs_stlinkv3_spi[] = {
- {0x0483, 0x374E, NT, "STMicroelectronics", "STLINK-V3E"},
+ {0x0483, 0x374E, BAD, "STMicroelectronics", "STLINK-V3E"},
{0x0483, 0x374F, OK, "STMicroelectronics", "STLINK-V3S"},
{0x0483, 0x3753, OK, "STMicroelectronics", "STLINK-V3 dual VCP"},
{0x0483, 0x3754, NT, "STMicroelectronics", "STLINK-V3 no MSD"},
@@ -498,8 +498,13 @@
devs_stlinkv3_spi[devIndex].vendor_id,
devs_stlinkv3_spi[devIndex].device_id,
param_str);
- if (stlinkv3_handle)
+ if (stlinkv3_handle) {
+ if (devs_stlinkv3_spi[devIndex].status == BAD) {
+ msg_perr("The STLINK-V3 Mini/MiniE does not support the bridge interface\n");
+ goto init_err_exit;
+ }
break;
+ }
devIndex++;
}
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Change subject: Provide an option to use PCI_ACCESS_ECAM to access pci register
......................................................................
Patch Set 3: Code-Review+1
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Change subject: Provide an option to use PCI_ACCESS_ECAM to access pci register
......................................................................
Patch Set 3:
This change is ready for review.
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Anastasia Klimchuk has submitted this change. ( https://review.coreboot.org/c/flashrom/+/83852?usp=email )
Change subject: flashrom.c: Rename {erase|write}_by_layout_new as the only one
......................................................................
flashrom.c: Rename {erase|write}_by_layout_new as the only one
We used to have two code paths for erase and write, so we had
{erase|write}_by_layout in two variants: *_new and *_legacy.
Now that legacy is removed, *_new can be renamed without *_new
suffix.
Change-Id: Ib21bf29e1993c4fc0516e76fde2ad283eedb50d2
Signed-off-by: Anastasia Klimchuk <aklm(a)flashrom.org>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/83852
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Aarya <aarya.chaumal(a)gmail.com>
Reviewed-by: Peter Marheine <pmarheine(a)chromium.org>
---
M flashrom.c
1 file changed, 2 insertions(+), 14 deletions(-)
Approvals:
Aarya: Looks good to me, approved
build bot (Jenkins): Verified
Peter Marheine: Looks good to me, approved
diff --git a/flashrom.c b/flashrom.c
index 453a2bf..01a41c4 100644
--- a/flashrom.c
+++ b/flashrom.c
@@ -1327,7 +1327,7 @@
return ret;
}
-static int erase_by_layout_new(struct flashctx *const flashctx)
+static int erase_by_layout(struct flashctx *const flashctx)
{
bool all_skipped = true;
const uint32_t flash_size = flashctx->chip->total_size * 1024;
@@ -1370,12 +1370,7 @@
return ret;
}
-static int erase_by_layout(struct flashctx *const flashctx)
-{
- return erase_by_layout_new(flashctx);
-}
-
-static int write_by_layout_new(struct flashctx *const flashctx,
+static int write_by_layout(struct flashctx *const flashctx,
void *const curcontents, const void *const newcontents,
bool *all_skipped)
{
@@ -1410,13 +1405,6 @@
return ret;
}
-static int write_by_layout(struct flashctx *const flashctx,
- uint8_t *const curcontents, const uint8_t *const newcontents,
- bool *all_skipped)
-{
- return write_by_layout_new(flashctx, curcontents, newcontents, all_skipped);
-}
-
/**
* @brief Compares the included layout regions with content from a buffer.
*
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Change subject: flashchips: add support for MX77U51250F chip
......................................................................
Patch Set 4: Code-Review+2
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