May 2024 - flashrom-gerrit - mail.coreboot.org

[M] Change in flashrom[main]: ch347_spi: Add driver support for CH347F packaging
by ZhiYuanNJ (Code Review) 31 May '24

31 May '24

Attention is currently required from: Paul Menzel. ZhiYuanNJ has posted comments on this change by ZhiYuanNJ. ( https://review.coreboot.org/c/flashrom/+/82193?usp=email ) Change subject: ch347_spi: Add driver support for CH347F packaging ...................................................................... Patch Set 13: (1 comment) Patchset: PS13: My SUBMIT button is in an unreachable state, prompting:You don't have permission to submit change 82193 Is this a normal phenomenon? -- To view, visit https://review.coreboot.org/c/flashrom/+/82193?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: I693baf1a0d9dc20757f56fba626b5f5ad20f71dd Gerrit-Change-Number: 82193 Gerrit-PatchSet: 13 Gerrit-Owner: ZhiYuanNJ Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Fri, 31 May 2024 02:29:42 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XS] Change in flashrom[main]: Add clarification to struct flash_region on chipoff_t
by Peter Marheine (Code Review) 31 May '24

31 May '24

Peter Marheine has submitted this change. ( https://review.coreboot.org/c/flashrom/+/82677?usp=email ) ( 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: Add clarification to struct flash_region on chipoff_t ...................................................................... Add clarification to struct flash_region on chipoff_t Although chipoff_t is fairly clearly documented on its own, it seems fairly frequent that developers will treat the end address of a flash region as an exclusive upper bound rather than the inclusive one it should be; for example CB:82496 fixes an incorrect use that affected multiple sites, and CB:73571 stemmed from a similar cause. Add a clarifying comment to call attention to this, to help programmers avoid making similar mistakes in the future. Change-Id: I80b61a87ca31bd5a116224aadb4e211ee6841e1f Signed-off-by: Peter Marheine <pmarheine(a)chromium.org> Reviewed-on: https://review.coreboot.org/c/flashrom/+/82677 Reviewed-by: Hsuan-ting Chen <roccochen(a)google.com> Reviewed-by: Anastasia Klimchuk <aklm(a)chromium.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M include/layout.h 1 file changed, 5 insertions(+), 0 deletions(-) Approvals: Anastasia Klimchuk: Looks good to me, approved build bot (Jenkins): Verified Hsuan-ting Chen: Looks good to me, but someone else must approve diff --git a/include/layout.h b/include/layout.h index 5614bea..d03a15b 100644 --- a/include/layout.h +++ b/include/layout.h @@ -37,6 +37,11 @@ struct flash_region { char *name; + /* + * Note that because start and end are chipoff_t, end is an inclusive upper + * bound: the length of a region is (end - start + 1) bytes and it is + * impossible to represent a region with zero length. + */ chipoff_t start; chipoff_t end; bool read_prot; -- To view, visit https://review.coreboot.org/c/flashrom/+/82677?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: I80b61a87ca31bd5a116224aadb4e211ee6841e1f Gerrit-Change-Number: 82677 Gerrit-PatchSet: 3 Gerrit-Owner: Peter Marheine <pmarheine(a)chromium.org> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Hsuan-ting Chen <roccochen(a)google.com> Gerrit-Reviewer: Peter Marheine <pmarheine(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[M] Change in flashrom[main]: tests/erase: record the opcode for each erase
by Peter Marheine (Code Review) 31 May '24

31 May '24

Peter Marheine has submitted this change. ( https://review.coreboot.org/c/flashrom/+/82251?usp=email ) Change subject: tests/erase: record the opcode for each erase ...................................................................... tests/erase: record the opcode for each erase This allows tests to verify that the correct opcode is used when erasing, which is required to unit-test the fix to issue #525 where in some situations an incorrect erase opcode will be used. BUG=https://ticket.coreboot.org/issues/525 Change-Id: I3983fe42c2e7f06668a1bd20d2db7fafa93b8043 Signed-off-by: Peter Marheine <pmarheine(a)chromium.org> Reviewed-on: https://review.coreboot.org/c/flashrom/+/82251 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm(a)chromium.org> --- M flashrom.c M include/flash.h M tests/chip.c M tests/erase_func_algo.c M tests/meson.build 5 files changed, 157 insertions(+), 58 deletions(-) Approvals: Anastasia Klimchuk: Looks good to me, approved build bot (Jenkins): Verified diff --git a/flashrom.c b/flashrom.c index a365303..a056929 100644 --- a/flashrom.c +++ b/flashrom.c @@ -402,8 +402,10 @@ return 0; } -/* special unit-test hook */ -erasefunc_t *g_test_erase_injector; +#ifdef FLASHROM_TEST +/* special unit-test hooks */ +erasefunc_t *g_test_erase_injector[NUM_TEST_ERASE_INJECTORS]; +#endif erasefunc_t *lookup_erase_func_ptr(const struct block_eraser *const eraser) { @@ -442,7 +444,14 @@ case ERASE_SECTOR_49LFXXXC: return &erase_sector_49lfxxxc; case STM50_SECTOR_ERASE: return &erase_sector_stm50; // TODO rename to &stm50_sector_erase; case EDI_CHIP_BLOCK_ERASE: return &edi_chip_block_erase; - case TEST_ERASE_INJECTOR: return g_test_erase_injector; +#ifdef FLASHROM_TEST + case TEST_ERASE_INJECTOR_1: + case TEST_ERASE_INJECTOR_2: + case TEST_ERASE_INJECTOR_3: + case TEST_ERASE_INJECTOR_4: + case TEST_ERASE_INJECTOR_5: + return g_test_erase_injector[eraser->block_erase - TEST_ERASE_INJECTOR_1]; +#endif /* default: total function, 0 indicates no erase function set. * We explicitly do not want a default catch-all case in the switch * to ensure unhandled enum's are compiler warnings. @@ -540,8 +549,10 @@ return ret; } +#ifdef FLASHROM_TEST /* special unit-test hook */ read_func_t *g_test_read_injector; +#endif static read_func_t *lookup_read_func_ptr(const struct flashchip *chip) { @@ -552,7 +563,9 @@ case EDI_CHIP_READ: return &edi_chip_read; case SPI_READ_AT45DB: return spi_read_at45db; case SPI_READ_AT45DB_E8: return spi_read_at45db_e8; +#ifdef FLASHROM_TEST case TEST_READ_INJECTOR: return g_test_read_injector; +#endif /* default: total function, 0 indicates no read function set. * We explicitly do not want a default catch-all case in the switch * to ensure unhandled enum's are compiler warnings. @@ -976,7 +989,9 @@ } /* special unit-test hook */ +#ifdef FLASHROM_TEST write_func_t *g_test_write_injector; +#endif static write_func_t *lookup_write_func_ptr(const struct flashchip *chip) { @@ -992,7 +1007,9 @@ case WRITE_82802AB: return &write_82802ab; case WRITE_EN29LV640B: return &write_en29lv640b; case EDI_CHIP_WRITE: return &edi_chip_write; +#ifdef FLASHROM_TEST case TEST_WRITE_INJECTOR: return g_test_write_injector; +#endif /* default: total function, 0 indicates no write function set. * We explicitly do not want a default catch-all case in the switch * to ensure unhandled enum's are compiler warnings. diff --git a/include/flash.h b/include/flash.h index 284461e..aa89409 100644 --- a/include/flash.h +++ b/include/flash.h @@ -266,10 +266,16 @@ WRITE_82802AB, WRITE_EN29LV640B, EDI_CHIP_WRITE, +#ifdef FLASHROM_TEST TEST_WRITE_INJECTOR, /* special case must come last. */ +#endif }; typedef int (write_func_t)(struct flashctx *flash, const uint8_t *buf, unsigned int start, unsigned int len); +#ifdef FLASHROM_TEST +extern write_func_t *g_test_write_injector; +#endif + enum read_func { NO_READ_FUNC = 0, /* 0 indicates no read function set. */ SPI_CHIP_READ = 1, @@ -278,11 +284,17 @@ EDI_CHIP_READ, SPI_READ_AT45DB, SPI_READ_AT45DB_E8, +#ifdef FLASHROM_TEST TEST_READ_INJECTOR, /* special case must come last. */ +#endif }; typedef int (read_func_t)(struct flashctx *flash, uint8_t *buf, unsigned int start, unsigned int len); int read_flash(struct flashctx *flash, uint8_t *buf, unsigned int start, unsigned int len); +#ifdef FLASHROM_TEST +extern read_func_t *g_test_read_injector; +#endif + enum block_erase_func { NO_BLOCK_ERASE_FUNC = 0, /* 0 indicates no block erase function set. */ SPI_BLOCK_ERASE_EMULATION = 1, @@ -319,9 +331,21 @@ ERASE_SECTOR_49LFXXXC, STM50_SECTOR_ERASE, EDI_CHIP_BLOCK_ERASE, - TEST_ERASE_INJECTOR, /* special case must come last. */ +#ifdef FLASHROM_TEST + /* special cases must come last. */ + TEST_ERASE_INJECTOR_1, + TEST_ERASE_INJECTOR_2, + TEST_ERASE_INJECTOR_3, + TEST_ERASE_INJECTOR_4, + TEST_ERASE_INJECTOR_5, +#endif }; +#ifdef FLASHROM_TEST +#define NUM_TEST_ERASE_INJECTORS 5 +extern erasefunc_t *g_test_erase_injector[NUM_TEST_ERASE_INJECTORS]; +#endif + enum blockprotect_func { NO_BLOCKPROTECT_FUNC = 0, /* 0 indicates no unlock function set. */ SPI_DISABLE_BLOCKPROTECT, diff --git a/tests/chip.c b/tests/chip.c index 96be7b1..3e1ae3b 100644 --- a/tests/chip.c +++ b/tests/chip.c @@ -118,10 +118,6 @@ io_mock_register(NULL); } -extern write_func_t *g_test_write_injector; -extern read_func_t *g_test_read_injector; -extern erasefunc_t *g_test_erase_injector; - static const struct flashchip chip_8MiB = { .vendor = "aklm", .total_size = MOCK_CHIP_SIZE / KiB, @@ -132,7 +128,7 @@ {{ /* All blocks within total size of the chip. */ .eraseblocks = { {2 * MiB, 4} }, - .block_erase = TEST_ERASE_INJECTOR, + .block_erase = TEST_ERASE_INJECTOR_1, }}, }; @@ -179,7 +175,7 @@ g_test_write_injector = write_chip; g_test_read_injector = read_chip; - g_test_erase_injector = block_erase_chip; + g_test_erase_injector[0] = block_erase_chip; struct flashrom_flashctx flashctx = { 0 }; struct flashrom_layout *layout; struct flashchip mock_chip = chip_8MiB; @@ -238,7 +234,7 @@ g_test_write_injector = write_chip; g_test_read_injector = read_chip; - g_test_erase_injector = block_erase_chip; + g_test_erase_injector[0] = block_erase_chip; struct flashrom_flashctx flashctx = { 0 }; struct flashrom_layout *layout; struct flashchip mock_chip = chip_8MiB; @@ -313,7 +309,7 @@ g_test_write_injector = write_chip; g_test_read_injector = read_chip; - g_test_erase_injector = block_erase_chip; + g_test_erase_injector[0] = block_erase_chip; struct flashrom_flashctx flashctx = { 0 }; struct flashrom_layout *layout; struct flashchip mock_chip = chip_8MiB; @@ -504,7 +500,7 @@ g_test_write_injector = write_chip; g_test_read_injector = read_chip; - g_test_erase_injector = block_erase_chip; + g_test_erase_injector[0] = block_erase_chip; struct flashrom_flashctx flashctx = { 0 }; struct flashrom_layout *layout; struct flashchip mock_chip = chip_8MiB; diff --git a/tests/erase_func_algo.c b/tests/erase_func_algo.c index ed9eb04..b0969c2 100644 --- a/tests/erase_func_algo.c +++ b/tests/erase_func_algo.c @@ -39,6 +39,7 @@ struct erase_invoke { unsigned int blockaddr; unsigned int blocklen; + enum block_erase_func erase_func; }; struct test_case { @@ -82,16 +83,17 @@ return 0; } -static int block_erase_chip(struct flashctx *flash, unsigned int blockaddr, unsigned int blocklen) +static int block_erase_chip_tagged(struct flashctx *flash, enum block_erase_func erase_func, unsigned int blockaddr, unsigned int blocklen) { if (blockaddr + blocklen <= MOCK_CHIP_SIZE) { LOG_ERASE_FUNC; /* Register eraseblock invocation. */ - g_state.eraseblocks_actual[g_state.eraseblocks_actual_ind].blocklen - = blocklen; - g_state.eraseblocks_actual[g_state.eraseblocks_actual_ind].blockaddr - = blockaddr; + g_state.eraseblocks_actual[g_state.eraseblocks_actual_ind] = (struct erase_invoke){ + .blocklen = blocklen, + .blockaddr = blockaddr, + .erase_func = erase_func, + }; g_state.eraseblocks_actual_ind++; } @@ -101,10 +103,6 @@ return 0; } -extern write_func_t *g_test_write_injector; -extern read_func_t *g_test_read_injector; -extern erasefunc_t *g_test_erase_injector; - static struct flashchip chip_1_2_4_8_16 = { .vendor = "aklm", /* @@ -127,19 +125,19 @@ { { .eraseblocks = { {1, MIN_REAL_CHIP_SIZE} }, - .block_erase = TEST_ERASE_INJECTOR, + .block_erase = TEST_ERASE_INJECTOR_1, }, { .eraseblocks = { {2, MIN_REAL_CHIP_SIZE / 2} }, - .block_erase = TEST_ERASE_INJECTOR, + .block_erase = TEST_ERASE_INJECTOR_2, }, { .eraseblocks = { {4, MIN_REAL_CHIP_SIZE / 4} }, - .block_erase = TEST_ERASE_INJECTOR, + .block_erase = TEST_ERASE_INJECTOR_3, }, { .eraseblocks = { {8, MIN_REAL_CHIP_SIZE / 8} }, - .block_erase = TEST_ERASE_INJECTOR, + .block_erase = TEST_ERASE_INJECTOR_4, }, { .eraseblocks = { {16, MIN_REAL_CHIP_SIZE / 16} }, - .block_erase = TEST_ERASE_INJECTOR, + .block_erase = TEST_ERASE_INJECTOR_5, } }, }; @@ -156,13 +154,13 @@ { { .eraseblocks = { {1, MIN_REAL_CHIP_SIZE} }, - .block_erase = TEST_ERASE_INJECTOR, + .block_erase = TEST_ERASE_INJECTOR_1, }, { .eraseblocks = { {8, MIN_REAL_CHIP_SIZE / 8} }, - .block_erase = TEST_ERASE_INJECTOR, + .block_erase = TEST_ERASE_INJECTOR_4, }, { .eraseblocks = { {16, MIN_REAL_CHIP_SIZE / 16} }, - .block_erase = TEST_ERASE_INJECTOR, + .block_erase = TEST_ERASE_INJECTOR_5, } }, }; @@ -179,20 +177,41 @@ { { .eraseblocks = { {8, MIN_REAL_CHIP_SIZE / 8} }, - .block_erase = TEST_ERASE_INJECTOR, + .block_erase = TEST_ERASE_INJECTOR_4, }, { .eraseblocks = { {16, MIN_REAL_CHIP_SIZE / 16} }, - .block_erase = TEST_ERASE_INJECTOR, + .block_erase = TEST_ERASE_INJECTOR_5, } }, }; +#define BLOCK_ERASE_FUNC(n) \ + static int block_erase_chip_ ## n (struct flashctx *flash, unsigned int blockaddr, unsigned int blocklen) { \ + return block_erase_chip_tagged(flash, TEST_ERASE_INJECTOR_ ## n, blockaddr, blocklen); \ + } +BLOCK_ERASE_FUNC(1) +BLOCK_ERASE_FUNC(2) +BLOCK_ERASE_FUNC(3) +BLOCK_ERASE_FUNC(4) +BLOCK_ERASE_FUNC(5) + static void setup_chip(struct flashrom_flashctx *flashctx, struct flashrom_layout **layout, const char *programmer_param, struct test_case *current_test_case) { g_test_write_injector = write_chip; g_test_read_injector = read_chip; - g_test_erase_injector = block_erase_chip; + /* Each erasefunc corresponds to an operation that erases a block of + * the chip with a particular size in bytes. */ + memcpy(g_test_erase_injector, + (erasefunc_t *const[]){ + block_erase_chip_1, // 1 byte + block_erase_chip_2, // 2 bytes + block_erase_chip_3, // 4 bytes + block_erase_chip_4, // 8 bytes + block_erase_chip_5, // 16 bytes + }, + sizeof(g_test_erase_injector) + ); /* First MOCK_CHIP_SIZE bytes have a meaning and set with given values for this test case. */ memcpy(g_state.buf, current_test_case->initial_buf, MOCK_CHIP_SIZE); @@ -271,7 +290,7 @@ ERASE_VALUE, ERASE_VALUE, ERASE_VALUE, ERASE_VALUE}, .written_buf = {0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f}, - .eraseblocks_expected = {{0x0, 0x10}}, + .eraseblocks_expected = {{0x0, 0x10, TEST_ERASE_INJECTOR_5}}, .eraseblocks_expected_ind = 1, .erase_test_name = "Erase test case #0", .write_test_name = "Write test case #0", @@ -293,7 +312,7 @@ ERASE_VALUE, ERASE_VALUE, ERASE_VALUE, ERASE_VALUE}, .written_buf = {0xf0, 0xf1, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7, 0xf8, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f}, - .eraseblocks_expected = {{0x8, 0x8}, {0x0, 0x8}}, + .eraseblocks_expected = {{0x8, 0x8, TEST_ERASE_INJECTOR_4}, {0x0, 0x8, TEST_ERASE_INJECTOR_4}}, .eraseblocks_expected_ind = 2, .erase_test_name = "Erase test case #1", .write_test_name = "Write test case #1", @@ -315,7 +334,13 @@ ERASE_VALUE, ERASE_VALUE, ERASE_VALUE, ERASE_VALUE}, .written_buf = {0xff, 0xff, 0x0, 0xff, 0x0, 0xff, 0x20, 0x2f, 0x20, 0x2f, 0x0, 0xff, 0xff, 0xff, 0x2f, 0x2f}, - .eraseblocks_expected = {{0xb, 0x1}, {0xc, 0x4}, {0xa, 0x1}, {0x8, 0x2}, {0x0, 0x8}}, + .eraseblocks_expected = { + {0xb, 0x1, TEST_ERASE_INJECTOR_1}, + {0xc, 0x4, TEST_ERASE_INJECTOR_3}, + {0xa, 0x1, TEST_ERASE_INJECTOR_1}, + {0x8, 0x2, TEST_ERASE_INJECTOR_2}, + {0x0, 0x8, TEST_ERASE_INJECTOR_4} + }, .eraseblocks_expected_ind = 5, .erase_test_name = "Erase test case #2", .write_test_name = "Write test case #2", @@ -337,7 +362,7 @@ ERASE_VALUE, ERASE_VALUE, ERASE_VALUE, ERASE_VALUE}, .written_buf = {0xff, 0xff, 0xff, 0xff, 0x1, 0x2, 0x3, 0x4, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .eraseblocks_expected = {{0x0, 0x10}}, + .eraseblocks_expected = {{0x0, 0x10, TEST_ERASE_INJECTOR_5}}, .eraseblocks_expected_ind = 1, .erase_test_name = "Erase test case #3", .write_test_name = "Write test case #3", @@ -359,7 +384,7 @@ ERASE_VALUE, ERASE_VALUE, ERASE_VALUE, ERASE_VALUE}, .written_buf = {0x11, 0x22, 0x33, 0x44, 0xff, 0xff, 0xff, 0xff, 0xa1, 0xa2, 0xa3, 0xa4, 0xa5, 0xa6, 0xa7, 0xa8}, - .eraseblocks_expected = {{0x0, 0x10}}, + .eraseblocks_expected = {{0x0, 0x10, TEST_ERASE_INJECTOR_5}}, .eraseblocks_expected_ind = 1, .erase_test_name = "Erase test case #4", .write_test_name = "Write test case #4", @@ -381,7 +406,7 @@ ERASE_VALUE, ERASE_VALUE, ERASE_VALUE, ERASE_VALUE}, .written_buf = {0x11, 0x22, 0x33, 0x44, 0x55, 0x66, 0x77, 0xff, 0xa1, 0xa2, 0xa3, 0xa4, 0xa5, 0xa6, 0xa7, 0xa8}, - .eraseblocks_expected = {{0x0, 0x10}}, + .eraseblocks_expected = {{0x0, 0x10, TEST_ERASE_INJECTOR_5}}, .eraseblocks_expected_ind = 1, .erase_test_name = "Erase test case #5", .write_test_name = "Write test case #5", @@ -403,7 +428,7 @@ ERASE_VALUE, ERASE_VALUE, ERASE_VALUE, ERASE_VALUE}, .written_buf = {0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, 0xdd, 0xa1, 0xa2, 0xa3, 0xa4, 0xa5, 0xa6, 0xa7, 0xa8}, - .eraseblocks_expected = {{0x0, 0x10}}, + .eraseblocks_expected = {{0x0, 0x10, TEST_ERASE_INJECTOR_5}}, .eraseblocks_expected_ind = 1, .erase_test_name = "Erase test case #6", .write_test_name = "Write test case #6", @@ -425,8 +450,16 @@ ERASE_VALUE, ERASE_VALUE, ERASE_VALUE, ERASE_VALUE}, .written_buf = {0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f}, - .eraseblocks_expected = {{0xf, 0x1}, {0xe, 0x1}, {0xc, 0x2}, {0x8, 0x4}, - {0x3, 0x1}, {0x4, 0x4}, {0x2, 0x1}, {0x0, 0x2}}, + .eraseblocks_expected = { + {0xf, 0x1, TEST_ERASE_INJECTOR_1}, + {0xe, 0x1, TEST_ERASE_INJECTOR_1}, + {0xc, 0x2, TEST_ERASE_INJECTOR_2}, + {0x8, 0x4, TEST_ERASE_INJECTOR_3}, + {0x3, 0x1, TEST_ERASE_INJECTOR_1}, + {0x4, 0x4, TEST_ERASE_INJECTOR_3}, + {0x2, 0x1, TEST_ERASE_INJECTOR_1}, + {0x0, 0x2, TEST_ERASE_INJECTOR_2} + }, .eraseblocks_expected_ind = 8, .erase_test_name = "Erase test case #7", .write_test_name = "Write test case #7", @@ -448,7 +481,7 @@ ERASE_VALUE, ERASE_VALUE, ERASE_VALUE, ERASE_VALUE}, .written_buf = {0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f}, - .eraseblocks_expected = {{0x0, 0x10}}, + .eraseblocks_expected = {{0x0, 0x10, TEST_ERASE_INJECTOR_5}}, .eraseblocks_expected_ind = 1, .erase_test_name = "Erase test case #8", .write_test_name = "Write test case #8", @@ -471,7 +504,7 @@ ERASE_VALUE, ERASE_VALUE, ERASE_VALUE, ERASE_VALUE}, .written_buf = {0xf0, 0xf1, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7, 0xf8, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f}, - .eraseblocks_expected = {{0x8, 0x8}, {0x0, 0x8}}, + .eraseblocks_expected = {{0x8, 0x8, TEST_ERASE_INJECTOR_4}, {0x0, 0x8, TEST_ERASE_INJECTOR_4}}, .eraseblocks_expected_ind = 2, .erase_test_name = "Erase test case #9", .write_test_name = "Write test case #9", @@ -493,8 +526,17 @@ ERASE_VALUE, ERASE_VALUE, ERASE_VALUE, ERASE_VALUE}, .written_buf = {0xff, 0xff, 0x0, 0xff, 0x0, 0xff, 0x20, 0x2f, 0x20, 0x2f, 0x0, 0xff, 0xff, 0xff, 0x2f, 0x2f}, - .eraseblocks_expected = {{0xb, 0x1}, {0xc, 0x1}, {0xd, 0x1}, {0xe, 0x1}, - {0xf, 0x1}, {0x8, 0x1}, {0x9, 0x1}, {0xa, 0x1}, {0x0, 0x8}}, + .eraseblocks_expected = { + {0xb, 0x1, TEST_ERASE_INJECTOR_1}, + {0xc, 0x1, TEST_ERASE_INJECTOR_1}, + {0xd, 0x1, TEST_ERASE_INJECTOR_1}, + {0xe, 0x1, TEST_ERASE_INJECTOR_1}, + {0xf, 0x1, TEST_ERASE_INJECTOR_1}, + {0x8, 0x1, TEST_ERASE_INJECTOR_1}, + {0x9, 0x1, TEST_ERASE_INJECTOR_1}, + {0xa, 0x1, TEST_ERASE_INJECTOR_1}, + {0x0, 0x8, TEST_ERASE_INJECTOR_4} + }, .eraseblocks_expected_ind = 9, .erase_test_name = "Erase test case #10", .write_test_name = "Write test case #10", @@ -516,7 +558,7 @@ ERASE_VALUE, ERASE_VALUE, ERASE_VALUE, ERASE_VALUE}, .written_buf = {0xff, 0xff, 0xff, 0xff, 0x1, 0x2, 0x3, 0x4, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, - .eraseblocks_expected = {{0x0, 0x10}}, + .eraseblocks_expected = {{0x0, 0x10, TEST_ERASE_INJECTOR_5}}, .eraseblocks_expected_ind = 1, .erase_test_name = "Erase test case #11", .write_test_name = "Write test case #11", @@ -538,7 +580,7 @@ ERASE_VALUE, ERASE_VALUE, ERASE_VALUE, ERASE_VALUE}, .written_buf = {0x11, 0x22, 0x33, 0x44, 0xff, 0xff, 0xff, 0xff, 0xa1, 0xa2, 0xa3, 0xa4, 0xa5, 0xa6, 0xa7, 0xa8}, - .eraseblocks_expected = {{0x0, 0x10}}, + .eraseblocks_expected = {{0x0, 0x10, TEST_ERASE_INJECTOR_5}}, .eraseblocks_expected_ind = 1, .erase_test_name = "Erase test case #12", .write_test_name = "Write test case #12", @@ -560,7 +602,7 @@ ERASE_VALUE, ERASE_VALUE, ERASE_VALUE, ERASE_VALUE}, .written_buf = {0x11, 0x22, 0x33, 0x44, 0x55, 0x66, 0x77, 0xff, 0xa1, 0xa2, 0xa3, 0xa4, 0xa5, 0xa6, 0xa7, 0xa8}, - .eraseblocks_expected = {{0x0, 0x10}}, + .eraseblocks_expected = {{0x0, 0x10, TEST_ERASE_INJECTOR_5}}, .eraseblocks_expected_ind = 1, .erase_test_name = "Erase test case #13", .write_test_name = "Write test case #13", @@ -582,7 +624,7 @@ ERASE_VALUE, ERASE_VALUE, ERASE_VALUE, ERASE_VALUE}, .written_buf = {0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, 0xdd, 0xa1, 0xa2, 0xa3, 0xa4, 0xa5, 0xa6, 0xa7, 0xa8}, - .eraseblocks_expected = {{0x0, 0x10}}, + .eraseblocks_expected = {{0x0, 0x10, TEST_ERASE_INJECTOR_5}}, .eraseblocks_expected_ind = 1, .erase_test_name = "Erase test case #14", .write_test_name = "Write test case #14", @@ -605,10 +647,24 @@ ERASE_VALUE, ERASE_VALUE, ERASE_VALUE, ERASE_VALUE}, .written_buf = {0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f}, - .eraseblocks_expected = {{0xf, 0x1}, {0x8, 0x1}, {0x9, 0x1}, {0xa, 0x1}, - {0xb, 0x1}, {0xc, 0x1}, {0xd, 0x1}, {0xe, 0x1}, - {0x3, 0x1}, {0x4, 0x1}, {0x5, 0x1}, {0x6, 0x1}, - {0x7, 0x1}, {0x0, 0x1}, {0x1, 0x1}, {0x2, 0x1}}, + .eraseblocks_expected = { + {0xf, 0x1, TEST_ERASE_INJECTOR_1}, + {0x8, 0x1, TEST_ERASE_INJECTOR_1}, + {0x9, 0x1, TEST_ERASE_INJECTOR_1}, + {0xa, 0x1, TEST_ERASE_INJECTOR_1}, + {0xb, 0x1, TEST_ERASE_INJECTOR_1}, + {0xc, 0x1, TEST_ERASE_INJECTOR_1}, + {0xd, 0x1, TEST_ERASE_INJECTOR_1}, + {0xe, 0x1, TEST_ERASE_INJECTOR_1}, + {0x3, 0x1, TEST_ERASE_INJECTOR_1}, + {0x4, 0x1, TEST_ERASE_INJECTOR_1}, + {0x5, 0x1, TEST_ERASE_INJECTOR_1}, + {0x6, 0x1, TEST_ERASE_INJECTOR_1}, + {0x7, 0x1, TEST_ERASE_INJECTOR_1}, + {0x0, 0x1, TEST_ERASE_INJECTOR_1}, + {0x1, 0x1, TEST_ERASE_INJECTOR_1}, + {0x2, 0x1, TEST_ERASE_INJECTOR_1}, + }, .eraseblocks_expected_ind = 16, .erase_test_name = "Erase test case #15", .write_test_name = "Write test case #15", @@ -631,7 +687,12 @@ ERASE_VALUE, ERASE_VALUE, ERASE_VALUE, ERASE_VALUE}, .written_buf = {0x14, 0x14, 0x15, 0x15, 0x15, 0x15, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x17}, - .eraseblocks_expected = {{0x8, 0x8}, {0x0, 0x10}, {0x0, 0x8}, {0x0, 0x8}}, + .eraseblocks_expected = { + {0x8, 0x8, TEST_ERASE_INJECTOR_4}, + {0x0, 0x10, TEST_ERASE_INJECTOR_5}, + {0x0, 0x8, TEST_ERASE_INJECTOR_4}, + {0x0, 0x8, TEST_ERASE_INJECTOR_4}, + }, .eraseblocks_expected_ind = 4, .erase_test_name = "Erase test case #16", .write_test_name = "Write test case #16", @@ -653,7 +714,7 @@ ERASE_VALUE, ERASE_VALUE, ERASE_VALUE, ERASE_VALUE}, .written_buf = {0x14, 0x14, 0x14, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16}, - .eraseblocks_expected = {{0x0, 0x10}, {0x0, 0x8}}, + .eraseblocks_expected = {{0x0, 0x10, TEST_ERASE_INJECTOR_5}, {0x0, 0x8, TEST_ERASE_INJECTOR_4}}, .eraseblocks_expected_ind = 2, .erase_test_name = "Erase test case #17", .write_test_name = "Write test case #17", @@ -675,7 +736,7 @@ ERASE_VALUE, ERASE_VALUE, ERASE_VALUE, ERASE_VALUE}, .written_buf = {0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16}, - .eraseblocks_expected = {{0x8, 0x8}, {0x0, 0x10}}, + .eraseblocks_expected = {{0x8, 0x8, TEST_ERASE_INJECTOR_4}, {0x0, 0x10, TEST_ERASE_INJECTOR_5}}, .eraseblocks_expected_ind = 2, .erase_test_name = "Erase test case #18", .write_test_name = "Write test case #18", @@ -696,7 +757,7 @@ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, .written_buf = {0x14, 0x14, 0x14, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, - .eraseblocks_expected = {{0x0, 0x8}}, + .eraseblocks_expected = {{0x0, 0x8, TEST_ERASE_INJECTOR_4}}, .eraseblocks_expected_ind = 1, .erase_test_name = "Erase test case #19", .write_test_name = "Write test case #19", diff --git a/tests/meson.build b/tests/meson.build index e8de4b7..e788b80 100644 --- a/tests/meson.build +++ b/tests/meson.build @@ -124,6 +124,7 @@ '-ffunction-sections', '-fdata-sections', '-U_FORTIFY_SOURCE', + '-DFLASHROM_TEST', ], export_dynamic : true, link_args : mocks + link_args, -- To view, visit https://review.coreboot.org/c/flashrom/+/82251?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: I3983fe42c2e7f06668a1bd20d2db7fafa93b8043 Gerrit-Change-Number: 82251 Gerrit-PatchSet: 9 Gerrit-Owner: Peter Marheine <pmarheine(a)chromium.org> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: Peter Marheine <pmarheine(a)chromium.org> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[M] Change in flashrom[main]: ch347_spi: Add driver support for CH347F packaging
by Nicholas Chin (Code Review) 30 May '24

30 May '24

Attention is currently required from: Paul Menzel, ZhiYuanNJ. Nicholas Chin has posted comments on this change by ZhiYuanNJ. ( https://review.coreboot.org/c/flashrom/+/82193?usp=email ) Change subject: ch347_spi: Add driver support for CH347F packaging ...................................................................... Patch Set 13: Code-Review+2 -- To view, visit https://review.coreboot.org/c/flashrom/+/82193?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: I693baf1a0d9dc20757f56fba626b5f5ad20f71dd Gerrit-Change-Number: 82193 Gerrit-PatchSet: 13 Gerrit-Owner: ZhiYuanNJ Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: ZhiYuanNJ Gerrit-Comment-Date: Thu, 30 May 2024 21:28:52 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[M] Change in flashrom[main]: flashchips: add support for chip model Winbond W25Q16JV_M
by Michael Heimpold (Code Review) 30 May '24

30 May '24

Michael Heimpold has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/82715?usp=email ) Change subject: flashchips: add support for chip model Winbond W25Q16JV_M ...................................................................... flashchips: add support for chip model Winbond W25Q16JV_M This is a 2 MiB model with QE=0 factory setting. Tested with ch341a programmer: probe, read, write, erase Link to datasheet: https://www.winbond.com/resource-files/w25q16jv%20spi%20revh%2004082019%20p… Change-Id: Ida1ceb5fe31411bef647e5133c5bd0bdb02d7704 Signed-off-by: Michael Heimpold <mhei(a)heimpold.de> --- M flashchips.c M include/flashchips.h 2 files changed, 53 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/15/82715/1 diff --git a/flashchips.c b/flashchips.c index 2065746..87170a7 100644 --- a/flashchips.c +++ b/flashchips.c @@ -19285,6 +19285,58 @@ { .vendor = "Winbond", + .name = "W25Q16JV_M", + .bustype = BUS_SPI, + .manufacture_id = WINBOND_NEX_ID, + .model_id = WINBOND_NEX_W25Q16JV_M, + .total_size = 2048, + .page_size = 256, + /* supports SFDP */ + /* OTP: 3x 256B total; read 0x48; write 0x42, erase 0x44, read ID 0x4B */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_QPI | + FEATURE_WRSR_EXT2 | FEATURE_WRSR2 | FEATURE_WRSR3, + .tested = TEST_OK_PREW, + .probe = PROBE_SPI_RDID, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 512} }, + .block_erase = SPI_BLOCK_ERASE_20, + }, { + .eraseblocks = { {32 * 1024, 64} }, + .block_erase = SPI_BLOCK_ERASE_52, + }, { + .eraseblocks = { {64 * 1024, 32} }, + .block_erase = SPI_BLOCK_ERASE_D8, + }, { + .eraseblocks = { {2 * 1024 * 1024, 1} }, + .block_erase = SPI_BLOCK_ERASE_60, + }, { + .eraseblocks = { {2 * 1024 * 1024, 1} }, + .block_erase = SPI_BLOCK_ERASE_C7, + } + }, + .printlock = SPI_PRETTYPRINT_STATUS_REGISTER_BP3_SRWD, + .unlock = SPI_DISABLE_BLOCKPROTECT, + .write = SPI_CHIP_WRITE256, + .read = SPI_CHIP_READ, + .voltage = {2700, 3600}, + .reg_bits = + { + .srp = {STATUS1, 7, RW}, + .sec = {STATUS1, 6, RW}, + .tb = {STATUS1, 5, RW}, + .bp = {{STATUS1, 2, RW}, {STATUS1, 3, RW}, {STATUS1, 4, RW}}, + .cmp = {STATUS2, 6, RW}, + .srl = {STATUS2, 0, RW}, + .wps = {STATUS3, 2, RW}, + }, + .decode_range = DECODE_RANGE_SPI25, + }, + + { + .vendor = "Winbond", .name = "W25Q16.V", .bustype = BUS_SPI, .manufacture_id = WINBOND_NEX_ID, diff --git a/include/flashchips.h b/include/flashchips.h index b8a58b2..6ca461b 100644 --- a/include/flashchips.h +++ b/include/flashchips.h @@ -1007,6 +1007,7 @@ #define WINBOND_NEX_W25Q64_W 0x6017 /* W25Q64DW; W25Q64FV in QPI mode */ #define WINBOND_NEX_W25Q128_W 0x6018 /* W25Q128FW; W25Q128FV in QPI mode */ #define WINBOND_NEX_W25Q256_W 0x6019 /* W25Q256JW */ +#define WINBOND_NEX_W25Q16JV_M 0x7015 /* W25Q16JV_M (QE=0) */ #define WINBOND_NEX_W25Q64JV 0x7017 /* W25Q64JV */ #define WINBOND_NEX_W25Q128_V_M 0x7018 /* W25Q128JVSM */ #define WINBOND_NEX_W25Q256JV_M 0x7019 /* W25Q256JV_M (QE=0) */ -- To view, visit https://review.coreboot.org/c/flashrom/+/82715?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: Ida1ceb5fe31411bef647e5133c5bd0bdb02d7704 Gerrit-Change-Number: 82715 Gerrit-PatchSet: 1 Gerrit-Owner: Michael Heimpold <mhei(a)heimpold.de>

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[M] Change in flashrom[main]: ch347_spi: Add driver support for CH347F packaging
by Anastasia Klimchuk (Code Review) 30 May '24

30 May '24

Attention is currently required from: Nicholas Chin, Paul Menzel, ZhiYuanNJ. Anastasia Klimchuk has posted comments on this change by ZhiYuanNJ. ( https://review.coreboot.org/c/flashrom/+/82193?usp=email ) Change subject: ch347_spi: Add driver support for CH347F packaging ...................................................................... Patch Set 13: (1 comment) Patchset: PS13: Nicholas, the patch got few more patchsets, and so you vote was lost. If you are happy with the latest patchset, could you please vote again. Thank you! -- To view, visit https://review.coreboot.org/c/flashrom/+/82193?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: I693baf1a0d9dc20757f56fba626b5f5ad20f71dd Gerrit-Change-Number: 82193 Gerrit-PatchSet: 13 Gerrit-Owner: ZhiYuanNJ Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: ZhiYuanNJ Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Comment-Date: Thu, 30 May 2024 13:49:22 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

1 0

[M] Change in flashrom[main]: ch347_spi: Add driver support for CH347F packaging
by Anastasia Klimchuk (Code Review) 30 May '24

30 May '24

Attention is currently required from: Nicholas Chin, Paul Menzel, ZhiYuanNJ. Anastasia Klimchuk has posted comments on this change by ZhiYuanNJ. ( https://review.coreboot.org/c/flashrom/+/82193?usp=email ) Change subject: ch347_spi: Add driver support for CH347F packaging ...................................................................... Patch Set 13: Code-Review+2 -- To view, visit https://review.coreboot.org/c/flashrom/+/82193?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: I693baf1a0d9dc20757f56fba626b5f5ad20f71dd Gerrit-Change-Number: 82193 Gerrit-PatchSet: 13 Gerrit-Owner: ZhiYuanNJ Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: ZhiYuanNJ Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Comment-Date: Thu, 30 May 2024 13:46:30 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[M] Change in flashrom[main]: ch347_spi: Add driver support for CH347F packaging
by ZhiYuanNJ (Code Review) 30 May '24

30 May '24

Attention is currently required from: Anastasia Klimchuk, Nicholas Chin, Paul Menzel. ZhiYuanNJ has posted comments on this change by ZhiYuanNJ. ( https://review.coreboot.org/c/flashrom/+/82193?usp=email ) Change subject: ch347_spi: Add driver support for CH347F packaging ...................................................................... Patch Set 13: (1 comment) File ch347_spi.c: https://review.coreboot.org/c/flashrom/+/82193/comment/810dc3e3_81a17c8e?us… : PS12, Line 338: > There is a trailing whitespace (two tabs). Could you please remove? […] Done -- To view, visit https://review.coreboot.org/c/flashrom/+/82193?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: I693baf1a0d9dc20757f56fba626b5f5ad20f71dd Gerrit-Change-Number: 82193 Gerrit-PatchSet: 13 Gerrit-Owner: ZhiYuanNJ Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Comment-Date: Thu, 30 May 2024 12:00:30 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Anastasia Klimchuk <aklm(a)chromium.org>

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[S] Change in flashrom[main]: doc: Add doc for supported chipsets
by Anastasia Klimchuk (Code Review) 30 May '24

30 May '24

Attention is currently required from: Peter Marheine, Thomas Heijligen. Anastasia Klimchuk has posted comments on this change by Anastasia Klimchuk. ( https://review.coreboot.org/c/flashrom/+/82198?usp=email ) Change subject: doc: Add doc for supported chipsets ...................................................................... Patch Set 4: (1 comment) File doc/supported_hw/supported_chipsets.rst: https://review.coreboot.org/c/flashrom/+/82198/comment/3480d8dd_0d9ca527?us… : PS3, Line 12: Alternatively inspect the file `on the web UI of our GitHub mirror <https://github.com/flashrom/flashrom/blob/main/chipset_enable.c#L1768>`_. > Move this up to line 7, since it's another way to see the source. Done -- To view, visit https://review.coreboot.org/c/flashrom/+/82198?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: I9c9edc7deeeb7a783e2ba2fc6b372edb9c61609e Gerrit-Change-Number: 82198 Gerrit-PatchSet: 4 Gerrit-Owner: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Peter Marheine <pmarheine(a)chromium.org> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Thomas Heijligen <src(a)posteo.de> Gerrit-Attention: Peter Marheine <pmarheine(a)chromium.org> Gerrit-Comment-Date: Thu, 30 May 2024 09:30:14 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Peter Marheine <pmarheine(a)chromium.org>

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[S] Change in flashrom[main]: doc: Add doc for supported chipsets
by Anastasia Klimchuk (Code Review) 30 May '24

30 May '24

Attention is currently required from: Anastasia Klimchuk, Thomas Heijligen. Hello Peter Marheine, Thomas Heijligen, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/flashrom/+/82198?usp=email to look at the new patch set (#4). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: doc: Add doc for supported chipsets ...................................................................... doc: Add doc for supported chipsets Change-Id: I9c9edc7deeeb7a783e2ba2fc6b372edb9c61609e Signed-off-by: Anastasia Klimchuk <aklm(a)flashrom.org> --- M doc/supported_hw/index.rst A doc/supported_hw/supported_chipsets.rst 2 files changed, 22 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/98/82198/4 -- To view, visit https://review.coreboot.org/c/flashrom/+/82198?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: I9c9edc7deeeb7a783e2ba2fc6b372edb9c61609e Gerrit-Change-Number: 82198 Gerrit-PatchSet: 4 Gerrit-Owner: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Peter Marheine <pmarheine(a)chromium.org> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Thomas Heijligen <src(a)posteo.de> Gerrit-Attention: Anastasia Klimchuk <aklm(a)chromium.org>

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