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Hello Anastasia Klimchuk, Nikolai Artemiev, Stefan Reinauer, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/flashrom/+/84752?usp=email
to look at the new patch set (#2).
The following approvals got outdated and were removed:
Verified+1 by build bot (Jenkins)
Change subject: flashchips: add Winbond W25R512NW / W74M51NW
......................................................................
flashchips: add Winbond W25R512NW / W74M51NW
I used W25Q256JW as a template and just increased every erase size
calculation.
Datasheet can be found by form contact only via
https://www.winbond.com/hq/product/code-storage-flash-memory/serial-nor-fla…
I tested it by running:
dd if=/dev/urandom of=/tmp/random.bin bs=1M count=64
sudo /tmp/flashrom/build/flashrom -p ft2232_spi:type=2232H -w /tmp/random.bin --progress
sudo /tmp/flashrom/build/flashrom -p ft2232_spi:type=2232H -v /tmp/random.bin
And I saw "Verifying flash... VERIFIED."
PS: Yes I know I probably overvolted the chip by giving it 3.3V
Change-Id: Ibf670e4014a22e4636789768b759cb51f75cd046
Signed-off-by: Alexandru M Stan <ams(a)frame.work>
---
M flashchips.c
M include/flashchips.h
2 files changed, 49 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/52/84752/2
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Peter Marheine has posted comments on this change by Anastasia Klimchuk. ( https://review.coreboot.org/c/flashrom/+/84686?usp=email )
Change subject: erase/write: Deselect all smaller blocks when large block is selected
......................................................................
Patch Set 3: Code-Review+2
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Change subject: erase/write: Deselect all smaller blocks when large block is selected
......................................................................
Patch Set 3:
(1 comment)
File erasure_layout.c:
https://review.coreboot.org/c/flashrom/+/84686/comment/ecd05016_47a2709c?us… :
PS2, Line 254: We are selecting one large block instead, to send opcode once
: instead of sending many smaller once. */
> typos […]
Done
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Change subject: flashchips: add GD25F256F
......................................................................
Patch Set 2: Code-Review+2
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Change subject: erasure_layout: Erase larger block only when all sub-block need erase
......................................................................
erasure_layout: Erase larger block only when all sub-block need erase
A larger (not the smallest) erase block used to get erased when half
of sub-blocks it contains need erase, which has at least 2 issues:
1. The rest half of sub-blocks that do not need erase are also erased,
introducing some erase overheads.
2. More severely, since this logic only selects a block and delects
its sub-blocks when half of sub-blocks need erase, but this logic
does not deselect "nested sub-blocks (sub-blocks of sub-block)" not
reach the limit under this block, the logic may cause duplicated
erase. For example, if a erase block (often the largest one
corresponding to the whole chip) has half of its sub-blocks and
some incontiguous nested sub-blocks needing erase, these double
sub-blocks will end up being erased twice, introducing even more
erase overheads than whole-chip erase.
The older behavior of flashrom before adding erasure_layout.c, when no
communicational error occurs, will neither erase blocks that do not
need erase, nor cause duplicated erase. Higher efficiency should be
achieved without introducing extra erase overheads, by allowing
combining contiguous small erase blocks only when they can
coincidently form a larger erase block.
Change-Id: I9e10749186e395da67ec80e296119f33c3f83122
Signed-off-by: persmule <persmule(a)hardenedlinux.org>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/84614
Reviewed-by: Peter Marheine <pmarheine(a)chromium.org>
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Anastasia Klimchuk <aklm(a)chromium.org>
---
M erasure_layout.c
1 file changed, 1 insertion(+), 1 deletion(-)
Approvals:
build bot (Jenkins): Verified
Anastasia Klimchuk: Looks good to me, approved
Peter Marheine: Looks good to me, approved
diff --git a/erasure_layout.c b/erasure_layout.c
index c3a415b..56841ab 100644
--- a/erasure_layout.c
+++ b/erasure_layout.c
@@ -228,7 +228,7 @@
}
const int total_blocks = sub_block_end - sub_block_start + 1;
- if (count && count > total_blocks/2) {
+ if (count == total_blocks) {
if (ll->start_addr >= rstart && ll->end_addr <= rend) {
for (int j = sub_block_start; j <= sub_block_end; j++)
layout[findex - 1].layout_list[j].selected = false;
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Change subject: flashchips: add GD25F64F
......................................................................
Patch Set 2:
(1 comment)
Commit Message:
https://review.coreboot.org/c/flashrom/+/84705/comment/34d9ac9b_bf19e3b9?us… :
PS1, Line 10: Will send datasheet through email
> Got the email, I did the review. You can remove this line from commit message. […]
Acknowledged
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Hello Anastasia Klimchuk, Nikolai Artemiev, Stefan Reinauer, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/flashrom/+/84705?usp=email
to look at the new patch set (#2).
Change subject: flashchips: add GD25F64F
......................................................................
flashchips: add GD25F64F
GD25F64F: 3V 64Mbit, high performance
Tested on ch347 with erase, write, read, and protection
Change-Id: I07005f1589b76c8a61a1a744b16dc6b0c9020e11
Signed-off-by: Victor Lim <vlim(a)gigadevice.com>
---
M flashchips.c
M include/flashchips.h
2 files changed, 50 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/05/84705/2
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Change subject: flashchips: add GD25F256F
......................................................................
Patch Set 2:
(1 comment)
File flashchips.c:
https://review.coreboot.org/c/flashrom/+/84090/comment/8d108056_3421be22?us… :
PS2, Line 8056: reg_bits
> The exact definition in the datasheet for STATUS1 bit 7 is "Reserved". […]
Since it is now a "reserved" bit, that means this bit is no longer meaningful. When reading it, it will give value 0.
It can still do SW protection; just no HW protection.
Below is the message when reading the --wp-status.
> Found GigaDevice flash chip "GD25F256F" (32768 kB, SPI) on ch347_spi.
> Protection range: start=0x01e00000 length=0x00200000 (upper 1/16)
> Protection mode: disabled
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Anastasia Klimchuk has posted comments on this change by Anastasia Klimchuk. ( https://review.coreboot.org/c/flashrom/+/84439?usp=email )
Change subject: Display progress for what is actually erased/written
......................................................................
Patch Set 9:
(1 comment)
File flashrom.c:
https://review.coreboot.org/c/flashrom/+/84439/comment/79da4579_69079e41?us… :
PS7, Line 1265: // TODO: take FEATURE_NO_ERASE into account?
> I found something to fix for FEATURE_NO_ERASE, although not here. […]
How it looks to me now, there can be two possible workarounds for FEATURE_NO_ERASE:
Either hacking spi_write_chunked so that it knows when it's erase instead of write
or re-init progress in between erase and write, then it would looks like WRITE 0...100 and then once more WRITE 0...100
It seem to me the latter it more realistic.
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Change subject: WIP: flashchips: add Winbond W25R512NWEIQ
......................................................................
Patch Set 1:
(2 comments)
Commit Message:
https://review.coreboot.org/c/flashrom/+/84752/comment/fc65cc45_4bc0b1a2?us… :
PS1, Line 8:
: I don't actually have a datasheet for this (so feel free to reject this
: CL)
Thank you for contribution! No I won't reject it so easily, my first reaction is to try and find the datasheet.
It doesn't have to be fully public datasheet, could be someone who has datasheet reviewing this patch. This does not necessarily mean that the person has to share the datasheet with the whole world.
Please keep the patch... let's try to find the reviewer.
https://review.coreboot.org/c/flashrom/+/84752/comment/428c0d54_3ff9a47e?us… :
PS1, Line 10: I just bruteforced it
This is so cool! :)
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