October 2024 - flashrom-gerrit

[S] Change in flashrom[main]: flashchips: add Winbond W25R512NW / W74M51NW
by Anastasia Klimchuk (Code Review) 18 Oct '24

18 Oct '24

Attention is currently required from: Alexandru Stan, Nikolai Artemiev, Stefan Reinauer. Anastasia Klimchuk has posted comments on this change by Alexandru Stan. ( https://review.coreboot.org/c/flashrom/+/84752?usp=email ) Change subject: flashchips: add Winbond W25R512NW / W74M51NW ...................................................................... Patch Set 2: (3 comments) File flashchips.c: https://review.coreboot.org/c/flashrom/+/84752/comment/4ff7045d_42bc76c9?us… : PS1, Line 20271: 1650 > What the datasheet says? I would say, voltage you better just copy from datasheet ah, but you already updated the voltage according to datasheet. I am resolving this. File flashchips.c: https://review.coreboot.org/c/flashrom/+/84752/comment/d67c813b_4d2c36c1?us… : PS2, Line 20239: 1024B total, 256B reserved Maybe the better comment is what's in the datasheet: > 3X256-Bytes Security Registers with OTP locks and then the rest of the comment as it is, with opcodes. Or as I said you can remove the comment line. https://review.coreboot.org/c/flashrom/+/84752/comment/58908027_b4550506?us… : PS2, Line 20269: .printlock = SPI_PRETTYPRINT_STATUS_REGISTER_BP3_SRWD, : .unlock = SPI_DISABLE_BLOCKPROTECT, : > Since you haven't tested write-protection and not marking it as tested, you can put here […] Actually, from the datasheet this is fine, leave it. And yes, you are not marking it as tested anyway. -- To view, visit https://review.coreboot.org/c/flashrom/+/84752?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: Ibf670e4014a22e4636789768b759cb51f75cd046 Gerrit-Change-Number: 84752 Gerrit-PatchSet: 2 Gerrit-Owner: Alexandru Stan <ams(a)frame.work> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Alexandru Stan <ams(a)frame.work> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Comment-Date: Fri, 18 Oct 2024 11:55:12 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Alexandru Stan <ams(a)frame.work> Comment-In-Reply-To: Anastasia Klimchuk <aklm(a)chromium.org>

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[S] Change in flashrom[main]: flashchips: add Winbond W25R512NW / W74M51NW
by Anastasia Klimchuk (Code Review) 18 Oct '24

18 Oct '24

Attention is currently required from: Alexandru Stan, Nikolai Artemiev, Stefan Reinauer. Anastasia Klimchuk has posted comments on this change by Alexandru Stan. ( https://review.coreboot.org/c/flashrom/+/84752?usp=email ) Change subject: flashchips: add Winbond W25R512NW / W74M51NW ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/flashrom/+/84752/comment/38a6e96c_bb681731?us… : PS1, Line 8: : I don't actually have a datasheet for this (so feel free to reject this : CL) > > I just got a datasheet myself […] Actually, the latest news: the datasheet made its way to me! :) I will look today later. Thank you! -- To view, visit https://review.coreboot.org/c/flashrom/+/84752?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: Ibf670e4014a22e4636789768b759cb51f75cd046 Gerrit-Change-Number: 84752 Gerrit-PatchSet: 2 Gerrit-Owner: Alexandru Stan <ams(a)frame.work> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Alexandru Stan <ams(a)frame.work> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Comment-Date: Fri, 18 Oct 2024 04:46:17 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Alexandru Stan <ams(a)frame.work> Comment-In-Reply-To: Anastasia Klimchuk <aklm(a)chromium.org>

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[S] Change in flashrom[main]: flashchips: add Winbond W25R512NW / W74M51NW
by Anastasia Klimchuk (Code Review) 17 Oct '24

17 Oct '24

Attention is currently required from: Alexandru Stan, Nikolai Artemiev, Stefan Reinauer. Anastasia Klimchuk has posted comments on this change by Alexandru Stan. ( https://review.coreboot.org/c/flashrom/+/84752?usp=email ) Change subject: flashchips: add Winbond W25R512NW / W74M51NW ...................................................................... Patch Set 2: (5 comments) Commit Message: https://review.coreboot.org/c/flashrom/+/84752/comment/07e291c5_cc09a398?us… : PS1, Line 8: : I don't actually have a datasheet for this (so feel free to reject this : CL) > I just got a datasheet myself This is perfect, thanks so much for your effort! I understand not everything is distributable and we don't have Winbond engineers collaborating with us yet, not yet. However if you have the datasheet and the chip itself, and you tested it, that's all what is needed. You already checked the chip definition to the best of your knowledge, and tested the chip. If you have any doubts about anything, please ask! But I think you asked your questions already. So there are few open comments left and it should be all good. Sadly, I won't have anything relevant on my gdrive anymore. Also sadly, my job situation has changed dramatically, my current job is completely irrelevant to flashrom. I am here as a hobby <3 File flashchips.c: https://review.coreboot.org/c/flashrom/+/84752/comment/69fcf0e8_4191ab55?us… : PS1, Line 20271: 1650 > Datasheet disagreed here. What the datasheet says? I would say, voltage you better just copy from datasheet File flashchips.c: https://review.coreboot.org/c/flashrom/+/84752/comment/0cc5e647_fcc3c82f?us… : PS2, Line 20230: W25R512NW The situation you described in the following two lines, we do the following: we mark with the name `.name = W25R512NW/W74M51NW` , and then you don't need the comment in the following two lines. https://review.coreboot.org/c/flashrom/+/84752/comment/e3f8ed38_de5f2bbf?us… : PS2, Line 20239: 1024B total, 256B reserved > Again, copied this comment from that Winbond chip. […] I am often confused by how OTP size is described in the datasheet :( although I shouldn't be. Let's leave it. OTP is not implemented yet, these comments are for future. I will try to find similar chip model with similar OTP size with the datasheet I have, to compare. You can leave it, or if you have any concerns, you can just remove this comment line. https://review.coreboot.org/c/flashrom/+/84752/comment/bdb960de_6c116a1d?us… : PS2, Line 20269: .printlock = SPI_PRETTYPRINT_STATUS_REGISTER_BP3_SRWD, : .unlock = SPI_DISABLE_BLOCKPROTECT, : > Given I haven't tested WP, I don't know if these are good. […] Since you haven't tested write-protection and not marking it as tested, you can put here .printlock = SPI_PRETTYPRINT_STATUS_REGISTER_PLAIN, .unlock = SPI_DISABLE_BLOCKPROTECT, and then later when/if write-protection is added, these values might be updated. -- To view, visit https://review.coreboot.org/c/flashrom/+/84752?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: Ibf670e4014a22e4636789768b759cb51f75cd046 Gerrit-Change-Number: 84752 Gerrit-PatchSet: 2 Gerrit-Owner: Alexandru Stan <ams(a)frame.work> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Alexandru Stan <ams(a)frame.work> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Comment-Date: Thu, 17 Oct 2024 09:21:54 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Alexandru Stan <ams(a)frame.work> Comment-In-Reply-To: Anastasia Klimchuk <aklm(a)chromium.org>

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[XS] Change in flashrom[main]: flashchips: Add Support for XMC XM25LU64C
by Anastasia Klimchuk (Code Review) 17 Oct '24

17 Oct '24

Attention is currently required from: Nikolai Artemiev, Ssunk, Stefan Reinauer. Anastasia Klimchuk has posted comments on this change by Ssunk. ( https://review.coreboot.org/c/flashrom/+/84775?usp=email ) Change subject: flashchips: Add Support for XMC XM25LU64C ...................................................................... Patch Set 1: (1 comment) File flashchips.c: https://review.coreboot.org/c/flashrom/+/84775/comment/7afa072b_bf855298?us… : PS1, Line 22696: TEST_UNTESTED The existing entry for XM25QU64C was untested, and if two models share the same definition, they also share test status. So the new model would also be marked "untested" even though you actually tested it. Is it possible that you test XM25QU64C (the one that was here before)? Then you will be able to mark them both as tested. If you do that, you will then add in commit message the info that you tested both models. Thank you! -- To view, visit https://review.coreboot.org/c/flashrom/+/84775?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: I8d1af7fbfb4c45db09ed5ac82c683d273c8151c7 Gerrit-Change-Number: 84775 Gerrit-PatchSet: 1 Gerrit-Owner: Ssunk <ssunkkan(a)gmail.com> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Ssunk <ssunkkan(a)gmail.com> Gerrit-Attention: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Comment-Date: Thu, 17 Oct 2024 07:59:59 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[M] Change in flashrom[main]: flashchips: add GD25F256F
by Anastasia Klimchuk (Code Review) 17 Oct '24

17 Oct '24

Attention is currently required from: Stefan Reinauer, Victor Lim. Anastasia Klimchuk has posted comments on this change by Victor Lim. ( https://review.coreboot.org/c/flashrom/+/84090?usp=email ) Change subject: flashchips: add GD25F256F ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: Victor, this is now in the state of "merge conflict" because another flashchip was submitted earlier. Would you be able to rebase on the top of main? Thank you! -- To view, visit https://review.coreboot.org/c/flashrom/+/84090?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: Ibbbbb8a55adbcbc2ee1785782c4eb3771d50c167 Gerrit-Change-Number: 84090 Gerrit-PatchSet: 2 Gerrit-Owner: Victor Lim <vlim(a)gigadevice.com> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Victor Lim <vlim(a)gigadevice.com> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Comment-Date: Thu, 17 Oct 2024 07:29:34 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[S] Change in flashrom[main]: erase/write: Deselect all smaller blocks when large block is selected
by Anastasia Klimchuk (Code Review) 16 Oct '24

16 Oct '24

Attention is currently required from: Aarya, Bill XIE. Anastasia Klimchuk has posted comments on this change by Anastasia Klimchuk. ( https://review.coreboot.org/c/flashrom/+/84686?usp=email ) Change subject: erase/write: Deselect all smaller blocks when large block is selected ...................................................................... Patch Set 4: (2 comments) File erasure_layout.c: https://review.coreboot.org/c/flashrom/+/84686/comment/d5592b3b_ca42e7f2?us… : PS1, Line 237: /* Deselect all smaller blocks covering the same region. */ > I still need to add a test for this in `tests/erase_func_algo. […] I made the test! CB:84783 I need to tell you more about it! :) I needed to upgrade the test case so that they assert the eraseblocks invocations for write operation (it was recorded and logged, but not asserted). Previously, it was asserted for erase op only. With that, cases #9, 13, 20 feel the difference of CB:84614. So this is useful. I updated them to pass on current head. Now, about this patch, the issue it is fixing can never happen after CB:84614, however it can start re-happening after CB:84721. So the case #20 is specifically creating the situation of "nested sub-blocks", to be able to test CB:84721 later. I used case #20 to test this patch in isolation. File erasure_layout.c: https://review.coreboot.org/c/flashrom/+/84686/comment/9b455365_e21f93ee?us… : PS2, Line 254: We are selecting one large block instead, to send opcode once : instead of sending many smaller once. */ > Done thanks! -- To view, visit https://review.coreboot.org/c/flashrom/+/84686?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: Icfc18d5c090b1dcb92ab157e2c139be71af59300 Gerrit-Change-Number: 84686 Gerrit-PatchSet: 4 Gerrit-Owner: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Aarya <aarya.chaumal(a)gmail.com> Gerrit-Reviewer: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-Reviewer: Peter Marheine <pmarheine(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-Attention: Aarya <aarya.chaumal(a)gmail.com> Gerrit-Comment-Date: Wed, 16 Oct 2024 12:08:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Bill XIE <persmule(a)hardenedlinux.org> Comment-In-Reply-To: Anastasia Klimchuk <aklm(a)chromium.org> Comment-In-Reply-To: Peter Marheine <pmarheine(a)chromium.org>

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[M] Change in flashrom[main]: tests: Add assert for eraseblocks order of invocations for write op
by Anastasia Klimchuk (Code Review) 16 Oct '24

16 Oct '24

Anastasia Klimchuk has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/84783?usp=email ) Change subject: tests: Add assert for eraseblocks order of invocations for write op ...................................................................... tests: Add assert for eraseblocks order of invocations for write op Change-Id: I558fded2b9f876e33ca92dea324d90ef73f6a2be Signed-off-by: Anastasia Klimchuk <aklm(a)flashrom.org> --- M tests/erase_func_algo.c 1 file changed, 187 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/83/84783/1 diff --git a/tests/erase_func_algo.c b/tests/erase_func_algo.c index d947eb9..cec4879 100644 --- a/tests/erase_func_algo.c +++ b/tests/erase_func_algo.c @@ -52,6 +52,8 @@ uint8_t written_protected_buf[MOCK_CHIP_SIZE]; /* Expected content after write with protected region. */ struct erase_invoke eraseblocks_expected[MOCK_CHIP_SIZE]; /* Expected order of eraseblocks invocations. */ unsigned int eraseblocks_expected_ind; /* Expected number of eraseblocks invocations. */ + struct erase_invoke write_eraseblocks_expected[MOCK_CHIP_SIZE]; /* Expected order of eraseblocks invocations. */ + unsigned int write_eraseblocks_expected_ind; /* Expected number of eraseblocks invocations. */ char erase_test_name[40]; /* Test case display name for testing erase operation. */ char write_test_name[40]; /* Test case display name for testing write operation. */ }; @@ -212,6 +214,29 @@ }, }; +static struct flashchip chip_1_4_16 = { + .vendor = "aklm", + /* See comment on previous chip. */ + .total_size = 1, + .tested = TEST_OK_PREW, + .gran = WRITE_GRAN_1BYTE, + .read = TEST_READ_INJECTOR, + .write = TEST_WRITE_INJECTOR, + .block_erasers = + { + { + .eraseblocks = { {1, MIN_REAL_CHIP_SIZE} }, + .block_erase = TEST_ERASE_INJECTOR_1, + }, { + .eraseblocks = { {4, MIN_REAL_CHIP_SIZE / 4} }, + .block_erase = TEST_ERASE_INJECTOR_3, + }, { + .eraseblocks = { {16, MIN_REAL_CHIP_SIZE / 16} }, + .block_erase = TEST_ERASE_INJECTOR_5, + } + }, +}; + #define BLOCK_ERASE_FUNC(n) \ static int block_erase_chip_ ## n (struct flashctx *flash, unsigned int blockaddr, unsigned int blocklen) { \ return block_erase_chip_tagged(flash, TEST_ERASE_INJECTOR_ ## n, blockaddr, blocklen); \ @@ -341,6 +366,8 @@ 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f}, .eraseblocks_expected = {{0x0, 0x10, TEST_ERASE_INJECTOR_5}}, .eraseblocks_expected_ind = 1, + .write_eraseblocks_expected = {{0x0, 0x10, TEST_ERASE_INJECTOR_5}}, + .write_eraseblocks_expected_ind = 1, .erase_test_name = "Erase test case #0", .write_test_name = "Write test case #0", }, { @@ -354,7 +381,7 @@ .chip = &chip_1_2_4_8_16, .regions = {{0, MOCK_CHIP_SIZE/2 - 1, "part1"}, {MOCK_CHIP_SIZE/2, MIN_REAL_CHIP_SIZE - 1, "part2"}}, .initial_buf = {0xf0, 0xf1, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7, - 0xf8, 0xf9, 0xfa, 0xfb, 0xfc, 0xfd, 0xfe, 0xff}, + 0xf8, 0xf9, 0xfa, 0xfb, 0xfc, 0xfd, 0xfe, 0xf1}, .erased_buf = {ERASE_VALUE, ERASE_VALUE, ERASE_VALUE, ERASE_VALUE, ERASE_VALUE, ERASE_VALUE, ERASE_VALUE, ERASE_VALUE, ERASE_VALUE, ERASE_VALUE, ERASE_VALUE, ERASE_VALUE, @@ -363,6 +390,10 @@ 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f}, .eraseblocks_expected = {{0x8, 0x8, TEST_ERASE_INJECTOR_4}, {0x0, 0x8, TEST_ERASE_INJECTOR_4}}, .eraseblocks_expected_ind = 2, + .write_eraseblocks_expected = {{0x9, 0x1, TEST_ERASE_INJECTOR_1}, + {0xa, 0x2, TEST_ERASE_INJECTOR_2}, + {0xc, 0x4, TEST_ERASE_INJECTOR_3}}, + .write_eraseblocks_expected_ind = 3, .erase_test_name = "Erase test case #1", .write_test_name = "Write test case #1", }, { @@ -391,6 +422,11 @@ {0x0, 0x8, TEST_ERASE_INJECTOR_4} }, .eraseblocks_expected_ind = 5, + .write_eraseblocks_expected = { + {0x6, 0x1, TEST_ERASE_INJECTOR_1}, + {0x8, 0x1, TEST_ERASE_INJECTOR_1} + }, + .write_eraseblocks_expected_ind = 2, .erase_test_name = "Erase test case #2", .write_test_name = "Write test case #2", }, { @@ -413,6 +449,8 @@ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, .eraseblocks_expected = {{0x0, 0x10, TEST_ERASE_INJECTOR_5}}, .eraseblocks_expected_ind = 1, + .write_eraseblocks_expected = {{0x4, 0x4, TEST_ERASE_INJECTOR_3}}, + .write_eraseblocks_expected_ind = 1, .erase_test_name = "Erase test case #3", .write_test_name = "Write test case #3", }, { @@ -435,6 +473,8 @@ 0xa1, 0xa2, 0xa3, 0xa4, 0xa5, 0xa6, 0xa7, 0xa8}, .eraseblocks_expected = {{0x0, 0x10, TEST_ERASE_INJECTOR_5}}, .eraseblocks_expected_ind = 1, + .write_eraseblocks_expected = {{0x0, 0x4, TEST_ERASE_INJECTOR_3}, {0x8, 0x8, TEST_ERASE_INJECTOR_4}}, + .write_eraseblocks_expected_ind = 2, .erase_test_name = "Erase test case #4", .write_test_name = "Write test case #4", }, { @@ -457,6 +497,11 @@ 0xa1, 0xa2, 0xa3, 0xa4, 0xa5, 0xa6, 0xa7, 0xa8}, .eraseblocks_expected = {{0x0, 0x10, TEST_ERASE_INJECTOR_5}}, .eraseblocks_expected_ind = 1, + .write_eraseblocks_expected = {{0x6, 0x1, TEST_ERASE_INJECTOR_1}, + {0x4, 0x2, TEST_ERASE_INJECTOR_2}, + {0x0, 0x4, TEST_ERASE_INJECTOR_3}, + {0x8, 0x8, TEST_ERASE_INJECTOR_4}}, + .write_eraseblocks_expected_ind = 4, .erase_test_name = "Erase test case #5", .write_test_name = "Write test case #5", }, { @@ -479,6 +524,8 @@ 0xa1, 0xa2, 0xa3, 0xa4, 0xa5, 0xa6, 0xa7, 0xa8}, .eraseblocks_expected = {{0x0, 0x10, TEST_ERASE_INJECTOR_5}}, .eraseblocks_expected_ind = 1, + .write_eraseblocks_expected = {{0x7, 0x1, TEST_ERASE_INJECTOR_1}}, + .write_eraseblocks_expected_ind = 1, .erase_test_name = "Erase test case #6", .write_test_name = "Write test case #6", }, { @@ -510,6 +557,17 @@ {0x0, 0x2, TEST_ERASE_INJECTOR_2} }, .eraseblocks_expected_ind = 8, + .write_eraseblocks_expected = { + {0xf, 0x1, TEST_ERASE_INJECTOR_1}, + {0xe, 0x1, TEST_ERASE_INJECTOR_1}, + {0xc, 0x2, TEST_ERASE_INJECTOR_2}, + {0x8, 0x4, TEST_ERASE_INJECTOR_3}, + {0x3, 0x1, TEST_ERASE_INJECTOR_1}, + {0x4, 0x4, TEST_ERASE_INJECTOR_3}, + {0x2, 0x1, TEST_ERASE_INJECTOR_1}, + {0x0, 0x2, TEST_ERASE_INJECTOR_2} + }, + .write_eraseblocks_expected_ind = 8, .erase_test_name = "Erase test case #7", .write_test_name = "Write test case #7", }, { @@ -532,6 +590,8 @@ 0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f}, .eraseblocks_expected = {{0x0, 0x10, TEST_ERASE_INJECTOR_5}}, .eraseblocks_expected_ind = 1, + .write_eraseblocks_expected = {{0x0, 0x10, TEST_ERASE_INJECTOR_5}}, + .write_eraseblocks_expected_ind = 1, .erase_test_name = "Erase test case #8", .write_test_name = "Write test case #8", }, { @@ -546,7 +606,7 @@ .regions = {{0, MOCK_CHIP_SIZE/2 - 1, "part1"}, {MOCK_CHIP_SIZE/2, MOCK_CHIP_SIZE - 1, "part2"}, {MOCK_CHIP_SIZE, MIN_REAL_CHIP_SIZE - 1, "longtail"}}, .initial_buf = {0xf0, 0xf1, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7, - 0xf8, 0xf9, 0xfa, 0xfb, 0xfc, 0xfd, 0xfe, 0xff}, + 0xf8, 0xf9, 0xfa, 0xfb, 0xfc, 0xfd, 0xfe, 0xf1}, .erased_buf = {ERASE_VALUE, ERASE_VALUE, ERASE_VALUE, ERASE_VALUE, ERASE_VALUE, ERASE_VALUE, ERASE_VALUE, ERASE_VALUE, ERASE_VALUE, ERASE_VALUE, ERASE_VALUE, ERASE_VALUE, @@ -555,6 +615,14 @@ 0xf8, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f}, .eraseblocks_expected = {{0x8, 0x8, TEST_ERASE_INJECTOR_4}, {0x0, 0x8, TEST_ERASE_INJECTOR_4}}, .eraseblocks_expected_ind = 2, + .write_eraseblocks_expected = {{0x9, 0x1, TEST_ERASE_INJECTOR_1}, + {0xa, 0x1, TEST_ERASE_INJECTOR_1}, + {0xb, 0x1, TEST_ERASE_INJECTOR_1}, + {0xc, 0x1, TEST_ERASE_INJECTOR_1}, + {0xd, 0x1, TEST_ERASE_INJECTOR_1}, + {0xe, 0x1, TEST_ERASE_INJECTOR_1}, + {0xf, 0x1, TEST_ERASE_INJECTOR_1}}, + .write_eraseblocks_expected_ind = 7, .erase_test_name = "Erase test case #9", .write_test_name = "Write test case #9", }, { @@ -587,6 +655,11 @@ {0x0, 0x8, TEST_ERASE_INJECTOR_4} }, .eraseblocks_expected_ind = 9, + .write_eraseblocks_expected = { + {0x6, 0x1, TEST_ERASE_INJECTOR_1}, + {0x8, 0x1, TEST_ERASE_INJECTOR_1} + }, + .write_eraseblocks_expected_ind = 2, .erase_test_name = "Erase test case #10", .write_test_name = "Write test case #10", }, { @@ -609,6 +682,11 @@ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, .eraseblocks_expected = {{0x0, 0x10, TEST_ERASE_INJECTOR_5}}, .eraseblocks_expected_ind = 1, + .write_eraseblocks_expected = {{0x4, 0x1, TEST_ERASE_INJECTOR_1}, + {0x5, 0x1, TEST_ERASE_INJECTOR_1}, + {0x6, 0x1, TEST_ERASE_INJECTOR_1}, + {0x7, 0x1, TEST_ERASE_INJECTOR_1}}, + .write_eraseblocks_expected_ind = 4, .erase_test_name = "Erase test case #11", .write_test_name = "Write test case #11", }, { @@ -631,6 +709,12 @@ 0xa1, 0xa2, 0xa3, 0xa4, 0xa5, 0xa6, 0xa7, 0xa8}, .eraseblocks_expected = {{0x0, 0x10, TEST_ERASE_INJECTOR_5}}, .eraseblocks_expected_ind = 1, + .write_eraseblocks_expected = {{0x0, 0x1, TEST_ERASE_INJECTOR_1}, + {0x1, 0x1, TEST_ERASE_INJECTOR_1}, + {0x2, 0x1, TEST_ERASE_INJECTOR_1}, + {0x3, 0x1, TEST_ERASE_INJECTOR_1}, + {0x8, 0x8, TEST_ERASE_INJECTOR_4}}, + .write_eraseblocks_expected_ind = 5, .erase_test_name = "Erase test case #12", .write_test_name = "Write test case #12", }, { @@ -653,6 +737,15 @@ 0xa1, 0xa2, 0xa3, 0xa4, 0xa5, 0xa6, 0xa7, 0xa8}, .eraseblocks_expected = {{0x0, 0x10, TEST_ERASE_INJECTOR_5}}, .eraseblocks_expected_ind = 1, + .write_eraseblocks_expected = {{0x0, 0x1, TEST_ERASE_INJECTOR_1}, + {0x1, 0x1, TEST_ERASE_INJECTOR_1}, + {0x2, 0x1, TEST_ERASE_INJECTOR_1}, + {0x3, 0x1, TEST_ERASE_INJECTOR_1}, + {0x4, 0x1, TEST_ERASE_INJECTOR_1}, + {0x5, 0x1, TEST_ERASE_INJECTOR_1}, + {0x6, 0x1, TEST_ERASE_INJECTOR_1}, + {0x8, 0x8, TEST_ERASE_INJECTOR_4}}, + .write_eraseblocks_expected_ind = 8, .erase_test_name = "Erase test case #13", .write_test_name = "Write test case #13", }, { @@ -675,6 +768,8 @@ 0xa1, 0xa2, 0xa3, 0xa4, 0xa5, 0xa6, 0xa7, 0xa8}, .eraseblocks_expected = {{0x0, 0x10, TEST_ERASE_INJECTOR_5}}, .eraseblocks_expected_ind = 1, + .write_eraseblocks_expected = {{0x7, 0x1, TEST_ERASE_INJECTOR_1}}, + .write_eraseblocks_expected_ind = 1, .erase_test_name = "Erase test case #14", .write_test_name = "Write test case #14", }, { @@ -715,6 +810,25 @@ {0x2, 0x1, TEST_ERASE_INJECTOR_1}, }, .eraseblocks_expected_ind = 16, + .write_eraseblocks_expected = { + {0xf, 0x1, TEST_ERASE_INJECTOR_1}, + {0x8, 0x1, TEST_ERASE_INJECTOR_1}, + {0x9, 0x1, TEST_ERASE_INJECTOR_1}, + {0xa, 0x1, TEST_ERASE_INJECTOR_1}, + {0xb, 0x1, TEST_ERASE_INJECTOR_1}, + {0xc, 0x1, TEST_ERASE_INJECTOR_1}, + {0xd, 0x1, TEST_ERASE_INJECTOR_1}, + {0xe, 0x1, TEST_ERASE_INJECTOR_1}, + {0x3, 0x1, TEST_ERASE_INJECTOR_1}, + {0x4, 0x1, TEST_ERASE_INJECTOR_1}, + {0x5, 0x1, TEST_ERASE_INJECTOR_1}, + {0x6, 0x1, TEST_ERASE_INJECTOR_1}, + {0x7, 0x1, TEST_ERASE_INJECTOR_1}, + {0x0, 0x1, TEST_ERASE_INJECTOR_1}, + {0x1, 0x1, TEST_ERASE_INJECTOR_1}, + {0x2, 0x1, TEST_ERASE_INJECTOR_1}, + }, + .write_eraseblocks_expected_ind = 16, .erase_test_name = "Erase test case #15", .write_test_name = "Write test case #15", }, { @@ -743,6 +857,13 @@ {0x0, 0x8, TEST_ERASE_INJECTOR_4}, }, .eraseblocks_expected_ind = 4, + .write_eraseblocks_expected = { + {0x8, 0x8, TEST_ERASE_INJECTOR_4}, + {0x0, 0x10, TEST_ERASE_INJECTOR_5}, + {0x0, 0x8, TEST_ERASE_INJECTOR_4}, + {0x0, 0x8, TEST_ERASE_INJECTOR_4}, + }, + .write_eraseblocks_expected_ind = 4, .erase_test_name = "Erase test case #16", .write_test_name = "Write test case #16", }, { @@ -765,6 +886,8 @@ 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16}, .eraseblocks_expected = {{0x0, 0x10, TEST_ERASE_INJECTOR_5}, {0x0, 0x8, TEST_ERASE_INJECTOR_4}}, .eraseblocks_expected_ind = 2, + .write_eraseblocks_expected = {{0x0, 0x10, TEST_ERASE_INJECTOR_5}, {0x0, 0x8, TEST_ERASE_INJECTOR_4}}, + .write_eraseblocks_expected_ind = 2, .erase_test_name = "Erase test case #17", .write_test_name = "Write test case #17", }, { @@ -787,6 +910,8 @@ 0x14, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16}, .eraseblocks_expected = {{0x8, 0x8, TEST_ERASE_INJECTOR_4}, {0x0, 0x10, TEST_ERASE_INJECTOR_5}}, .eraseblocks_expected_ind = 2, + .write_eraseblocks_expected = {{0x8, 0x8, TEST_ERASE_INJECTOR_4}, {0x0, 0x10, TEST_ERASE_INJECTOR_5}}, + .write_eraseblocks_expected_ind = 2, .erase_test_name = "Erase test case #18", .write_test_name = "Write test case #18", }, { @@ -808,8 +933,43 @@ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, .eraseblocks_expected = {{0x0, 0x8, TEST_ERASE_INJECTOR_4}}, .eraseblocks_expected_ind = 1, + .write_eraseblocks_expected = {{0x0, 0x8, TEST_ERASE_INJECTOR_4}}, + .write_eraseblocks_expected_ind = 1, .erase_test_name = "Erase test case #19", .write_test_name = "Write test case #19", + }, { + /* + * Test case #20 + * + * Initial vs written: 3s+1d+3s+1d+3s+1d+3d+1s + * Layout with one region covering the whole chip + * Chip with eraseblocks 1, 4, 16. + */ + .chip = &chip_1_4_16, + .regions = {{0, MOCK_CHIP_SIZE - 1, "mock chip"}, {MOCK_CHIP_SIZE, MIN_REAL_CHIP_SIZE - 1, "longtail"}}, + .initial_buf = {0x0, 0x1, 0x2, 0xf, 0x4, 0x5, 0x6, 0xf, + 0x8, 0x9, 0xa, 0xf, 0xf, 0xf, 0xf, 0x1f}, + .erased_buf = {ERASE_VALUE, ERASE_VALUE, ERASE_VALUE, ERASE_VALUE, + ERASE_VALUE, ERASE_VALUE, ERASE_VALUE, ERASE_VALUE, + ERASE_VALUE, ERASE_VALUE, ERASE_VALUE, ERASE_VALUE, + ERASE_VALUE, ERASE_VALUE, ERASE_VALUE, ERASE_VALUE}, + .written_buf = {0x01, 0x11, 0x22, 0xf, 0x44, 0x55, 0x66, 0xf, + 0x88, 0x99, 0xaa, 0xf, 0xf, 0xf, 0xf, 0xf1}, + .eraseblocks_expected = {{0x0, 0x10, TEST_ERASE_INJECTOR_5}}, + .eraseblocks_expected_ind = 1, + .write_eraseblocks_expected = {{0x0, 0x1, TEST_ERASE_INJECTOR_1}, + {0x1, 0x1, TEST_ERASE_INJECTOR_1}, + {0x2, 0x1, TEST_ERASE_INJECTOR_1}, + {0x4, 0x1, TEST_ERASE_INJECTOR_1}, + {0x5, 0x1, TEST_ERASE_INJECTOR_1}, + {0x6, 0x1, TEST_ERASE_INJECTOR_1}, + {0x8, 0x1, TEST_ERASE_INJECTOR_1}, + {0x9, 0x1, TEST_ERASE_INJECTOR_1}, + {0xa, 0x1, TEST_ERASE_INJECTOR_1}, + {0xf, 0x1, TEST_ERASE_INJECTOR_1}}, + .write_eraseblocks_expected_ind = 10, + .erase_test_name = "Erase test case #20", + .write_test_name = "Write test case #20", }, }; @@ -1180,6 +1340,13 @@ int chip_written = !memcmp(g_state.buf, current_test_case->written_buf, MOCK_CHIP_SIZE); + int eraseblocks_in_order = !memcmp(g_state.eraseblocks_actual, + current_test_case->write_eraseblocks_expected, + current_test_case->write_eraseblocks_expected_ind * sizeof(struct erase_invoke)); + + int eraseblocks_invocations = (g_state.eraseblocks_actual_ind == + current_test_case->write_eraseblocks_expected_ind); + int chip_verified = 1; for (unsigned int i = 0; i <= verify_end_boundary; i++) if (g_state.was_modified[i] && !g_state.was_verified[i]) { @@ -1194,6 +1361,22 @@ printf("Written chip memory state for %s is WRONG\n", current_test_case->write_test_name); + if (eraseblocks_in_order) + printf("Eraseblocks order of invocation for %s is CORRECT\n", + current_test_case->write_test_name); + else + printf("Eraseblocks order of invocation for %s is WRONG\n", + current_test_case->write_test_name); + + if (eraseblocks_invocations) + printf("Eraseblocks number of invocations for %s is CORRECT\n", + current_test_case->write_test_name); + else + printf("Eraseblocks number of invocations for %s is WRONG, expected %d actual %d\n", + current_test_case->write_test_name, + current_test_case->write_eraseblocks_expected_ind, + g_state.eraseblocks_actual_ind); + if (chip_verified) printf("Written chip memory state for %s was verified successfully\n", current_test_case->write_test_name); @@ -1203,6 +1386,8 @@ all_write_test_result |= ret; all_write_test_result |= !chip_written; + all_write_test_result |= !eraseblocks_in_order; + all_write_test_result |= !eraseblocks_invocations; all_write_test_result |= !chip_verified; teardown_chip(&layout); -- To view, visit https://review.coreboot.org/c/flashrom/+/84783?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: I558fded2b9f876e33ca92dea324d90ef73f6a2be Gerrit-Change-Number: 84783 Gerrit-PatchSet: 1 Gerrit-Owner: Anastasia Klimchuk <aklm(a)chromium.org>

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[M] Change in flashrom[main]: flashchips: add GD25F64F
by Anastasia Klimchuk (Code Review) 16 Oct '24

16 Oct '24

Anastasia Klimchuk has submitted this change. ( https://review.coreboot.org/c/flashrom/+/84705?usp=email ) ( 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: flashchips: add GD25F64F ...................................................................... flashchips: add GD25F64F GD25F64F: 3V 64Mbit, high performance Tested on ch347 with erase, write, read, and protection Change-Id: I07005f1589b76c8a61a1a744b16dc6b0c9020e11 Signed-off-by: Victor Lim <vlim(a)gigadevice.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/84705 Reviewed-by: Anastasia Klimchuk <aklm(a)chromium.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M flashchips.c M include/flashchips.h 2 files changed, 50 insertions(+), 0 deletions(-) Approvals: Anastasia Klimchuk: Looks good to me, approved build bot (Jenkins): Verified diff --git a/flashchips.c b/flashchips.c index 02eefa4..e56851c 100644 --- a/flashchips.c +++ b/flashchips.c @@ -8139,6 +8139,55 @@ .voltage = {2300, 3600}, }, +{ + .vendor = "GigaDevice", + .name = "GD25F64F", + .bustype = BUS_SPI, + .manufacture_id = GIGADEVICE_ID, + .model_id = GIGADEVICE_GD25F64F, + .total_size = 8192, + .page_size = 256, + /* OTP: 1024B total, 256B reserved; read 0x48; write 0x42, erase 0x44 */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_WRSR2 | FEATURE_WRSR3, + .tested = TEST_OK_PREWB, + .probe = PROBE_SPI_RDID, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 2048} }, + .block_erase = SPI_BLOCK_ERASE_20, + }, { + .eraseblocks = { {32 * 1024, 256} }, + .block_erase = SPI_BLOCK_ERASE_52, + }, { + .eraseblocks = { {64 * 1024, 128} }, + .block_erase = SPI_BLOCK_ERASE_D8, + }, { + .eraseblocks = { {8 * 1024 * 1024, 1} }, + .block_erase = SPI_BLOCK_ERASE_60, + }, { + .eraseblocks = { {8 * 1024 * 1024, 1} }, + .block_erase = SPI_BLOCK_ERASE_C7, + } + }, + .printlock = SPI_PRETTYPRINT_STATUS_REGISTER_BP4_SRWD, + .unlock = SPI_DISABLE_BLOCKPROTECT_BP4_SRWD, /* TODO: 2nd status reg (read with 0x35) */ + .write = SPI_CHIP_WRITE256, + .read = SPI_CHIP_READ, /* Fast read (0x0B) and multi I/O supported */ + .voltage = {2700, 3600}, + .reg_bits = + { + .srp = {STATUS1, 7, RW}, + .srl = {STATUS2, 0, RW}, + .bp = {{STATUS1, 2, RW}, {STATUS1, 3, RW}, {STATUS1, 4, RW}}, + .tb = {STATUS1, 5, RW}, /* Called BP3 in datasheet, acts like TB */ + .sec = {STATUS1, 6, RW}, /* Called BP4 in datasheet, acts like SEC */ + .cmp = {STATUS3, 4, RW}, + }, + .decode_range = DECODE_RANGE_SPI25, + }, + { .vendor = "GigaDevice", .name = "GD25WQ80E", diff --git a/include/flashchips.h b/include/flashchips.h index 5f3bed0..53cc9ec 100644 --- a/include/flashchips.h +++ b/include/flashchips.h @@ -401,6 +401,7 @@ #define GIGADEVICE_GD25VQ41B 0x4213 /* Same as GD25VQ40C, can be distinguished by SFDP */ #define GIGADEVICE_GD25VQ80C 0x4214 #define GIGADEVICE_GD25VQ16C 0x4215 +#define GIGADEVICE_GD25F64F 0x4317 #define GIGADEVICE_GD25LQ40 0x6013 #define GIGADEVICE_GD25LQ80 0x6014 #define GIGADEVICE_GD25LQ16 0x6015 -- To view, visit https://review.coreboot.org/c/flashrom/+/84705?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: I07005f1589b76c8a61a1a744b16dc6b0c9020e11 Gerrit-Change-Number: 84705 Gerrit-PatchSet: 3 Gerrit-Owner: Victor Lim <vlim(a)gigadevice.com> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in flashrom[main]: flashchips: Add Support for XMC XM25LU64C
by Ssunk (Code Review) 15 Oct '24

15 Oct '24

Ssunk has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/84775?usp=email ) Change subject: flashchips: Add Support for XMC XM25LU64C ...................................................................... flashchips: Add Support for XMC XM25LU64C Add initial support for the SPI flash chip XM25LU64C Datasheet link: https://www.xmcwh.com/uploads/954/XM25LU64C%20_%20Ver1.4.pdf Tested with ch341a programmer: probe, read, write, erase Change-Id: I8d1af7fbfb4c45db09ed5ac82c683d273c8151c7 Signed-off-by: Kan Sun <ssunkkan(a)gmail.com> --- M flashchips.c M include/flashchips.h 2 files changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/75/84775/1 diff --git a/flashchips.c b/flashchips.c index 02eefa4..15ee3cd 100644 --- a/flashchips.c +++ b/flashchips.c @@ -22686,7 +22686,7 @@ { .vendor = "XMC", - .name = "XM25QU64C", + .name = "XM25QU64C/XM25LU64", .bustype = BUS_SPI, .manufacture_id = ST_ID, .model_id = XMC_XM25QU64C, diff --git a/include/flashchips.h b/include/flashchips.h index 5f3bed0..1403cf3 100644 --- a/include/flashchips.h +++ b/include/flashchips.h @@ -854,7 +854,7 @@ #define ST_M45PE80 0x4014 /* Same as XM25QH80B */ #define ST_M45PE16 0x4015 #define XMC_XM25QH64C 0x4017 /* Same as XM25QH64D */ -#define XMC_XM25QU64C 0x4117 +#define XMC_XM25QU64C 0x4117 /* Same as XM25LU64C */ #define XMC_XM25QU80B 0x5014 #define XMC_XM25QH16C 0x4015 /* Same as XM25QH16D */ #define XMC_XM25QU16C 0x5015 -- To view, visit https://review.coreboot.org/c/flashrom/+/84775?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: I8d1af7fbfb4c45db09ed5ac82c683d273c8151c7 Gerrit-Change-Number: 84775 Gerrit-PatchSet: 1 Gerrit-Owner: Ssunk <ssunkkan(a)gmail.com>

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[S] Change in flashrom[main]: flashchips: add Winbond W25R512NW / W74M51NW
by Alexandru Stan (Code Review) 15 Oct '24

15 Oct '24

Attention is currently required from: Anastasia Klimchuk, Nikolai Artemiev, Stefan Reinauer. Alexandru Stan has posted comments on this change by Alexandru Stan. ( https://review.coreboot.org/c/flashrom/+/84752?usp=email ) Change subject: flashchips: add Winbond W25R512NW / W74M51NW ...................................................................... Patch Set 2: (6 comments) Patchset: PS2: PTAL. I'm pretty sure I successfully confirmed every other `.property =` that I did not comment about already with the datasheet. Commit Message: https://review.coreboot.org/c/flashrom/+/84752/comment/758ce844_3b56fa42?us… : PS1, Line 8: : I don't actually have a datasheet for this (so feel free to reject this : CL) > Thank you for contribution! No I won't reject it so easily, my first reaction is to try and find the […] Still working on this, I just got a datasheet myself, but not sure how distributable it is (since I'm not Winbond), asking around for now (could you check your gdrive perhaps ;) but 64MB might be a little big for chromeos). https://review.coreboot.org/c/flashrom/+/84752/comment/205d28bc_f9fb6ba2?us… : PS1, Line 10: I just bruteforced it > This is so cool! :) Yay, the datasheet (that I just internally aquired) confirms my work! File flashchips.c: https://review.coreboot.org/c/flashrom/+/84752/comment/990f97c0_f49ef469?us… : PS1, Line 20271: 1650 Datasheet disagreed here. File flashchips.c: https://review.coreboot.org/c/flashrom/+/84752/comment/d023e13c_dd2e7af4?us… : PS2, Line 20239: 1024B total, 256B reserved Again, copied this comment from that Winbond chip. From the datasheet it's worded differently (3* 256B), but maybe the same? https://review.coreboot.org/c/flashrom/+/84752/comment/0a08bcb9_9e9bfd07?us… : PS2, Line 20269: .printlock = SPI_PRETTYPRINT_STATUS_REGISTER_BP3_SRWD, : .unlock = SPI_DISABLE_BLOCKPROTECT, : Given I haven't tested WP, I don't know if these are good. I copied the other chip's definition which has the same thing. Someone better at testing this should confirm. Though given `.tested = TEST_OK_PREW,` maybe this is ok enough? -- To view, visit https://review.coreboot.org/c/flashrom/+/84752?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: Ibf670e4014a22e4636789768b759cb51f75cd046 Gerrit-Change-Number: 84752 Gerrit-PatchSet: 2 Gerrit-Owner: Alexandru Stan <ams(a)frame.work> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Attention: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Comment-Date: Tue, 15 Oct 2024 04:23:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Anastasia Klimchuk <aklm(a)chromium.org>

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