February 2023 - flashrom-gerrit

[L] Change in flashrom[master]: wbsio_spi.c: Drop unmaintained driver path
by Angel Pons (Code Review) 07 Feb '23

07 Feb '23

Attention is currently required from: Thomas Heijligen, Edward O'Callaghan. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/72828 ) Change subject: wbsio_spi.c: Drop unmaintained driver path ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: As mentioned in the ML, could this be encapsulated so that the functionality doesn't need to be dropped? -- To view, visit https://review.coreboot.org/c/flashrom/+/72828 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I25c4d02126fcf183662dec73a800cac3988a1773 Gerrit-Change-Number: 72828 Gerrit-PatchSet: 2 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Thomas Heijligen <src(a)posteo.de> Gerrit-Attention: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Comment-Date: Tue, 07 Feb 2023 13:58:02 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in flashrom[master]: wbsio_spi.c: Convert to direct driver entry
by Edward O'Callaghan (Code Review) 07 Feb '23

07 Feb '23

Attention is currently required from: Thomas Heijligen. Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/72864 ) Change subject: wbsio_spi.c: Convert to direct driver entry ...................................................................... wbsio_spi.c: Convert to direct driver entry Change-Id: I54b166048089bc502b99a345c02e91894590894e Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> --- M Makefile M include/programmer.h M meson.build M programmer_table.c M wbsio_spi.c 5 files changed, 76 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/64/72864/1 diff --git a/Makefile b/Makefile index 2ebd370..5eaf241 100644 --- a/Makefile +++ b/Makefile @@ -135,6 +135,7 @@ CONFIG_NICREALTEK \ CONFIG_RAYER_SPI \ CONFIG_SATAMV \ + CONFIG_WBSIO_SPI \ DEPENDS_ON_LIBPCI := \ CONFIG_ATAHPT \ @@ -465,6 +466,9 @@ # Disables Parade LSPCON support until the i2c helper supports multiple systems. CONFIG_PARADE_LSPCON ?= no +# Disables wbsio_spi support. +CONFIG_WBSIO_SPI ?= no + # Disables MediaTek support until the i2c helper supports multiple systems. CONFIG_MEDIATEK_I2C_SPI ?= no @@ -584,7 +588,7 @@ ifeq ($(CONFIG_INTERNAL) $(CONFIG_INTERNAL_X86), yes yes) FEATURE_FLAGS += -D'CONFIG_INTERNAL=1' PROGRAMMER_OBJS += processor_enable.o chipset_enable.o board_enable.o cbtable.o \ - internal.o it87spi.o sb600spi.o superio.o amd_imc.o wbsio_spi.o mcp6x_spi.o \ + internal.o it87spi.o sb600spi.o superio.o amd_imc.o mcp6x_spi.o \ ichspi.o dmi.o known_boards.o ACTIVE_PROGRAMMERS += internal endif @@ -696,6 +700,12 @@ ACTIVE_PROGRAMMERS += parade_lspcon endif +ifeq ($(CONFIG_WBSIO_SPI), yes) +FEATURE_FLAGS += -D'CONFIG_WBSIO_SPI=1' +PROGRAMMER_OBJS += wbsio_spi.o +ACTIVE_PROGRAMMERS += wbsio_spi +endif + ifeq ($(CONFIG_MEDIATEK_I2C_SPI), yes) FEATURE_FLAGS += -D'CONFIG_MEDIATEK_I2C_SPI=1' PROGRAMMER_OBJS += mediatek_i2c_spi.o diff --git a/include/programmer.h b/include/programmer.h index db32b2c..62e0779 100644 --- a/include/programmer.h +++ b/include/programmer.h @@ -73,6 +73,7 @@ extern const struct programmer_entry programmer_linux_mtd; extern const struct programmer_entry programmer_linux_spi; extern const struct programmer_entry programmer_parade_lspcon; +extern const struct programmer_entry programmer_wbsio_spi; extern const struct programmer_entry programmer_mediatek_i2c_spi; extern const struct programmer_entry programmer_mstarddc_spi; extern const struct programmer_entry programmer_ni845x_spi; @@ -391,9 +392,6 @@ /* sb600spi.c */ int sb600_probe_spi(const struct programmer_cfg *cfg, struct pci_dev *dev); - -/* wbsio_spi.c */ -int wbsio_check_for_spi(void); #endif /* opaque.c */ diff --git a/meson.build b/meson.build index 57ac438..d0ed2b7 100644 --- a/meson.build +++ b/meson.build @@ -249,7 +249,6 @@ 'sb600spi.c', 'superio.c', 'amd_imc.c', - 'wbsio_spi.c', 'mcp6x_spi.c', 'ichspi.c', 'dmi.c', @@ -308,6 +307,14 @@ 'flags' : [ '-DCONFIG_PARADE_LSPCON=1' ], 'default' : false }, + 'wbsio_spi' : { + 'systems' : [ 'linux' ], + 'deps' : [ linux_headers ], + 'groups' : [ group_i2c ], + 'srcs' : files('wbsio_spi.c'), + 'flags' : [ '-DCONFIG_WBSIO_SPI=1' ], + 'default' : false, + }, 'mediatek_i2c_spi' : { 'systems' : [ 'linux' ], 'deps' : [ linux_headers ], diff --git a/programmer_table.c b/programmer_table.c index d58a155..e1bb805 100644 --- a/programmer_table.c +++ b/programmer_table.c @@ -128,6 +128,10 @@ &programmer_parade_lspcon, #endif +#if CONFIG_WBSIO_SPI == 1 + &programmer_wbsio_spi, +#endif + #if CONFIG_MEDIATEK_I2C_SPI == 1 &programmer_mediatek_i2c_spi, #endif diff --git a/wbsio_spi.c b/wbsio_spi.c index d635a09..d6c0f16 100644 --- a/wbsio_spi.c +++ b/wbsio_spi.c @@ -196,9 +196,44 @@ .probe_opcode = default_spi_probe_opcode, }; -int wbsio_check_for_spi(void) +static int get_params(const struct programmer_cfg *cfg, bool *allow_brick) +{ + char *param_str; + int ret = 0; + + *allow_brick = false; /* Default behaviour is to bail. */ + param_str = extract_programmer_param_str(cfg, "allow_brick"); + if (param_str) { + if (!strcmp(param_str, "yes")) { + *allow_brick = true; + } else { + msg_perr("%s: Incorrect param format, allow_brick=yes.\n", __func__); + ret = SPI_GENERIC_ERROR; + } + } + free(param_str); + + return ret; +} + +static int wbsio_spi_init(const struct programmer_cfg *cfg) { uint16_t wbsio_spibase = 0; + bool allow_brick; + + if (get_params(cfg, &allow_brick)) + return SPI_GENERIC_ERROR; + + /* + * TODO: Once board_enable can facilitate safe allow listing + * then this can be removed. + */ + if (!allow_brick) { + msg_perr("%s: For Super I/O drivers you must explicitly 'allow_brick=yes'. ", __func__); + msg_perr("There is currently no way to determine if the programmer works on a board. " + "Set 'allow_brick=yes' if you are sure you know what you are doing.\n"); + return SPI_GENERIC_ERROR; + } if (0 == (wbsio_spibase = wbsio_get_spibase(WBSIO_PORT1))) if (0 == (wbsio_spibase = wbsio_get_spibase(WBSIO_PORT2))) @@ -219,3 +254,9 @@ return register_spi_master(&spi_master_wbsio, data); } + +const struct programmer_entry programmer_wbsio_spi = { + .name = "wbsio_spi", + .type = OTHER, + .init = wbsio_spi_init, +}; -- To view, visit https://review.coreboot.org/c/flashrom/+/72864 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I54b166048089bc502b99a345c02e91894590894e Gerrit-Change-Number: 72864 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Attention: Thomas Heijligen <src(a)posteo.de> Gerrit-MessageType: newchange

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[S] Change in flashrom[master]: board_enable.c: Drop Intel D201GLY entry for wbsio_spi drv
by Edward O'Callaghan (Code Review) 07 Feb '23

07 Feb '23

Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/72863 ) Change subject: board_enable.c: Drop Intel D201GLY entry for wbsio_spi drv ...................................................................... board_enable.c: Drop Intel D201GLY entry for wbsio_spi drv Change-Id: Iab1e28c61ecb5a03c68cb935191ed494edf9bb28 Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> --- M board_enable.c 1 file changed, 10 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/63/72863/1 diff --git a/board_enable.c b/board_enable.c index d35b151..6032529 100644 --- a/board_enable.c +++ b/board_enable.c @@ -2467,7 +2467,6 @@ {0x10de, 0x0369, 0x103c, 0x12fe, 0x10de, 0x0364, 0x103c, 0x12fe, NULL, "hp", "xw9400", P3, "HP", "xw9400", 0, OK, nvidia_mcp_gpio5_raise}, {0x8086, 0x27A0, 0, 0, 0x8086, 0x27B9, 0, 0, NULL, "ibase", "mb899", P3, "IBASE", "MB899", 0, OK, intel_ich_gpio26_raise}, {0x1166, 0x0205, 0x1014, 0x0347, 0x1002, 0x515E, 0x1014, 0x0325, NULL, NULL, NULL, P3, "IBM", "x3455", 0, OK, board_ibm_x3455}, - {0x1039, 0x5513, 0x8086, 0xd61f, 0x1039, 0x6330, 0x8086, 0xd61f, NULL, NULL, NULL, P3, "Intel", "D201GLY", 0, OK, wbsio_check_for_spi}, {0x8086, 0x27b8, 0x8086, 0xd606, 0x8086, 0x2770, 0x8086, 0xd606, "^D945GCNL$", NULL, NULL, P2, "Intel", "D945GCNL", 0, OK, p2_not_a_laptop}, {0x8086, 0x7190, 0, 0, 0x8086, 0x7110, 0, 0, "^SE440BX-2$", NULL, NULL, P3, "Intel", "SE440BX-2", 0, NT, intel_piix4_gpo27_lower}, {0x1022, 0x7468, 0, 0, 0x1022, 0x7460, 0, 0, NULL, "iwill", "dk8_htx", P3, "IWILL", "DK8-HTX", 0, OK, w83627hf_gpio24_raise_2e}, -- To view, visit https://review.coreboot.org/c/flashrom/+/72863 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Iab1e28c61ecb5a03c68cb935191ed494edf9bb28 Gerrit-Change-Number: 72863 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: newchange

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[S] Change in flashrom[master]: dummyflasher: use new API to register shutdown function
by Anastasia Klimchuk (Code Review) 06 Feb '23

06 Feb '23

Attention is currently required from: Edward O'Callaghan, Alexander Goncharov. Anastasia Klimchuk has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/72408 ) Change subject: dummyflasher: use new API to register shutdown function ...................................................................... Patch Set 2: (1 comment) File dummyflasher.c: https://review.coreboot.org/c/flashrom/+/72408/comment/96df9a22_2e108c33 PS2, Line 1416: data->refs_cnt += ((dummy_buses_supported & BUS_PROG) != BUS_NONE); : data->refs_cnt += ((dummy_buses_supported & BUS_NONSPI) != BUS_NONE); : data->refs_cnt += ((dummy_buses_supported & BUS_SPI) != BUS_NONE); : : #if 0 : data->refs_cnt += (dummy_buses_supported & BUS_PROG) ? 1 : 0; : data->refs_cnt += (dummy_buses_supported & BUS_NONSPI) ? 1 : 0; : data->refs_cnt += (dummy_buses_supported & BUS_SPI) ? 1 : 0; : #endif > I thought about it at first sight. But this approach may potentially cause flashrom to crash. […] Okay, I understand, thanks for explanation! The main thing I take from this is: if any one register_master fails, init fails. But the code at the moment is trying to register all masters anyway. Even though just one failure makes init fail. I still want to use the same conditions. Technically, refs_cnt should increase for every successful register master. So an amendment to my initial idea: add if (!ret) refs_cnt++; into every if below ? -- To view, visit https://review.coreboot.org/c/flashrom/+/72408 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I0c67c25b0f53cd8c564c4ea0f09f2728e856f6ea Gerrit-Change-Number: 72408 Gerrit-PatchSet: 2 Gerrit-Owner: Alexander Goncharov <chat(a)joursoir.net> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Attention: Alexander Goncharov <chat(a)joursoir.net> Gerrit-Comment-Date: Mon, 06 Feb 2023 19:42:21 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Anastasia Klimchuk <aklm(a)chromium.org> Comment-In-Reply-To: Alexander Goncharov <chat(a)joursoir.net> Gerrit-MessageType: comment

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[M] Change in flashrom[master]: flashrom.c: Add new erase_by_layout and walk_by_layout implementations
by Thomas Heijligen (Code Review) 06 Feb '23

06 Feb '23

Attention is currently required from: Simon Buhrow, Aarya, Anastasia Klimchuk. Thomas Heijligen has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/71173 ) Change subject: flashrom.c: Add new erase_by_layout and walk_by_layout implementations ...................................................................... Patch Set 22: Code-Review+2 -- To view, visit https://review.coreboot.org/c/flashrom/+/71173 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Id79ae943eb9d6a817da28381db477725834faaf6 Gerrit-Change-Number: 71173 Gerrit-PatchSet: 22 Gerrit-Owner: Aarya <aarya.chaumal(a)gmail.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Simon Buhrow Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Attention: Simon Buhrow Gerrit-Attention: Aarya <aarya.chaumal(a)gmail.com> Gerrit-Attention: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Comment-Date: Mon, 06 Feb 2023 19:16:59 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[L] Change in flashrom[master]: flashrom.c: Add functions for new erase selction algorithm
by Thomas Heijligen (Code Review) 06 Feb '23

06 Feb '23

Attention is currently required from: Simon Buhrow, Aarya, Anastasia Klimchuk. Thomas Heijligen has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/65844 ) Change subject: flashrom.c: Add functions for new erase selction algorithm ...................................................................... Patch Set 87: (1 comment) Patchset: PS87: * The files are named `erasure_layout.h`. Is this intentional? You named the include guard `ERASE_LAYOUT_H` * We have the `/include/` directory for header files -- To view, visit https://review.coreboot.org/c/flashrom/+/65844 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Ic57ca1cca3d1646543f6b5939ba9c35db8d08256 Gerrit-Change-Number: 65844 Gerrit-PatchSet: 87 Gerrit-Owner: Aarya <aarya.chaumal(a)gmail.com> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Simon Buhrow Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Simon Buhrow Gerrit-Attention: Aarya <aarya.chaumal(a)gmail.com> Gerrit-Attention: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Comment-Date: Mon, 06 Feb 2023 19:14:05 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in flashrom[master]: flashrom.c: Add switch for legacy impl of erasure path
by Thomas Heijligen (Code Review) 06 Feb '23

06 Feb '23

Attention is currently required from: Felix Singer, Edward O'Callaghan, Aarya. Thomas Heijligen has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/71119 ) Change subject: flashrom.c: Add switch for legacy impl of erasure path ...................................................................... Patch Set 13: Code-Review+2 (1 comment) File flashrom.c: https://review.coreboot.org/c/flashrom/+/71119/comment/7115e1a3_085eec62 PS12, Line 37: use_legacy_erase_path > Cool. […] That's a good plan! Thanks for elaborating it. -- To view, visit https://review.coreboot.org/c/flashrom/+/71119 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Ib5660db0067c1c799dcb5c8e83b4a4826b236442 Gerrit-Change-Number: 71119 Gerrit-PatchSet: 13 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Aarya <aarya.chaumal(a)gmail.com> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Attention: Aarya <aarya.chaumal(a)gmail.com> Gerrit-Comment-Date: Mon, 06 Feb 2023 18:59:55 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Edward O'Callaghan <quasisec(a)chromium.org> Comment-In-Reply-To: Aarya <aarya.chaumal(a)gmail.com> Comment-In-Reply-To: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-MessageType: comment

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[M] Change in flashrom[master]: flashrom_tester: Use Range and usize for all ranges
by Nikolai Artemiev (Code Review) 06 Feb '23

06 Feb '23

Attention is currently required from: Evan Benn. Nikolai Artemiev has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/72004 ) Change subject: flashrom_tester: Use Range and usize for all ranges ...................................................................... Patch Set 9: Code-Review+1 -- To view, visit https://review.coreboot.org/c/flashrom/+/72004 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Ic09be66c3598acf45fbe8952093006a9b185810a Gerrit-Change-Number: 72004 Gerrit-PatchSet: 9 Gerrit-Owner: Evan Benn <evanbenn(a)google.com> Gerrit-Reviewer: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: Peter Marheine <pmarheine(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Evan Benn <evanbenn(a)google.com> Gerrit-Comment-Date: Mon, 06 Feb 2023 02:45:22 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[L] Change in flashrom[master]: wbsio_spi.c: Drop unmaintained driver path
by Edward O'Callaghan (Code Review) 06 Feb '23

06 Feb '23

Attention is currently required from: Thomas Heijligen. Hello Thomas Heijligen, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/flashrom/+/72828 to look at the new patch set (#2). Change subject: wbsio_spi.c: Drop unmaintained driver path ...................................................................... wbsio_spi.c: Drop unmaintained driver path The 'Intel D201GLY' board is extremely old and the specialised superio path it uses is highly bespoke to it. This causes a undue maintenance burden to core flashrom data structures in how the spi driver entry-point is dispatched via a board_enable hook. Therefore in the cost-benefit just deprecate it to allow the overall flashrom project to progress. Change-Id: I25c4d02126fcf183662dec73a800cac3988a1773 Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> --- M Makefile M board_enable.c M include/programmer.h M meson.build D wbsio_spi.c 5 files changed, 21 insertions(+), 231 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/28/72828/2 -- To view, visit https://review.coreboot.org/c/flashrom/+/72828 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I25c4d02126fcf183662dec73a800cac3988a1773 Gerrit-Change-Number: 72828 Gerrit-PatchSet: 2 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Attention: Thomas Heijligen <src(a)posteo.de> Gerrit-MessageType: newpatchset

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[M] Change in flashrom[master]: wbsio_spi.c: Drop unmaintained driver path
by Edward O'Callaghan (Code Review) 06 Feb '23

06 Feb '23

Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/72828 ) Change subject: wbsio_spi.c: Drop unmaintained driver path ...................................................................... wbsio_spi.c: Drop unmaintained driver path The 'Intel D201GLY' board is extremely old and the specialised superio path it uses is highly bespoke to it. This causes a undue maintenance burden to core flashrom data structures in how the spi driver entry-point is dispatched via a board_enable hook. Therefore in the cost-benefit just deprecate it to allow the overall flashrom project to progress. Change-Id: I25c4d02126fcf183662dec73a800cac3988a1773 Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> --- M Makefile M board_enable.c M include/programmer.h M meson.build D wbsio_spi.c 5 files changed, 19 insertions(+), 227 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/28/72828/1 diff --git a/Makefile b/Makefile index 2ebd370..3e8b1f5 100644 --- a/Makefile +++ b/Makefile @@ -584,7 +584,7 @@ ifeq ($(CONFIG_INTERNAL) $(CONFIG_INTERNAL_X86), yes yes) FEATURE_FLAGS += -D'CONFIG_INTERNAL=1' PROGRAMMER_OBJS += processor_enable.o chipset_enable.o board_enable.o cbtable.o \ - internal.o it87spi.o sb600spi.o superio.o amd_imc.o wbsio_spi.o mcp6x_spi.o \ + internal.o it87spi.o sb600spi.o superio.o amd_imc.o mcp6x_spi.o \ ichspi.o dmi.o known_boards.o ACTIVE_PROGRAMMERS += internal endif diff --git a/board_enable.c b/board_enable.c index d35b151..6032529 100644 --- a/board_enable.c +++ b/board_enable.c @@ -2467,7 +2467,6 @@ {0x10de, 0x0369, 0x103c, 0x12fe, 0x10de, 0x0364, 0x103c, 0x12fe, NULL, "hp", "xw9400", P3, "HP", "xw9400", 0, OK, nvidia_mcp_gpio5_raise}, {0x8086, 0x27A0, 0, 0, 0x8086, 0x27B9, 0, 0, NULL, "ibase", "mb899", P3, "IBASE", "MB899", 0, OK, intel_ich_gpio26_raise}, {0x1166, 0x0205, 0x1014, 0x0347, 0x1002, 0x515E, 0x1014, 0x0325, NULL, NULL, NULL, P3, "IBM", "x3455", 0, OK, board_ibm_x3455}, - {0x1039, 0x5513, 0x8086, 0xd61f, 0x1039, 0x6330, 0x8086, 0xd61f, NULL, NULL, NULL, P3, "Intel", "D201GLY", 0, OK, wbsio_check_for_spi}, {0x8086, 0x27b8, 0x8086, 0xd606, 0x8086, 0x2770, 0x8086, 0xd606, "^D945GCNL$", NULL, NULL, P2, "Intel", "D945GCNL", 0, OK, p2_not_a_laptop}, {0x8086, 0x7190, 0, 0, 0x8086, 0x7110, 0, 0, "^SE440BX-2$", NULL, NULL, P3, "Intel", "SE440BX-2", 0, NT, intel_piix4_gpo27_lower}, {0x1022, 0x7468, 0, 0, 0x1022, 0x7460, 0, 0, NULL, "iwill", "dk8_htx", P3, "IWILL", "DK8-HTX", 0, OK, w83627hf_gpio24_raise_2e}, diff --git a/include/programmer.h b/include/programmer.h index db32b2c..1ea53cd 100644 --- a/include/programmer.h +++ b/include/programmer.h @@ -391,9 +391,6 @@ /* sb600spi.c */ int sb600_probe_spi(const struct programmer_cfg *cfg, struct pci_dev *dev); - -/* wbsio_spi.c */ -int wbsio_check_for_spi(void); #endif /* opaque.c */ diff --git a/meson.build b/meson.build index 57ac438..2e92fa5 100644 --- a/meson.build +++ b/meson.build @@ -249,7 +249,6 @@ 'sb600spi.c', 'superio.c', 'amd_imc.c', - 'wbsio_spi.c', 'mcp6x_spi.c', 'ichspi.c', 'dmi.c', diff --git a/wbsio_spi.c b/wbsio_spi.c deleted file mode 100644 index d635a09..0000000 --- a/wbsio_spi.c +++ /dev/null @@ -1,221 +0,0 @@ -/* - * This file is part of the flashrom project. - * - * Copyright (C) 2008 Peter Stuge <peter(a)stuge.se> - * Copyright (C) 2009,2010 Carl-Daniel Hailfinger - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <stdlib.h> - -#include "flash.h" -#include "chipdrivers.h" -#include "programmer.h" -#include "hwaccess_physmap.h" -#include "hwaccess_x86_io.h" -#include "spi.h" - -#define WBSIO_PORT1 0x2e -#define WBSIO_PORT2 0x4e - -struct wbsio_spi_data { - uint16_t spibase; -}; - -static uint16_t wbsio_get_spibase(uint16_t port) -{ - uint8_t id; - uint16_t flashport = 0; - - w836xx_ext_enter(port); - id = sio_read(port, 0x20); - if (id != 0xa0) { - msg_perr("\nW83627 not found at 0x%x, id=0x%02x want=0xa0.\n", port, id); - goto done; - } - - if (0 == (sio_read(port, 0x24) & 2)) { - msg_perr("\nW83627 found at 0x%x, but SPI pins are not enabled. (CR[0x24] bit 1=0)\n", port); - goto done; - } - - sio_write(port, 0x07, 0x06); - if (0 == (sio_read(port, 0x30) & 1)) { - msg_perr("\nW83627 found at 0x%x, but SPI is not enabled. (LDN6[0x30] bit 0=0)\n", port); - goto done; - } - - flashport = (sio_read(port, 0x62) << 8) | sio_read(port, 0x63); - -done: - w836xx_ext_leave(port); - return flashport; -} - -/* W83627DHG has 11 command modes: - * 1=1 command only - * 2=1 command+1 data write - * 3=1 command+2 data read - * 4=1 command+3 address - * 5=1 command+3 address+1 data write - * 6=1 command+3 address+4 data write - * 7=1 command+3 address+1 dummy address inserted by wbsio+4 data read - * 8=1 command+3 address+1 data read - * 9=1 command+3 address+2 data read - * a=1 command+3 address+3 data read - * b=1 command+3 address+4 data read - * - * mode[7:4] holds the command mode - * mode[3:0] holds SPI address bits [19:16] - * - * The Winbond SPI master only supports 20 bit addresses on the SPI bus. :\ - * Would one more byte of RAM in the chip (to get all 24 bits) really make - * such a big difference? - */ -static int wbsio_spi_send_command(const struct flashctx *flash, unsigned int writecnt, - unsigned int readcnt, - const unsigned char *writearr, - unsigned char *readarr) -{ - unsigned int i; - uint8_t mode = 0; - - msg_pspew("%s:", __func__); - - const struct wbsio_spi_data *data = - (const struct wbsio_spi_data *)flash->mst->spi.data; - - if (1 == writecnt && 0 == readcnt) { - mode = 0x10; - } else if (2 == writecnt && 0 == readcnt) { - OUTB(writearr[1], data->spibase + 4); - msg_pspew(" data=0x%02x", writearr[1]); - mode = 0x20; - } else if (1 == writecnt && 2 == readcnt) { - mode = 0x30; - } else if (4 == writecnt && 0 == readcnt) { - msg_pspew(" addr=0x%02x", (writearr[1] & 0x0f)); - for (i = 2; i < writecnt; i++) { - OUTB(writearr[i], data->spibase + i); - msg_pspew("%02x", writearr[i]); - } - mode = 0x40 | (writearr[1] & 0x0f); - } else if (5 == writecnt && 0 == readcnt) { - msg_pspew(" addr=0x%02x", (writearr[1] & 0x0f)); - for (i = 2; i < 4; i++) { - OUTB(writearr[i], data->spibase + i); - msg_pspew("%02x", writearr[i]); - } - OUTB(writearr[i], data->spibase + i); - msg_pspew(" data=0x%02x", writearr[i]); - mode = 0x50 | (writearr[1] & 0x0f); - } else if (8 == writecnt && 0 == readcnt) { - msg_pspew(" addr=0x%02x", (writearr[1] & 0x0f)); - for (i = 2; i < 4; i++) { - OUTB(writearr[i], data->spibase + i); - msg_pspew("%02x", writearr[i]); - } - msg_pspew(" data=0x"); - for (; i < writecnt; i++) { - OUTB(writearr[i], data->spibase + i); - msg_pspew("%02x", writearr[i]); - } - mode = 0x60 | (writearr[1] & 0x0f); - } else if (5 == writecnt && 4 == readcnt) { - /* XXX: TODO not supported by flashrom infrastructure! - * This mode, 7, discards the fifth byte in writecnt, - * but since we can not express that in flashrom, fail - * the operation for now. - */ - ; - } else if (4 == writecnt && readcnt >= 1 && readcnt <= 4) { - msg_pspew(" addr=0x%02x", (writearr[1] & 0x0f)); - for (i = 2; i < writecnt; i++) { - OUTB(writearr[i], data->spibase + i); - msg_pspew("%02x", writearr[i]); - } - mode = ((7 + readcnt) << 4) | (writearr[1] & 0x0f); - } - msg_pspew(" cmd=%02x mode=%02x\n", writearr[0], mode); - - if (!mode) { - msg_perr("%s: unsupported command type wr=%d rd=%d\n", - __func__, writecnt, readcnt); - /* Command type refers to the number of bytes read/written. */ - return SPI_INVALID_LENGTH; - } - - OUTB(writearr[0], data->spibase); - OUTB(mode, data->spibase + 1); - default_delay(10); - - if (!readcnt) - return 0; - - msg_pspew("%s: returning data =", __func__); - for (i = 0; i < readcnt; i++) { - readarr[i] = INB(data->spibase + 4 + i); - msg_pspew(" 0x%02x", readarr[i]); - } - msg_pspew("\n"); - return 0; -} - -static int wbsio_spi_read(struct flashctx *flash, uint8_t *buf, - unsigned int start, unsigned int len) -{ - mmio_readn((void *)(flash->virtual_memory + start), buf, len); - return 0; -} - -static int wbsio_spi_shutdown(void *data) -{ - free(data); - return 0; -} - -static const struct spi_master spi_master_wbsio = { - .max_data_read = MAX_DATA_UNSPECIFIED, - .max_data_write = MAX_DATA_UNSPECIFIED, - .command = wbsio_spi_send_command, - .multicommand = default_spi_send_multicommand, - .map_flash_region = physmap, - .unmap_flash_region = physunmap, - .read = wbsio_spi_read, - .write_256 = spi_chip_write_1, - .write_aai = spi_chip_write_1, - .shutdown = wbsio_spi_shutdown, - .probe_opcode = default_spi_probe_opcode, -}; - -int wbsio_check_for_spi(void) -{ - uint16_t wbsio_spibase = 0; - - if (0 == (wbsio_spibase = wbsio_get_spibase(WBSIO_PORT1))) - if (0 == (wbsio_spibase = wbsio_get_spibase(WBSIO_PORT2))) - return 1; - - msg_pspew("\nwbsio_spibase = 0x%x\n", wbsio_spibase); - - msg_pdbg("%s: Winbond saved on 4 register bits so max chip size is " - "1024 kB!\n", __func__); - max_rom_decode.spi = 1024 * 1024; - - struct wbsio_spi_data *data = calloc(1, sizeof(*data)); - if (!data) { - msg_perr("Unable to allocate space for extra SPI master data.\n"); - return SPI_GENERIC_ERROR; - } - data->spibase = wbsio_spibase; - - return register_spi_master(&spi_master_wbsio, data); -} -- To view, visit https://review.coreboot.org/c/flashrom/+/72828 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I25c4d02126fcf183662dec73a800cac3988a1773 Gerrit-Change-Number: 72828 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: newchange

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flashrom-gerrit February 2023