September 2022 - flashrom-gerrit

[M] Change in flashrom[master]: drivers/: Make 'internal_delay' the default unless defined
by Angel Pons (Code Review) 09 Sep '22

09 Sep '22

Attention is currently required from: Nico Huber, Edward O'Callaghan, Nikolai Artemiev. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/67391 ) Change subject: drivers/: Make 'internal_delay' the default unless defined ...................................................................... Patch Set 3: (1 comment) Commit Message: https://review.coreboot.org/c/flashrom/+/67391/comment/a3855026_5029a297 PS3, Line 13: and paves way : to remove the 'programmer' global handle. > I don't understand the latter part. It doesn't change where the […] I can't connect the dots either. How does this change relate to removing the "programmer" global handle? -- To view, visit https://review.coreboot.org/c/flashrom/+/67391 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I17460bc2c0aebcbb48c8dfa052b260991525cc49 Gerrit-Change-Number: 67391 Gerrit-PatchSet: 3 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: Peter Marheine <pmarheine(a)chromium.org> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Attention: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Comment-Date: Fri, 09 Sep 2022 14:05:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: comment

1 0

[M] Change in flashrom[master]: tree/: Move programmer_delay() out of programmer state machine
by Nico Huber (Code Review) 09 Sep '22

09 Sep '22

Attention is currently required from: Felix Singer, Edward O'Callaghan. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/67393 ) Change subject: tree/: Move programmer_delay() out of programmer state machine ...................................................................... Patch Set 4: (4 comments) Commit Message: https://review.coreboot.org/c/flashrom/+/67393/comment/2d5955e6_2dca1f88 PS4, Line 13: I'm missing the reason for the change. Especially because some aspects regress. Programmers that register multiple masters would need redundant code. It also seems unclear if it would help with the `programmer` global issue. There are more complex programmer drivers that most likely have global state that isn't associated with a specific master. This state needs a place eventually and moving everything into the masters might not work out well. Looking at the libflashrom API, we currently have a `flashctx` at the chip level. This points to a master which gets us most of the state, but not all of it yet. One way would be to extend this chain, i.e. let the master point to a programmer context (something like `struct programmer` + state), and that to a libflashrom context (to be introduced into the API). File flashrom.c: https://review.coreboot.org/c/flashrom/+/67393/comment/940b61ef_a1355cac PS4, Line 219: flash->mst->buses_supported & BUS_SPI In case of multiple buses, this is not necessarily the bus that the flash chip is connected to. I'm not sure if we store that information somewhere in the `flashctx` yet. https://review.coreboot.org/c/flashrom/+/67393/comment/d1cddff2_07a68458 PS4, Line 224: flash->mst->par.delay(usecs); This could probably be better solved by having a common master struct, e.g. common things behind `flash->mst` and there something like `flash->mst->bus` that points to the bus specific things (the current `flash->mst`). File serprog.c: https://review.coreboot.org/c/flashrom/+/67393/comment/47437804_aa18d6b6 PS4, Line 451: }; We would need the delay here too, right? (rhetorical, see comment on commit message) -- To view, visit https://review.coreboot.org/c/flashrom/+/67393 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Id059abb58b31a066a408009073912da2b224d40c Gerrit-Change-Number: 67393 Gerrit-PatchSet: 4 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Peter Marheine <pmarheine(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Alexander Goncharov <chat(a)joursoir.net> Gerrit-CC: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Comment-Date: Fri, 09 Sep 2022 14:04:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

[M] Change in flashrom[master]: flashrom.c:Add function to get a flattened view of the chip erase blocks
by Aarya (Code Review) 09 Sep '22

09 Sep '22

Attention is currently required from: Felix Singer, Simon Buhrow, Nico Huber, Paul Menzel. Aarya has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/65879 ) Change subject: flashrom.c:Add function to get a flattened view of the chip erase blocks ...................................................................... Patch Set 29: (1 comment) Commit Message: https://review.coreboot.org/c/flashrom/+/65879/comment/7e469635_3a8fb18e PS29, Line 7: flashrom.c:Add > I guess the space is missing because the line would exceed the 72 character limit else Yes -- To view, visit https://review.coreboot.org/c/flashrom/+/65879 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Iafe78de00daa55f7114bd4ce09465dd88074ece4 Gerrit-Change-Number: 65879 Gerrit-PatchSet: 29 Gerrit-Owner: Aarya <aarya.chaumal(a)gmail.com> Gerrit-Reviewer: Simon Buhrow Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Simon Buhrow Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Fri, 09 Sep 2022 14:01:41 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Singer <felixsinger(a)posteo.net> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

1 0

[S] Change in flashrom[master]: ichspi: Add Intel Idaville HCC support
by Felix Singer (Code Review) 09 Sep '22

09 Sep '22

Attention is currently required from: Thomas Heijligen, Anastasia Klimchuk, Kevin Yu. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/67438 ) Change subject: ichspi: Add Intel Idaville HCC support ...................................................................... Patch Set 3: (1 comment) Commit Message: https://review.coreboot.org/c/flashrom/+/67438/comment/4ca9e005_5e3a3326 PS3, Line 9: CDF PCH What is CDF? Please write it out. -- To view, visit https://review.coreboot.org/c/flashrom/+/67438 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I3d73b4796f610953d38506794eb20791871ec31f Gerrit-Change-Number: 67438 Gerrit-PatchSet: 3 Gerrit-Owner: Kevin Yu <ykevin(a)celestica.com> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Thomas Heijligen <src(a)posteo.de> Gerrit-Attention: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Attention: Kevin Yu <ykevin(a)celestica.com> Gerrit-Comment-Date: Fri, 09 Sep 2022 13:48:21 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

[S] Change in flashrom[master]: ichspi: Add Intel Idaville HCC support
by Felix Singer (Code Review) 09 Sep '22

09 Sep '22

Attention is currently required from: Thomas Heijligen, Anastasia Klimchuk, Kevin Yu. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/67438 ) Change subject: ichspi: Add Intel Idaville HCC support ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/flashrom/+/67438 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I3d73b4796f610953d38506794eb20791871ec31f Gerrit-Change-Number: 67438 Gerrit-PatchSet: 3 Gerrit-Owner: Kevin Yu <ykevin(a)celestica.com> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Thomas Heijligen <src(a)posteo.de> Gerrit-Attention: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Attention: Kevin Yu <ykevin(a)celestica.com> Gerrit-Comment-Date: Fri, 09 Sep 2022 13:47:04 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

[M] Change in flashrom[master]: drivers/: Make 'internal_delay' the default unless defined
by Nico Huber (Code Review) 09 Sep '22

09 Sep '22

Attention is currently required from: Edward O'Callaghan, Nikolai Artemiev. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/67391 ) Change subject: drivers/: Make 'internal_delay' the default unless defined ...................................................................... Patch Set 3: (1 comment) Commit Message: https://review.coreboot.org/c/flashrom/+/67391/comment/121d6c59_e2468051 PS3, Line 13: and paves way : to remove the 'programmer' global handle. I don't understand the latter part. It doesn't change where the information is stored only how we name it (NULL vs. the explicit pointer, it's still the same storage location). -- To view, visit https://review.coreboot.org/c/flashrom/+/67391 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I17460bc2c0aebcbb48c8dfa052b260991525cc49 Gerrit-Change-Number: 67391 Gerrit-PatchSet: 3 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: Peter Marheine <pmarheine(a)chromium.org> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Attention: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Comment-Date: Fri, 09 Sep 2022 13:39:34 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

[S] Change in flashrom[master]: spi: Make 'default_spi_write_aai' the default unless defined
by Felix Singer (Code Review) 09 Sep '22

09 Sep '22

Attention is currently required from: Thomas Heijligen, Edward O'Callaghan, Peter Marheine. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/67479 ) Change subject: spi: Make 'default_spi_write_aai' the default unless defined ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/flashrom/+/67479 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I7f14aaea0edcf0c08cea0e9cd27d58152707fb2a Gerrit-Change-Number: 67479 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Peter Marheine <pmarheine(a)chromium.org> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Thomas Heijligen <src(a)posteo.de> Gerrit-Attention: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Attention: Peter Marheine <pmarheine(a)chromium.org> Gerrit-Comment-Date: Fri, 09 Sep 2022 13:35:13 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

[M] Change in flashrom[master]: drivers/: Make 'internal_delay' the default unless defined
by Angel Pons (Code Review) 09 Sep '22

09 Sep '22

Attention is currently required from: Edward O'Callaghan, Nikolai Artemiev. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/67391 ) Change subject: drivers/: Make 'internal_delay' the default unless defined ...................................................................... Patch Set 3: Code-Review+1 -- To view, visit https://review.coreboot.org/c/flashrom/+/67391 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I17460bc2c0aebcbb48c8dfa052b260991525cc49 Gerrit-Change-Number: 67391 Gerrit-PatchSet: 3 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: Peter Marheine <pmarheine(a)chromium.org> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Attention: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Comment-Date: Fri, 09 Sep 2022 13:27:10 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

[S] Change in flashrom[master]: ichspi: Add Intel Idaville HCC support
by Angel Pons (Code Review) 09 Sep '22

09 Sep '22

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/66635 ) Change subject: ichspi: Add Intel Idaville HCC support ...................................................................... Patch Set 3: (1 comment) Patchset: PS3: > I check the Merge Conflict, there are many updates to the codebase, so I have resubmitted a code com […] Alright. Gerrit associates commits with changes using the Change-Id line in the commit message. If you push an updated commit with the same Change-Id line, it will be treated as an update of the existing change. -- To view, visit https://review.coreboot.org/c/flashrom/+/66635 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I36fe5d296ed65547fbd5130abe1a0c8dd291e920 Gerrit-Change-Number: 66635 Gerrit-PatchSet: 3 Gerrit-Owner: Kevin Yu <ykevin(a)celestica.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 09 Sep 2022 13:25:41 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Kevin Yu <ykevin(a)celestica.com> Gerrit-MessageType: comment

1 0

[S] Change in flashrom[master]: spi: Make 'default_spi_send_multicommand' the default unless defined
by Edward O'Callaghan (Code Review) 09 Sep '22

09 Sep '22

Attention is currently required from: Peter Marheine. Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/67481 ) Change subject: spi: Make 'default_spi_send_multicommand' the default unless defined ...................................................................... spi: Make 'default_spi_send_multicommand' the default unless defined Drop the explicit need to specify the default 'default_spi_send_multicommand' callback function pointer. This is a reasonable default for most driver in the tree with only a few exceptions. This simplifies the code and driver development. Change-Id: I6cc24bf982da3d5251d391eb397db43dd10280e8 Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> --- M bitbang_spi.c M buspirate_spi.c M ch341a_spi.c M dediprog.c M digilent_spi.c M dummyflasher.c M it87spi.c M jlink_spi.c M linux_spi.c M mediatek_i2c_spi.c M mstarddc_spi.c M ni845x_spi.c M parade_lspcon.c M pickit2_spi.c M raiden_debug_spi.c M realtek_mst_i2c_spi.c M sb600spi.c M serprog.c M spi.c M stlinkv3_spi.c M usbblaster_spi.c M wbsio_spi.c 22 files changed, 22 insertions(+), 27 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/81/67481/1 diff --git a/bitbang_spi.c b/bitbang_spi.c index 2823131..6132420 100644 --- a/bitbang_spi.c +++ b/bitbang_spi.c @@ -143,7 +143,6 @@ .max_data_read = MAX_DATA_READ_UNLIMITED, .max_data_write = MAX_DATA_WRITE_UNLIMITED, .command = bitbang_spi_send_command, - .multicommand = default_spi_send_multicommand, .read = default_spi_read, .write_256 = default_spi_write_256, .shutdown = bitbang_spi_shutdown, diff --git a/buspirate_spi.c b/buspirate_spi.c index 6a62ed9..7128ea5 100644 --- a/buspirate_spi.c +++ b/buspirate_spi.c @@ -178,7 +178,6 @@ .max_data_read = MAX_DATA_UNSPECIFIED, .max_data_write = MAX_DATA_UNSPECIFIED, .command = NULL, - .multicommand = default_spi_send_multicommand, .read = default_spi_read, .write_256 = default_spi_write_256, .shutdown = buspirate_spi_shutdown, diff --git a/ch341a_spi.c b/ch341a_spi.c index 54675b3..ee502ec 100644 --- a/ch341a_spi.c +++ b/ch341a_spi.c @@ -413,7 +413,6 @@ .max_data_read = 4 * 1024, .max_data_write = 4 * 1024, .command = ch341a_spi_spi_send_command, - .multicommand = default_spi_send_multicommand, .read = default_spi_read, .write_256 = default_spi_write_256, .shutdown = ch341a_spi_shutdown, diff --git a/dediprog.c b/dediprog.c index f957be6..9611c09 100644 --- a/dediprog.c +++ b/dediprog.c @@ -1034,7 +1034,6 @@ .max_data_read = 16, /* 18 seems to work fine as well, but 19 times out sometimes with FW 5.15. */ .max_data_write = 16, .command = dediprog_spi_send_command, - .multicommand = default_spi_send_multicommand, .read = dediprog_spi_read, .write_256 = dediprog_spi_write_256, .write_aai = dediprog_spi_write_aai, diff --git a/digilent_spi.c b/digilent_spi.c index 12c9ec2..2240892 100644 --- a/digilent_spi.c +++ b/digilent_spi.c @@ -333,7 +333,6 @@ .max_data_read = 252, .max_data_write = 252, .command = digilent_spi_send_command, - .multicommand = default_spi_send_multicommand, .read = default_spi_read, .write_256 = default_spi_write_256, .shutdown = digilent_spi_shutdown, diff --git a/dummyflasher.c b/dummyflasher.c index b52c110..2c34af2 100644 --- a/dummyflasher.c +++ b/dummyflasher.c @@ -924,7 +924,6 @@ .max_data_read = MAX_DATA_READ_UNLIMITED, .max_data_write = MAX_DATA_UNSPECIFIED, .command = dummy_spi_send_command, - .multicommand = default_spi_send_multicommand, .read = default_spi_read, .write_256 = dummy_spi_write_256, .probe_opcode = dummy_spi_probe_opcode, diff --git a/it87spi.c b/it87spi.c index 85da150..ecb9291 100644 --- a/it87spi.c +++ b/it87spi.c @@ -314,7 +314,6 @@ .max_data_read = 3, .max_data_write = MAX_DATA_UNSPECIFIED, .command = it8716f_spi_send_command, - .multicommand = default_spi_send_multicommand, .read = it8716f_spi_chip_read, .write_256 = it8716f_spi_chip_write_256, .write_aai = spi_chip_write_1, diff --git a/jlink_spi.c b/jlink_spi.c index ddc1b6b..0edc78e 100644 --- a/jlink_spi.c +++ b/jlink_spi.c @@ -184,7 +184,6 @@ /* Maximum data write size in one go (excluding opcode+address). */ .max_data_write = JTAG_MAX_TRANSFER_SIZE - 5, .command = jlink_spi_send_command, - .multicommand = default_spi_send_multicommand, .read = default_spi_read, .write_256 = default_spi_write_256, .features = SPI_MASTER_4BA, diff --git a/linux_spi.c b/linux_spi.c index 9e29007..3237574 100644 --- a/linux_spi.c +++ b/linux_spi.c @@ -116,7 +116,6 @@ .max_data_read = MAX_DATA_UNSPECIFIED, /* TODO? */ .max_data_write = MAX_DATA_UNSPECIFIED, /* TODO? */ .command = linux_spi_send_command, - .multicommand = default_spi_send_multicommand, .read = linux_spi_read, .write_256 = linux_spi_write_256, .shutdown = linux_spi_shutdown, diff --git a/mediatek_i2c_spi.c b/mediatek_i2c_spi.c index f0f700b..f39cca9 100644 --- a/mediatek_i2c_spi.c +++ b/mediatek_i2c_spi.c @@ -456,7 +456,6 @@ // Leave room for 1-byte command and up to a 4-byte address. .max_data_write = I2C_SMBUS_BLOCK_MAX - 5, .command = mediatek_send_command, - .multicommand = default_spi_send_multicommand, .read = default_spi_read, .write_256 = default_spi_write_256, .shutdown = mediatek_shutdown, diff --git a/mstarddc_spi.c b/mstarddc_spi.c index 206aa73..eb45f9f 100644 --- a/mstarddc_spi.c +++ b/mstarddc_spi.c @@ -142,7 +142,6 @@ .max_data_read = 256, .max_data_write = 256, .command = mstarddc_spi_send_command, - .multicommand = default_spi_send_multicommand, .read = default_spi_read, .write_256 = default_spi_write_256, .shutdown = mstarddc_spi_shutdown, diff --git a/ni845x_spi.c b/ni845x_spi.c index e4933b4..39f5af5 100644 --- a/ni845x_spi.c +++ b/ni845x_spi.c @@ -532,7 +532,6 @@ .max_data_read = MAX_DATA_READ_UNLIMITED, .max_data_write = MAX_DATA_WRITE_UNLIMITED, .command = ni845x_spi_transmit, - .multicommand = default_spi_send_multicommand, .read = default_spi_read, .write_256 = default_spi_write_256, .shutdown = ni845x_spi_shutdown, diff --git a/parade_lspcon.c b/parade_lspcon.c index 761e46b..9e5ef1a 100644 --- a/parade_lspcon.c +++ b/parade_lspcon.c @@ -432,7 +432,6 @@ .max_data_read = 16, .max_data_write = 12, .command = parade_lspcon_send_command, - .multicommand = default_spi_send_multicommand, .read = parade_lspcon_read, .write_256 = parade_lspcon_write_256, .write_aai = parade_lspcon_write_aai, diff --git a/pickit2_spi.c b/pickit2_spi.c index 0c63880..7603bda 100644 --- a/pickit2_spi.c +++ b/pickit2_spi.c @@ -380,7 +380,6 @@ .max_data_read = 40, .max_data_write = 40, .command = pickit2_spi_send_command, - .multicommand = default_spi_send_multicommand, .read = default_spi_read, .write_256 = default_spi_write_256, .shutdown = pickit2_shutdown, diff --git a/raiden_debug_spi.c b/raiden_debug_spi.c index 01c61f9..44690d0 100644 --- a/raiden_debug_spi.c +++ b/raiden_debug_spi.c @@ -1316,7 +1316,6 @@ .max_data_read = 0, .max_data_write = 0, .command = NULL, - .multicommand = default_spi_send_multicommand, .read = default_spi_read, .write_256 = default_spi_write_256, .shutdown = raiden_debug_spi_shutdown, diff --git a/realtek_mst_i2c_spi.c b/realtek_mst_i2c_spi.c index 74458c8..1c4f4c0 100644 --- a/realtek_mst_i2c_spi.c +++ b/realtek_mst_i2c_spi.c @@ -436,7 +436,6 @@ .max_data_read = 16, .max_data_write = 8, .command = realtek_mst_i2c_spi_send_command, - .multicommand = default_spi_send_multicommand, .read = realtek_mst_i2c_spi_read, .write_256 = realtek_mst_i2c_spi_write_256, .write_aai = realtek_mst_i2c_spi_write_aai, diff --git a/sb600spi.c b/sb600spi.c index dab240c..b79bb51 100644 --- a/sb600spi.c +++ b/sb600spi.c @@ -599,7 +599,6 @@ .max_data_read = FIFO_SIZE_OLD, .max_data_write = FIFO_SIZE_OLD - 3, .command = sb600_spi_send_command, - .multicommand = default_spi_send_multicommand, .read = default_spi_read, .write_256 = default_spi_write_256, .shutdown = sb600spi_shutdown, @@ -610,7 +609,6 @@ .max_data_read = FIFO_SIZE_YANGTZE - 3, /* Apparently the big SPI 100 buffer is not a ring buffer. */ .max_data_write = FIFO_SIZE_YANGTZE - 3, .command = spi100_spi_send_command, - .multicommand = default_spi_send_multicommand, .read = default_spi_read, .write_256 = default_spi_write_256, .shutdown = sb600spi_shutdown, @@ -621,7 +619,6 @@ .max_data_read = MAX_DATA_READ_UNLIMITED, .max_data_write = FIFO_SIZE_YANGTZE - 3, .command = spi100_spi_send_command, - .multicommand = default_spi_send_multicommand, .read = promontory_read_memmapped, .write_256 = default_spi_write_256, .shutdown = sb600spi_shutdown, diff --git a/serprog.c b/serprog.c index c6932e8..88dbc69 100644 --- a/serprog.c +++ b/serprog.c @@ -443,7 +443,6 @@ .max_data_read = MAX_DATA_READ_UNLIMITED, .max_data_write = MAX_DATA_WRITE_UNLIMITED, .command = serprog_spi_send_command, - .multicommand = default_spi_send_multicommand, .read = default_spi_read, .write_256 = default_spi_write_256, .probe_opcode = default_spi_probe_opcode, diff --git a/spi.c b/spi.c index 9d768a4..7b56ab0 100644 --- a/spi.c +++ b/spi.c @@ -37,7 +37,9 @@ int spi_send_multicommand(const struct flashctx *flash, struct spi_command *cmds) { - return flash->mst->spi.multicommand(flash, cmds); + if (flash->mst->spi.multicommand) + return flash->mst->spi.multicommand(flash, cmds); + return default_spi_send_multicommand(flash, cmds); } int default_spi_send_command(const struct flashctx *flash, unsigned int writecnt, @@ -153,10 +155,9 @@ } } - if (!mst->write_256 || !mst->read || - !mst->multicommand || !mst->probe_opcode || + if (!mst->write_256 || !mst->read || !mst->probe_opcode || ((mst->command == default_spi_send_command || !mst->command) && - (mst->multicommand == default_spi_send_multicommand))) { + (mst->multicommand == default_spi_send_multicommand || !mst->multicommand))) { msg_perr("%s called with incomplete master definition. " "Please report a bug at flashrom(a)flashrom.org\n", __func__); diff --git a/stlinkv3_spi.c b/stlinkv3_spi.c index b2da2fe..e3e6b75 100644 --- a/stlinkv3_spi.c +++ b/stlinkv3_spi.c @@ -466,7 +466,6 @@ .max_data_read = UINT16_MAX, .max_data_write = UINT16_MAX, .command = stlinkv3_spi_transmit, - .multicommand = default_spi_send_multicommand, .read = default_spi_read, .write_256 = default_spi_write_256, .shutdown = stlinkv3_spi_shutdown, diff --git a/usbblaster_spi.c b/usbblaster_spi.c index 67279c9..4c9bc40 100644 --- a/usbblaster_spi.c +++ b/usbblaster_spi.c @@ -168,7 +168,6 @@ .max_data_read = 256, .max_data_write = 256, .command = usbblaster_spi_send_command, - .multicommand = default_spi_send_multicommand, .read = default_spi_read, .write_256 = default_spi_write_256, .shutdown = usbblaster_shutdown, diff --git a/wbsio_spi.c b/wbsio_spi.c index 95ca1e9..ee34e30 100644 --- a/wbsio_spi.c +++ b/wbsio_spi.c @@ -186,7 +186,6 @@ .max_data_read = MAX_DATA_UNSPECIFIED, .max_data_write = MAX_DATA_UNSPECIFIED, .command = wbsio_spi_send_command, - .multicommand = default_spi_send_multicommand, .read = wbsio_spi_read, .write_256 = spi_chip_write_1, .write_aai = spi_chip_write_1, -- To view, visit https://review.coreboot.org/c/flashrom/+/67481 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I6cc24bf982da3d5251d391eb397db43dd10280e8 Gerrit-Change-Number: 67481 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Peter Marheine <pmarheine(a)chromium.org> Gerrit-Attention: Peter Marheine <pmarheine(a)chromium.org> Gerrit-MessageType: newchange

1 0

2025

2024

2023

2022

2021

2020

2019

2018

2017

flashrom-gerrit September 2022