May 2022 - flashrom-gerrit - mail.coreboot.org

Change in flashrom[master]: dummyflasher: Wire variable size feature via opaque infra
by Anastasia Klimchuk (Code Review) 25 May '22

25 May '22

Attention is currently required from: Thomas Heijligen, Edward O'Callaghan, Angel Pons, Anastasia Klimchuk, Nikolai Artemiev. Hello build bot (Jenkins), Thomas Heijligen, Edward O'Callaghan, Nikolai Artemiev, Peter Marheine, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/flashrom/+/64488 to look at the new patch set (#3). Change subject: dummyflasher: Wire variable size feature via opaque infra ...................................................................... dummyflasher: Wire variable size feature via opaque infra Wire "variable size" feature in dummy programmer via opaque infra. This patch fixes the broken build with CONFIG_DUMMY=no. Dummyflasher registers opaque master for the case when it is initialised with EMULATE_VARIABLE_SIZE. Dummy opaque master emulates read/write/erase as simple memory operations over `data->flashchip_contents`. Fixes: https://ticket.coreboot.org/issues/365 TEST=the following scenarious run successfully Testing build $ make clean && make CONFIG_DUMMY=no $ flashrom -h : dummy is not in the list $ make clean && make CONFIG_EVERYTHING=yes $ flashrom -h : dummy is in the list Testing "variable size" feature $ flashrom -p dummy:size=8388608,emulate=VARIABLE_SIZE -V $ flashrom -p dummy:size=8388608,emulate=VARIABLE_SIZE -r /tmp/dump.bin -V $ head -c 8388608 </dev/urandom >/tmp/image.bin $ flashrom -p dummy:image=/tmp/image.bin,size=8388608,emulate=VARIABLE_SIZE -w /tmp/dump.bin -V Testing standard flow $ flashrom -p dummy:emulate=W25Q128FV -V $ flashrom -p dummy:emulate=W25Q128FV -r /tmp/dump.bin -V $ head -c 16777216 </dev/urandom >/tmp/image.bin $ flashrom -p dummy:image=/tmp/image.bin,emulate=W25Q128FV -w /tmp/dump.bin -V Change-Id: I76402bfdf8b1a75489e4509fec92c9a777d0cf58 Signed-off-by: Anastasia Klimchuk <aklm(a)chromium.org> --- M dummyflasher.c M flashchips.c M include/chipdrivers.h 3 files changed, 77 insertions(+), 73 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/88/64488/3 -- To view, visit https://review.coreboot.org/c/flashrom/+/64488 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I76402bfdf8b1a75489e4509fec92c9a777d0cf58 Gerrit-Change-Number: 64488 Gerrit-PatchSet: 3 Gerrit-Owner: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: Peter Marheine <pmarheine(a)chromium.org> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: Namyoon Woo <namyoon(a)google.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Thomas Heijligen <src(a)posteo.de> Gerrit-Attention: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Attention: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-MessageType: newpatchset

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Change in flashrom[master]: flashchips: Add missing block eraser for S25FL512S
by Edward O'Callaghan (Code Review) 25 May '22

25 May '22

Attention is currently required from: Nico Huber, Angel Pons. Edward O'Callaghan has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/64637 ) Change subject: flashchips: Add missing block eraser for S25FL512S ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/flashrom/+/64637 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I8708294d42f5da80c0ca07ccdae627f13fd5c645 Gerrit-Change-Number: 64637 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Tue, 24 May 2022 23:54:03 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in flashrom[master]: flashchips.c: add CMP bit entry to W25Q256.V
by Edward O'Callaghan (Code Review) 25 May '22

25 May '22

Attention is currently required from: Nikolai Artemiev, Anastasia Klimchuk. Edward O'Callaghan has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/64607 ) Change subject: flashchips.c: add CMP bit entry to W25Q256.V ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/flashrom/+/64607 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I1cb400f6b8542a9054875b8f2557db1cc06292e2 Gerrit-Change-Number: 64607 Gerrit-PatchSet: 2 Gerrit-Owner: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Attention: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Comment-Date: Tue, 24 May 2022 23:49:23 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in flashrom[master]: meson: use files() for srcs list
by Edward O'Callaghan (Code Review) 25 May '22

25 May '22

Attention is currently required from: Thomas Heijligen. Edward O'Callaghan has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/64384 ) Change subject: meson: use files() for srcs list ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/flashrom/+/64384/comment/10519b5a_2623fbe9 PS1, Line 8: > Meson looks up if the file xyz.c exists when calling file("xyz.c"). […] Sorry I was too brief; yes please include the first part in the commit message that is all. -- To view, visit https://review.coreboot.org/c/flashrom/+/64384 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I346b5468b4203f1521ec73a90f93ff3b13ebf43c Gerrit-Change-Number: 64384 Gerrit-PatchSet: 1 Gerrit-Owner: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Thomas Heijligen <src(a)posteo.de> Gerrit-Comment-Date: Tue, 24 May 2022 23:46:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Thomas Heijligen <src(a)posteo.de> Comment-In-Reply-To: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: comment

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Change in flashrom[master]: spi25_statusreg.c: Allow opaque masters to hook spi_{rw}_register()
by Edward O'Callaghan (Code Review) 25 May '22

25 May '22

Attention is currently required from: Anastasia Klimchuk, Nikolai Artemiev, Sergii Dmytruk. Edward O'Callaghan has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/64375 ) Change subject: spi25_statusreg.c: Allow opaque masters to hook spi_{rw}_register() ...................................................................... Patch Set 4: (1 comment) File spi25_statusreg.c: https://review.coreboot.org/c/flashrom/+/64375/comment/df68aca4_bbd605a6 PS3, Line 35: } > Well, it says "Do not unnecessarily use braces where a single statement will do.". […] I think once we get clang-format decided on we can just make this sort of thing automatic and make the whole code-base consistent. This sort of thing comes up from time to time in code review unnecessarily due to lack of tooling usage. -- To view, visit https://review.coreboot.org/c/flashrom/+/64375 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I3ab0d7f5f48338c8ecb118a69651c203fbc516ac Gerrit-Change-Number: 64375 Gerrit-PatchSet: 4 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Attention: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Attention: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Comment-Date: Tue, 24 May 2022 23:43:07 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Edward O'Callaghan <quasisec(a)chromium.org> Comment-In-Reply-To: Anastasia Klimchuk <aklm(a)chromium.org> Comment-In-Reply-To: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-MessageType: comment

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Change in flashrom[master]: flashchips.c: Fix 4BA for S25FL512S
by Nico Huber (Code Review) 24 May '22

24 May '22

Attention is currently required from: Angel Pons. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/64425 ) Change subject: flashchips.c: Fix 4BA for S25FL512S ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/flashrom/+/64425/comment/2fd2e31d_42b18674 PS1, Line 12: so select them through `FEATURE_4BA_EAR7`. As it is not known how this > It looks like they use different opcodes, though (16/17 instead of […] Turned out we actually supported different opcodes already with the `.wrea_override` field. As it's hard to understand, I dropped it in CB:64636 and replaced it with a proper feature flag. If my commit chain lands, I guess this change here becomes obsolete. -- To view, visit https://review.coreboot.org/c/flashrom/+/64425 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I08c5a70351d945130183fe01c328dc4d30cfe0ef Gerrit-Change-Number: 64425 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Tue, 24 May 2022 13:49:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: comment

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Change in flashrom[master]: flashchips,spi25: Replace `.wrea_override` with FEATURE_4BA_EAR_1716
by Nico Huber (Code Review) 24 May '22

24 May '22

Attention is currently required from: Angel Pons. Hello Angel Pons, I'd like you to do a code review. Please visit https://review.coreboot.org/c/flashrom/+/64636 to review the following change. Change subject: flashchips,spi25: Replace `.wrea_override` with FEATURE_4BA_EAR_1716 ...................................................................... flashchips,spi25: Replace `.wrea_override` with FEATURE_4BA_EAR_1716 There are two competing sets of instructions to access the extended address register of 4BA SPI chips. Some chips even support both sets. So far, we assumed the 0xc5/0xc8 instructions by default and allowed to override the write instructions with the `.wrea_override` field. This has some disadvantages: * The additional field is easily overlooked. So when adding a new flash chip, one might assume only 0xc5/0xc8 are supported. * We cannot describe flash chips completely that allow both instructions (and some programmers may be picky about which instructions can be used). Therefore, replace the `.wrea_override` field with a feature flag, and set it for chips known to support it (Spansion and ISSI). The S25FL512S did not advertise EAR support at all, so we set it to TEST_UNTESTED again. Signed-off-by: Nico Huber <nico.h(a)gmx.de> Change-Id: I6d82f24898acd0789203516a7456fd785907bc10 Ticket: https://ticket.coreboot.org/issues/357 --- M dediprog.c M flashchips.c M include/flash.h M include/spi.h M spi25.c 5 files changed, 28 insertions(+), 15 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/36/64636/1 diff --git a/dediprog.c b/dediprog.c index 91a1632..9775fde 100644 --- a/dediprog.c +++ b/dediprog.c @@ -416,7 +416,7 @@ } } } else { - if (flash->chip->feature_bits & FEATURE_4BA_EAR_C5C8) { + if (flash->chip->feature_bits & FEATURE_4BA_EAR_ANY) { if (spi_set_extended_address(flash, start >> 24)) return 1; } else if (start >> 24) { diff --git a/flashchips.c b/flashchips.c index d8208fe..cc80159 100644 --- a/flashchips.c +++ b/flashchips.c @@ -7469,7 +7469,8 @@ .page_size = 256, /* supports SFDP */ /* OTP: 1024B total; read 0x68; write 0x62, erase 0x64, read ID 0x4B */ - .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_4BA | FEATURE_4BA_ENTER_EAR7, + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | + FEATURE_4BA | FEATURE_4BA_ENTER_EAR7 | FEATURE_4BA_EAR_1716, .tested = TEST_OK_PREW, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, @@ -7644,7 +7645,8 @@ .page_size = 256, /* supports SFDP */ /* OTP: 1024B total; read 0x68; write 0x62, erase 0x64, read ID 0x4B */ - .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_4BA | FEATURE_4BA_ENTER_EAR7, + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | + FEATURE_4BA | FEATURE_4BA_ENTER_EAR7 | FEATURE_4BA_EAR_1716, .tested = TEST_OK_PREW, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, @@ -16672,7 +16674,8 @@ .total_size = 32768, .page_size = 256, /* OTP: 1024B total, 32B reserved; read 0x4B; write 0x42 */ - .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_4BA_EAR7, + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | + FEATURE_4BA_NATIVE | FEATURE_4BA_ENTER_EAR7 | FEATURE_4BA_EAR_1716, .tested = TEST_OK_PREW, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, @@ -16706,7 +16709,6 @@ .write = spi_chip_write_256, /* Multi I/O supported */ .read = spi_chip_read, /* Fast read (0x0B) and multi I/O supported */ .voltage = {2700, 3600}, - .wrea_override = 0x17, }, { @@ -16718,8 +16720,9 @@ .total_size = 65536, /* 512 Mb (=> 64 MB)) */ .page_size = 256, /* OTP: 1024B total, 32B reserved; read 0x4B; write 0x42 */ - .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_4BA_NATIVE, - .tested = TEST_OK_PREW, + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | + FEATURE_4BA_NATIVE | FEATURE_4BA_ENTER_EAR7 | FEATURE_4BA_EAR_1716, + .tested = TEST_UNTESTED, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, .block_erasers = diff --git a/include/flash.h b/include/flash.h index 162c0ac..8203295 100644 --- a/include/flash.h +++ b/include/flash.h @@ -127,10 +127,12 @@ #define FEATURE_4BA_EAR_C5C8 (1 << 13) /**< Regular 3-byte operations can be used by writing the most significant address byte into an extended address register (using 0xc5/0xc8 instructions). */ -#define FEATURE_4BA_READ (1 << 14) /**< Native 4BA read instruction (0x13) is supported. */ -#define FEATURE_4BA_FAST_READ (1 << 15) /**< Native 4BA fast read instruction (0x0c) is supported. */ -#define FEATURE_4BA_WRITE (1 << 16) /**< Native 4BA byte program (0x12) is supported. */ +#define FEATURE_4BA_EAR_1716 (1 << 14) /**< Like FEATURE_4BA_EAR_C5C8 but with 0x17/0x16 instructions. */ +#define FEATURE_4BA_READ (1 << 15) /**< Native 4BA read instruction (0x13) is supported. */ +#define FEATURE_4BA_FAST_READ (1 << 16) /**< Native 4BA fast read instruction (0x0c) is supported. */ +#define FEATURE_4BA_WRITE (1 << 17) /**< Native 4BA byte program (0x12) is supported. */ /* 4BA Shorthands */ +#define FEATURE_4BA_EAR_ANY (FEATURE_4BA_EAR_C5C8 | FEATURE_4BA_EAR_1716) #define FEATURE_4BA_NATIVE (FEATURE_4BA_READ | FEATURE_4BA_FAST_READ | FEATURE_4BA_WRITE) #define FEATURE_4BA (FEATURE_4BA_ENTER | FEATURE_4BA_EAR_C5C8 | FEATURE_4BA_NATIVE) #define FEATURE_4BA_WREN (FEATURE_4BA_ENTER_WREN | FEATURE_4BA_EAR_C5C8 | FEATURE_4BA_NATIVE) @@ -273,9 +275,6 @@ } voltage; enum write_granularity gran; - /* SPI specific options (TODO: Make it a union in case other bustypes get specific options.) */ - uint8_t wrea_override; /**< override opcode for write extended address register */ - struct reg_bit_map { /* Status register protection bit (SRP) */ struct reg_bit_info srp; diff --git a/include/spi.h b/include/spi.h index 14f71aa..ef331db 100644 --- a/include/spi.h +++ b/include/spi.h @@ -176,9 +176,11 @@ /* Write Extended Address Register */ #define JEDEC_WRITE_EXT_ADDR_REG 0xC5 +#define ALT_WRITE_EXT_ADDR_REG_17 0x17 /* Read Extended Address Register */ #define JEDEC_READ_EXT_ADDR_REG 0xC8 +#define ALT_READ_EXT_ADDR_REG_16 0x16 /* Read the memory */ #define JEDEC_READ 0x03 diff --git a/spi25.c b/spi25.c index f6900a9..ad218fa 100644 --- a/spi25.c +++ b/spi25.c @@ -351,7 +351,16 @@ static int spi_write_extended_address_register(struct flashctx *const flash, const uint8_t regdata) { - const uint8_t op = flash->chip->wrea_override ? : JEDEC_WRITE_EXT_ADDR_REG; + uint8_t op; + if (flash->chip->feature_bits & FEATURE_4BA_EAR_C5C8) { + op = JEDEC_WRITE_EXT_ADDR_REG; + } else if (flash->chip->feature_bits & FEATURE_4BA_EAR_1716) { + op = ALT_WRITE_EXT_ADDR_REG_17; + } else { + msg_cerr("Flash misses feature flag for extended-address register.\n"); + return -1; + } + struct spi_command cmds[] = { { .readarr = 0, @@ -394,7 +403,7 @@ cmd_buf[4] = (addr >> 0) & 0xff; return 4; } else { - if (flash->chip->feature_bits & FEATURE_4BA_EAR_C5C8) { + if (flash->chip->feature_bits & FEATURE_4BA_EAR_ANY) { if (spi_set_extended_address(flash, addr >> 24)) return -1; } else if (addr >> 24) { -- To view, visit https://review.coreboot.org/c/flashrom/+/64636 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I6d82f24898acd0789203516a7456fd785907bc10 Gerrit-Change-Number: 64636 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in flashrom[master]: flashchips: Add missing block eraser for S25FL512S
by Nico Huber (Code Review) 24 May '22

24 May '22

Attention is currently required from: Angel Pons. Hello Angel Pons, I'd like you to do a code review. Please visit https://review.coreboot.org/c/flashrom/+/64637 to review the following change. Change subject: flashchips: Add missing block eraser for S25FL512S ...................................................................... flashchips: Add missing block eraser for S25FL512S Now that we can make use of the extended-address register, we can also advertise the `d8` eraser that can take 3- or 4-byte addresses. Signed-off-by: Nico Huber <nico.h(a)gmx.de> Ticket: https://ticket.coreboot.org/issues/357 Change-Id: I8708294d42f5da80c0ca07ccdae627f13fd5c645 --- M flashchips.c 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/37/64637/1 diff --git a/flashchips.c b/flashchips.c index cc80159..46a6017 100644 --- a/flashchips.c +++ b/flashchips.c @@ -16731,6 +16731,9 @@ .eraseblocks = { { 256 * 1024, 256} }, .block_erase = spi_block_erase_dc, }, { + .eraseblocks = { { 256 * 1024, 256} }, + .block_erase = spi_block_erase_d8, + }, { .eraseblocks = { { 65536 * 1024, 1} }, .block_erase = spi_block_erase_60, }, { -- To view, visit https://review.coreboot.org/c/flashrom/+/64637 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I8708294d42f5da80c0ca07ccdae627f13fd5c645 Gerrit-Change-Number: 64637 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in flashrom[master]: flashchips: Rename FEATURE_4BA_EXT_ADDR -> _EAR_C5C8
by Nico Huber (Code Review) 24 May '22

24 May '22

Attention is currently required from: Angel Pons. Hello Angel Pons, I'd like you to do a code review. Please visit https://review.coreboot.org/c/flashrom/+/64635 to review the following change. Change subject: flashchips: Rename FEATURE_4BA_EXT_ADDR -> _EAR_C5C8 ...................................................................... flashchips: Rename FEATURE_4BA_EXT_ADDR -> _EAR_C5C8 There are two competing sets of instructions to access the extended address register of 4BA SPI chips. Some chips even support both sets. To prepare for other instructions than the default 0xc5/0xc8, rename the original feature flag. Signed-off-by: Nico Huber <nico.h(a)gmx.de> Change-Id: Iacb7b68a9e3444fe28873ff0fe5e3fab16643c8c Ticket: https://ticket.coreboot.org/issues/357 --- M dediprog.c M flashchips.c M include/flash.h M spi25.c 4 files changed, 11 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/35/64635/1 diff --git a/dediprog.c b/dediprog.c index 8a05a7c..91a1632 100644 --- a/dediprog.c +++ b/dediprog.c @@ -416,7 +416,7 @@ } } } else { - if (flash->chip->feature_bits & FEATURE_4BA_EXT_ADDR) { + if (flash->chip->feature_bits & FEATURE_4BA_EAR_C5C8) { if (spi_set_extended_address(flash, start >> 24)) return 1; } else if (start >> 24) { diff --git a/flashchips.c b/flashchips.c index ece5c71..d8208fe 100644 --- a/flashchips.c +++ b/flashchips.c @@ -17496,7 +17496,7 @@ /* supports SFDP */ /* OTP: 1024B total, 256B reserved; read 0x48; write 0x42, erase 0x44, read ID 0x4B */ .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_4BA_ENTER_WREN | - FEATURE_4BA_EXT_ADDR | FEATURE_4BA_READ | FEATURE_4BA_FAST_READ | + FEATURE_4BA_EAR_C5C8 | FEATURE_4BA_READ | FEATURE_4BA_FAST_READ | FEATURE_WRSR2, .tested = TEST_OK_PREW, .probe = probe_spi_rdid, @@ -19632,7 +19632,7 @@ /* supports SFDP */ /* OTP: 1024B total, 256B reserved; read 0x48; write 0x42, erase 0x44, read ID 0x4B */ .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_4BA_ENTER_WREN | - FEATURE_4BA_EXT_ADDR | FEATURE_4BA_READ | FEATURE_4BA_FAST_READ | + FEATURE_4BA_EAR_C5C8 | FEATURE_4BA_READ | FEATURE_4BA_FAST_READ | FEATURE_WRSR2, .tested = TEST_UNTESTED, .probe = probe_spi_rdid, @@ -19682,7 +19682,7 @@ /* supports SFDP */ /* OTP: 1024B total, 256B reserved; read 0x48; write 0x42, erase 0x44, read ID 0x4B */ .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_4BA_ENTER_WREN - | FEATURE_4BA_EXT_ADDR | FEATURE_4BA_READ | FEATURE_4BA_FAST_READ, + | FEATURE_4BA_EAR_C5C8 | FEATURE_4BA_READ | FEATURE_4BA_FAST_READ, .tested = TEST_UNTESTED, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, diff --git a/include/flash.h b/include/flash.h index 27ade09..162c0ac 100644 --- a/include/flash.h +++ b/include/flash.h @@ -124,16 +124,17 @@ #define FEATURE_4BA_ENTER (1 << 10) /**< Can enter/exit 4BA mode with instructions 0xb7/0xe9 w/o WREN */ #define FEATURE_4BA_ENTER_WREN (1 << 11) /**< Can enter/exit 4BA mode with instructions 0xb7/0xe9 after WREN */ #define FEATURE_4BA_ENTER_EAR7 (1 << 12) /**< Can enter/exit 4BA mode by setting bit7 of the ext addr reg */ -#define FEATURE_4BA_EXT_ADDR (1 << 13) /**< Regular 3-byte operations can be used by writing the most - significant address byte into an extended address register. */ +#define FEATURE_4BA_EAR_C5C8 (1 << 13) /**< Regular 3-byte operations can be used by writing the most + significant address byte into an extended address register + (using 0xc5/0xc8 instructions). */ #define FEATURE_4BA_READ (1 << 14) /**< Native 4BA read instruction (0x13) is supported. */ #define FEATURE_4BA_FAST_READ (1 << 15) /**< Native 4BA fast read instruction (0x0c) is supported. */ #define FEATURE_4BA_WRITE (1 << 16) /**< Native 4BA byte program (0x12) is supported. */ /* 4BA Shorthands */ #define FEATURE_4BA_NATIVE (FEATURE_4BA_READ | FEATURE_4BA_FAST_READ | FEATURE_4BA_WRITE) -#define FEATURE_4BA (FEATURE_4BA_ENTER | FEATURE_4BA_EXT_ADDR | FEATURE_4BA_NATIVE) -#define FEATURE_4BA_WREN (FEATURE_4BA_ENTER_WREN | FEATURE_4BA_EXT_ADDR | FEATURE_4BA_NATIVE) -#define FEATURE_4BA_EAR7 (FEATURE_4BA_ENTER_EAR7 | FEATURE_4BA_EXT_ADDR | FEATURE_4BA_NATIVE) +#define FEATURE_4BA (FEATURE_4BA_ENTER | FEATURE_4BA_EAR_C5C8 | FEATURE_4BA_NATIVE) +#define FEATURE_4BA_WREN (FEATURE_4BA_ENTER_WREN | FEATURE_4BA_EAR_C5C8 | FEATURE_4BA_NATIVE) +#define FEATURE_4BA_EAR7 (FEATURE_4BA_ENTER_EAR7 | FEATURE_4BA_EAR_C5C8 | FEATURE_4BA_NATIVE) /* * Most flash chips are erased to ones and programmed to zeros. However, some * other flash chips, such as the ENE KB9012 internal flash, work the opposite way. diff --git a/spi25.c b/spi25.c index e96a38d..f6900a9 100644 --- a/spi25.c +++ b/spi25.c @@ -394,7 +394,7 @@ cmd_buf[4] = (addr >> 0) & 0xff; return 4; } else { - if (flash->chip->feature_bits & FEATURE_4BA_EXT_ADDR) { + if (flash->chip->feature_bits & FEATURE_4BA_EAR_C5C8) { if (spi_set_extended_address(flash, addr >> 24)) return -1; } else if (addr >> 24) { -- To view, visit https://review.coreboot.org/c/flashrom/+/64635 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Iacb7b68a9e3444fe28873ff0fe5e3fab16643c8c Gerrit-Change-Number: 64635 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in flashrom[master]: flashchips: Split W25Q256.V
by Nico Huber (Code Review) 24 May '22

24 May '22

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/64599 ) Change subject: flashchips: Split W25Q256.V ...................................................................... Patch Set 4: (1 comment) File flashchips.c: https://review.coreboot.org/c/flashrom/+/64599/comment/2023293a_a6175529 PS2, Line 17551: _WREN > Write enable looks spurious especially because it shares a datasheet with […] Done -- To view, visit https://review.coreboot.org/c/flashrom/+/64599 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I1a68121ff40d2b1769632d8e5151c2cd972c23ef Gerrit-Change-Number: 64599 Gerrit-PatchSet: 4 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Tue, 24 May 2022 13:20:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: comment

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