April 2022 - flashrom-gerrit - mail.coreboot.org

Change in flashrom[master]: flashrom.c: remove unused include
by Angel Pons (Code Review) 07 Apr '22

07 Apr '22

Attention is currently required from: Nico Huber, Thomas Heijligen. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/63412 ) Change subject: flashrom.c: remove unused include ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/flashrom/+/63412 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I09b3233a128582bc98c5af77b6c89bd49984800e Gerrit-Change-Number: 63412 Gerrit-PatchSet: 1 Gerrit-Owner: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Thomas Heijligen <src(a)posteo.de> Gerrit-Comment-Date: Thu, 07 Apr 2022 16:03:48 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in flashrom[master]: hwaccess_physmap: add missing DirectHW include
by Angel Pons (Code Review) 07 Apr '22

07 Apr '22

Attention is currently required from: Felix Singer, Nico Huber, Thomas Heijligen, Stefan Reinauer. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/62929 ) Change subject: hwaccess_physmap: add missing DirectHW include ...................................................................... Patch Set 1: Code-Review+2 (1 comment) Commit Message: https://review.coreboot.org/c/flashrom/+/62929/comment/13c05607_b19d9bef PS1, Line 13: misses missing -- To view, visit https://review.coreboot.org/c/flashrom/+/62929 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I0e0f3fd587ae46e6f73418f2c83641cb1202478c Gerrit-Change-Number: 62929 Gerrit-PatchSet: 1 Gerrit-Owner: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Thomas Heijligen <src(a)posteo.de> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Comment-Date: Thu, 07 Apr 2022 16:03:20 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in flashrom[master]: ichspi: Add `PCH100_` prefix for `Write Enable Type (WET)` macros
by Subrata Banik (Code Review) 07 Apr '22

07 Apr '22

Attention is currently required from: Subrata Banik, Nico Huber, Angel Pons. Hello build bot (Jenkins), Nico Huber, Edward O'Callaghan, Angel Pons, Anastasia Klimchuk, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/flashrom/+/62888 to look at the new patch set (#9). Change subject: ichspi: Add `PCH100_` prefix for `Write Enable Type (WET)` macros ...................................................................... ichspi: Add `PCH100_` prefix for `Write Enable Type (WET)` macros This patch renames the `WET` macro definitions based on its availability with PCH100 onwards chipset. HSFC_WET_OFF -> PCH100_HSFC_WET_OFF HSFC_WET -> PCH100_HSFC_WET BUG=b:223630977 TEST=Able to perform read/write/erase operation on PCH 600 series chipset (board name: Brya). Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: Id32cb4ccb83dd08e9b0b1ab30cc8e041dd059f5f --- M ichspi.c 1 file changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/88/62888/9 -- To view, visit https://review.coreboot.org/c/flashrom/+/62888 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Id32cb4ccb83dd08e9b0b1ab30cc8e041dd059f5f Gerrit-Change-Number: 62888 Gerrit-PatchSet: 9 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Subrata Banik <subi.banik(a)gmail.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newpatchset

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Change in flashrom[master]: Drop STANDALONE mode
by Thomas Heijligen (Code Review) 07 Apr '22

07 Apr '22

Thomas Heijligen has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/63469 ) Change subject: Drop STANDALONE mode ...................................................................... Drop STANDALONE mode STANDALONE mode was used to build flashrom without having support for file handling. This was relevant to build libflashrom on top of libpayload. For a while now, the code which is covered by STANDALONE has moved to cli_*.c and is not used for libflashrom. Therefor we can drop STANDALONE mode. Change-Id: I58fb82270a9884a323d9850176708d230fdc5165 Signed-off-by: Thomas Heijligen <thomas.heijligen(a)secunet.com> --- M Makefile M cli_classic.c M cli_output.c M flash.h M tests/meson.build 5 files changed, 2 insertions(+), 23 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/69/63469/1 diff --git a/Makefile b/Makefile index 9a59538..1c05a1d 100644 --- a/Makefile +++ b/Makefile @@ -290,7 +290,6 @@ .DEFAULT_GOAL := libflashrom.a $(info Setting default goal to libflashrom.a) endif -FLASHROM_CFLAGS += -DSTANDALONE $(call mark_unsupported,CONFIG_DUMMY) # libpayload does not provide the romsize field in struct pci_dev that the atapromise code requires. $(call mark_unsupported,CONFIG_ATAPROMISE) diff --git a/cli_classic.c b/cli_classic.c index 0b6e79c..c543ff7 100644 --- a/cli_classic.c +++ b/cli_classic.c @@ -112,12 +112,10 @@ /* Ensure a file is open by means of fstat */ static bool check_file(FILE *file) { -#ifndef STANDALONE struct stat statbuf; if (fstat(fileno(file), &statbuf) < 0) return false; -#endif /* !STANDALONE */ return true; } @@ -279,9 +277,7 @@ char *referencefile = NULL; char *layoutfile = NULL; char *fmapfile = NULL; -#ifndef STANDALONE char *logfile = NULL; -#endif /* !STANDALONE */ char *tempstr = NULL; char *pparam = NULL; struct layout_include_args *include_args = NULL; @@ -481,9 +477,6 @@ exit(0); break; case 'o': -#ifdef STANDALONE - cli_classic_abort_usage("Log file not supported in standalone mode. Aborting.\n"); -#else /* STANDALONE */ if (logfile) { fprintf(stderr, "Warning: -o/--output specified multiple times.\n"); free(logfile); @@ -493,7 +486,6 @@ if (logfile[0] == '\0') { cli_classic_abort_usage("No log filename specified.\n"); } -#endif /* STANDALONE */ break; default: cli_classic_abort_usage(NULL); @@ -511,13 +503,10 @@ cli_classic_abort_usage(NULL); if (referencefile && check_filename(referencefile, "reference")) cli_classic_abort_usage(NULL); - -#ifndef STANDALONE if (logfile && check_filename(logfile, "log")) cli_classic_abort_usage(NULL); if (logfile && open_logfile(logfile)) cli_classic_abort_usage(NULL); -#endif /* !STANDALONE */ #if CONFIG_PRINT_WIKI == 1 if (list_supported_wiki) { @@ -532,9 +521,7 @@ goto out; } -#ifndef STANDALONE start_logging(); -#endif /* !STANDALONE */ print_buildinfo(); msg_gdbg("Command line (%i args):", argc - 1); @@ -808,9 +795,7 @@ /* clean up global variables */ free((char *)chip_to_probe); /* Silence! Freeing is not modifying contents. */ chip_to_probe = NULL; -#ifndef STANDALONE free(logfile); ret |= close_logfile(); -#endif /* !STANDALONE */ return ret; } diff --git a/cli_output.c b/cli_output.c index e12446d..629db67 100644 --- a/cli_output.c +++ b/cli_output.c @@ -24,7 +24,6 @@ enum flashrom_log_level verbose_screen = FLASHROM_MSG_INFO; enum flashrom_log_level verbose_logfile = FLASHROM_MSG_DEBUG2; -#ifndef STANDALONE static FILE *logfile = NULL; int close_logfile(void) @@ -64,7 +63,6 @@ print_version(); verbose_screen = oldverbose_screen; } -#endif /* !STANDALONE */ /* Please note that level is the verbosity, not the importance of the message. */ int flashrom_print_cb(enum flashrom_log_level level, const char *fmt, va_list ap) @@ -85,13 +83,13 @@ if (level != FLASHROM_MSG_SPEW) fflush(output_type); } -#ifndef STANDALONE + if ((level <= verbose_logfile) && logfile) { ret = vfprintf(logfile, fmt, logfile_args); if (level != FLASHROM_MSG_SPEW) fflush(logfile); } -#endif /* !STANDALONE */ + va_end(logfile_args); return ret; } diff --git a/flash.h b/flash.h index f63aa5d..b283c6c 100644 --- a/flash.h +++ b/flash.h @@ -442,11 +442,9 @@ /* cli_output.c */ extern enum flashrom_log_level verbose_screen; extern enum flashrom_log_level verbose_logfile; -#ifndef STANDALONE int open_logfile(const char * const filename); int close_logfile(void); void start_logging(void); -#endif int flashrom_print_cb(enum flashrom_log_level level, const char *fmt, va_list ap); /* Let gcc and clang check for correct printf-style format strings. */ int print(enum flashrom_log_level level, const char *fmt, ...) diff --git a/tests/meson.build b/tests/meson.build index 90e0df1..d3b46b1 100644 --- a/tests/meson.build +++ b/tests/meson.build @@ -102,7 +102,6 @@ cargs, '-ffunction-sections', '-fdata-sections', - # '-DSTANDALONE', ], export_dynamic : true, link_args : mocks, -- To view, visit https://review.coreboot.org/c/flashrom/+/63469 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I58fb82270a9884a323d9850176708d230fdc5165 Gerrit-Change-Number: 63469 Gerrit-PatchSet: 1 Gerrit-Owner: Thomas Heijligen <src(a)posteo.de> Gerrit-MessageType: newchange

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Change in flashrom[master]: programmer.h: regroup parts for the internal programmer
by Thomas Heijligen (Code Review) 07 Apr '22

07 Apr '22

Thomas Heijligen has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/63468 ) Change subject: programmer.h: regroup parts for the internal programmer ...................................................................... programmer.h: regroup parts for the internal programmer Change-Id: I0dcdb6c7998eec36e619f6e5c82825f60a2435ac Signed-off-by: Thomas Heijligen <thomas.heijligen(a)secunet.com> --- M programmer.h 1 file changed, 74 insertions(+), 83 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/68/63468/1 diff --git a/programmer.h b/programmer.h index 8abd7d6..bf67a1c 100644 --- a/programmer.h +++ b/programmer.h @@ -141,6 +141,39 @@ int rpci_write_word(struct pci_dev *dev, int reg, uint16_t data); int rpci_write_long(struct pci_dev *dev, int reg, uint32_t data); +/* The following enum is needed by ich_descriptor_tool and ich* code as well as in chipset_enable.c. */ +enum ich_chipset { + CHIPSET_ICH_UNKNOWN, + CHIPSET_ICH, + CHIPSET_ICH2345, + CHIPSET_ICH6, + CHIPSET_POULSBO, /* SCH U* */ + CHIPSET_TUNNEL_CREEK, /* Atom E6xx */ + CHIPSET_CENTERTON, /* Atom S1220 S1240 S1260 */ + CHIPSET_ICH7, + CHIPSET_ICH8, + CHIPSET_ICH9, + CHIPSET_ICH10, + CHIPSET_5_SERIES_IBEX_PEAK, + CHIPSET_6_SERIES_COUGAR_POINT, + CHIPSET_7_SERIES_PANTHER_POINT, + CHIPSET_8_SERIES_LYNX_POINT, + CHIPSET_BAYTRAIL, /* Actually all with Silvermont architecture: Bay Trail, Avoton/Rangeley */ + CHIPSET_8_SERIES_LYNX_POINT_LP, + CHIPSET_8_SERIES_WELLSBURG, + CHIPSET_9_SERIES_WILDCAT_POINT, + CHIPSET_9_SERIES_WILDCAT_POINT_LP, + CHIPSET_100_SERIES_SUNRISE_POINT, /* also 6th/7th gen Core i/o (LP) variants */ + CHIPSET_C620_SERIES_LEWISBURG, + CHIPSET_300_SERIES_CANNON_POINT, + CHIPSET_400_SERIES_COMET_POINT, + CHIPSET_500_SERIES_TIGER_POINT, + CHIPSET_600_SERIES_ALDER_POINT, + CHIPSET_METEOR_LAKE, + CHIPSET_APOLLO_LAKE, + CHIPSET_GEMINI_LAKE, + CHIPSET_ELKHART_LAKE, +}; #if CONFIG_INTERNAL == 1 struct penable { @@ -207,15 +240,6 @@ extern const struct board_info boards_known[]; extern const struct board_info laptops_known[]; -#endif - -/* udelay.c */ -void myusec_delay(unsigned int usecs); -void myusec_calibrate_delay(void); -void internal_sleep(unsigned int usecs); -void internal_delay(unsigned int usecs); - -#if CONFIG_INTERNAL == 1 /* board_enable.c */ int selfcheck_board_enables(void); int board_parse_parameter(const char *boardstring, char **vendor, char **model); @@ -235,9 +259,7 @@ /* processor_enable.c */ int processor_flash_enable(void); -#endif -#if CONFIG_INTERNAL == 1 /* cbtable.c */ int cb_parse_table(const char **vendor, const char **model); int cb_check_image(const uint8_t *bios, unsigned int size); @@ -260,8 +282,7 @@ #define SUPERIO_VENDOR_NONE 0x0 #define SUPERIO_VENDOR_ITE 0x1 #define SUPERIO_VENDOR_WINBOND 0x2 -#endif -#if CONFIG_INTERNAL == 1 + extern int is_laptop; extern int laptop_ok; extern int force_boardenable; @@ -269,8 +290,48 @@ void probe_superio(void); int register_superio(struct superio s); extern enum chipbustype internal_buses_supported; + +/* ichspi.c */ +int ich_init_spi(void *spibar, enum ich_chipset ich_generation); +int via_init_spi(uint32_t mmio_base); + +/* amd_imc.c */ +int amd_imc_shutdown(struct pci_dev *dev); + +/* it85spi.c */ +int it85xx_spi_init(struct superio s); + +/* it87spi.c */ +void enter_conf_mode_ite(uint16_t port); +void exit_conf_mode_ite(uint16_t port); +void probe_superio_ite(void); +int init_superio_ite(void); + +#if CONFIG_LINUX_MTD == 1 +/* trivial wrapper to avoid cluttering internal_init() with #if */ +static inline int try_mtd(void) { return programmer_linux_mtd.init(); }; +#else +static inline int try_mtd(void) { return 1; }; #endif +/* mcp6x_spi.c */ +int mcp6x_spi_init(int want_spi); + + + +/* sb600spi.c */ +int sb600_probe_spi(struct pci_dev *dev); + +/* wbsio_spi.c */ +int wbsio_check_for_spi(void); +#endif + +/* udelay.c */ +void myusec_delay(unsigned int usecs); +void myusec_calibrate_delay(void); +void internal_sleep(unsigned int usecs); +void internal_delay(unsigned int usecs); + /* bitbang_spi.c */ int register_spi_bitbang_master(const struct bitbang_spi_master *master, void *spi_data); @@ -322,76 +383,6 @@ int default_spi_write_aai(struct flashctx *flash, const uint8_t *buf, unsigned int start, unsigned int len); int register_spi_master(const struct spi_master *mst, void *data); -/* The following enum is needed by ich_descriptor_tool and ich* code as well as in chipset_enable.c. */ -enum ich_chipset { - CHIPSET_ICH_UNKNOWN, - CHIPSET_ICH, - CHIPSET_ICH2345, - CHIPSET_ICH6, - CHIPSET_POULSBO, /* SCH U* */ - CHIPSET_TUNNEL_CREEK, /* Atom E6xx */ - CHIPSET_CENTERTON, /* Atom S1220 S1240 S1260 */ - CHIPSET_ICH7, - CHIPSET_ICH8, - CHIPSET_ICH9, - CHIPSET_ICH10, - CHIPSET_5_SERIES_IBEX_PEAK, - CHIPSET_6_SERIES_COUGAR_POINT, - CHIPSET_7_SERIES_PANTHER_POINT, - CHIPSET_8_SERIES_LYNX_POINT, - CHIPSET_BAYTRAIL, /* Actually all with Silvermont architecture: Bay Trail, Avoton/Rangeley */ - CHIPSET_8_SERIES_LYNX_POINT_LP, - CHIPSET_8_SERIES_WELLSBURG, - CHIPSET_9_SERIES_WILDCAT_POINT, - CHIPSET_9_SERIES_WILDCAT_POINT_LP, - CHIPSET_100_SERIES_SUNRISE_POINT, /* also 6th/7th gen Core i/o (LP) variants */ - CHIPSET_C620_SERIES_LEWISBURG, - CHIPSET_300_SERIES_CANNON_POINT, - CHIPSET_400_SERIES_COMET_POINT, - CHIPSET_500_SERIES_TIGER_POINT, - CHIPSET_600_SERIES_ALDER_POINT, - CHIPSET_METEOR_LAKE, - CHIPSET_APOLLO_LAKE, - CHIPSET_GEMINI_LAKE, - CHIPSET_ELKHART_LAKE, -}; - -/* ichspi.c */ -#if CONFIG_INTERNAL == 1 -int ich_init_spi(void *spibar, enum ich_chipset ich_generation); -int via_init_spi(uint32_t mmio_base); - -/* amd_imc.c */ -int amd_imc_shutdown(struct pci_dev *dev); - -/* it85spi.c */ -int it85xx_spi_init(struct superio s); - -/* it87spi.c */ -void enter_conf_mode_ite(uint16_t port); -void exit_conf_mode_ite(uint16_t port); -void probe_superio_ite(void); -int init_superio_ite(void); - -#if CONFIG_LINUX_MTD == 1 -/* trivial wrapper to avoid cluttering internal_init() with #if */ -static inline int try_mtd(void) { return programmer_linux_mtd.init(); }; -#else -static inline int try_mtd(void) { return 1; }; -#endif - -/* mcp6x_spi.c */ -int mcp6x_spi_init(int want_spi); - - - -/* sb600spi.c */ -int sb600_probe_spi(struct pci_dev *dev); - -/* wbsio_spi.c */ -int wbsio_check_for_spi(void); -#endif - /* opaque.c */ struct opaque_master { int max_data_read; -- To view, visit https://review.coreboot.org/c/flashrom/+/63468 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I0dcdb6c7998eec36e619f6e5c82825f60a2435ac Gerrit-Change-Number: 63468 Gerrit-PatchSet: 1 Gerrit-Owner: Thomas Heijligen <src(a)posteo.de> Gerrit-MessageType: newchange

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Change in flashrom[master]: NEED_PCI: remove macro
by Thomas Heijligen (Code Review) 07 Apr '22

07 Apr '22

Attention is currently required from: Nico Huber, Angel Pons. Hello build bot (Jenkins), Nico Huber, Angel Pons, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/flashrom/+/62834 to look at the new patch set (#4). Change subject: NEED_PCI: remove macro ...................................................................... NEED_PCI: remove macro The NEED_PCI macro is only used to guard prototypes. This is not needed. Change-Id: I6895b795bc96b3e251700bff4b0054407aac789a Signed-off-by: Thomas Heijligen <thomas.heijligen(a)secunet.com> --- M Makefile M meson.build M programmer.h 3 files changed, 1 insertion(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/34/62834/4 -- To view, visit https://review.coreboot.org/c/flashrom/+/62834 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I6895b795bc96b3e251700bff4b0054407aac789a Gerrit-Change-Number: 62834 Gerrit-PatchSet: 4 Gerrit-Owner: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newpatchset

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Change in flashrom[master]: ichspi: Add `PCH100_` prefix for `Write Enable Type (WET)` macros
by Subrata Banik (Code Review) 07 Apr '22

07 Apr '22

Attention is currently required from: Subrata Banik, Nico Huber, Angel Pons. Hello build bot (Jenkins), Nico Huber, Edward O'Callaghan, Angel Pons, Anastasia Klimchuk, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/flashrom/+/62888 to look at the new patch set (#8). Change subject: ichspi: Add `PCH100_` prefix for `Write Enable Type (WET)` macros ...................................................................... ichspi: Add `PCH100_` prefix for `Write Enable Type (WET)` macros This patch renames the `WET` macro definitions based on its availability with PCH100 onwards chipset. HSFC_WET_OFF -> PCH100_HSFC_WET_OFF HSFC_WET -> PCH100_HSFC_WET BUG=b:223630977 TEST=Able to perform read/write/erase operation on PCH 600 series chipset (board name: Brya). Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: Id32cb4ccb83dd08e9b0b1ab30cc8e041dd059f5f --- M ichspi.c 1 file changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/88/62888/8 -- To view, visit https://review.coreboot.org/c/flashrom/+/62888 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Id32cb4ccb83dd08e9b0b1ab30cc8e041dd059f5f Gerrit-Change-Number: 62888 Gerrit-PatchSet: 8 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Subrata Banik <subi.banik(a)gmail.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newpatchset

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Change in flashrom[master]: ichspi: Add `PCH100_` prefix for `Write Enable Type (WET)` macros
by Subrata Banik (Code Review) 07 Apr '22

07 Apr '22

Attention is currently required from: Subrata Banik, Nico Huber, Angel Pons. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/62888 ) Change subject: ichspi: Add `PCH100_` prefix for `Write Enable Type (WET)` macros ...................................................................... Patch Set 6: (1 comment) File ichspi.c: https://review.coreboot.org/c/flashrom/+/62888/comment/a426634f_b8a1b86c PS6, Line 91: /* New HSFC Control bit */ > +1 on renaming Ack -- To view, visit https://review.coreboot.org/c/flashrom/+/62888 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Id32cb4ccb83dd08e9b0b1ab30cc8e041dd059f5f Gerrit-Change-Number: 62888 Gerrit-PatchSet: 6 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Subrata Banik <subi.banik(a)gmail.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Thu, 07 Apr 2022 15:56:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in flashrom[master]: ichspi: Add `PCH100_` prefix for `Write Enable Type (WET)` macros
by Subrata Banik (Code Review) 07 Apr '22

07 Apr '22

Attention is currently required from: Subrata Banik, Nico Huber. Hello build bot (Jenkins), Nico Huber, Edward O'Callaghan, Angel Pons, Anastasia Klimchuk, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/flashrom/+/62888 to look at the new patch set (#7). Change subject: ichspi: Add `PCH100_` prefix for `Write Enable Type (WET)` macros ...................................................................... ichspi: Add `PCH100_` prefix for `Write Enable Type (WET)` macros This patch renames the `WET` macro definitions based on its availability with PCH100 onwards chipset. HSFC_WET_OFF -> PCH100_HSFC_WET_OFF HSFC_WET -> PCH100_HSFC_WET BUG=b:223630977 TEST=Able to perform read/write/erase operation on PCH 600 series chipset (board name: Brya). Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: Id32cb4ccb83dd08e9b0b1ab30cc8e041dd059f5f --- M ichspi.c 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/88/62888/7 -- To view, visit https://review.coreboot.org/c/flashrom/+/62888 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Id32cb4ccb83dd08e9b0b1ab30cc8e041dd059f5f Gerrit-Change-Number: 62888 Gerrit-PatchSet: 7 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Subrata Banik <subi.banik(a)gmail.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: newpatchset

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Change in flashrom[master]: ichspi: Unify timeouts across all SPI operations to 30s
by Subrata Banik (Code Review) 07 Apr '22

07 Apr '22

Attention is currently required from: Subrata Banik, Nico Huber, Paul Menzel, Edward O'Callaghan, Angel Pons, Anastasia Klimchuk. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/62867 ) Change subject: ichspi: Unify timeouts across all SPI operations to 30s ...................................................................... Patch Set 13: (3 comments) Commit Message: https://review.coreboot.org/c/flashrom/+/62867/comment/a8e3d2a0_8d05aa73 PS12, Line 38: Here is the timeout calculation for any hardware sequencing operation: : Worst Case Operational Delay = : (Maximum Time consumed by a SPI operation + Any marginal : adjustment) : : Timeout Recommendation for Hardware Sequencing Operation = : ((Worst Case Operational Delay) * (#No. Of SPI Master - 1) + : Current Operational latency) : : Assume, on Intel platform with 2 SPI master like, Host CPU and CSE, the : Timeout Calculation for SPI Write Operation would look like as below: : : Maximum Time consumed by a SPI Operation = 2 seconds : (for SPI Erase Operation as per Winbond Data Sheet) : : Worst Case Operational Delay = (2 seconds + 50 milliseconds) = : 2 seconds 50 milliseconds : Timeout Recommendation for Hardware Seq Operation = : (2 seconds 50 milliseconds) * (2 - 1) + 15 milliseconds : (for SPI Write Operation as per Winbond Data Sheet) : = 2 seconds 65 milliseconds > Doing the calculation with these numbers can be a bit confusing. I'd > do it with the estimated worst-case numbers right away (i.e. 6 masters, > 5s). > > Shorting some things might make it more readable, e.g. `2.05s` instead > of `2 seconds 50 milliseconds`, also shorter identifiers and removing > unnecessary parentheses can help legibility. ACK File ichspi.c: https://review.coreboot.org/c/flashrom/+/62867/comment/b5e01201_699130ba PS12, Line 1281: operation > `operations`? because multiple masters would preform multiple operations? ACK https://review.coreboot.org/c/flashrom/+/62867/comment/69952a8d_c524dd26 PS12, Line 1282: introduces > `introduce` without s, I guess ACK -- To view, visit https://review.coreboot.org/c/flashrom/+/62867 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Ifa910dea794175d8ee2ad277549e5a0d69cba45b Gerrit-Change-Number: 62867 Gerrit-PatchSet: 13 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Subrata Banik <subi.banik(a)gmail.com> Gerrit-Attention: Subrata Banik <subi.banik(a)gmail.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Comment-Date: Thu, 07 Apr 2022 15:17:18 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: comment

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