April 2022 - flashrom-gerrit - mail.coreboot.org

Change in flashrom[master]: hwaccess: use __asm__ as it is done elsewhere
by Felix Singer (Code Review) 08 Apr '22

08 Apr '22

Felix Singer has uploaded a new patch set (#2). ( https://review.coreboot.org/c/flashrom/+/63487 ) Change subject: hwaccess: use __asm__ as it is done elsewhere ...................................................................... hwaccess: use __asm__ as it is done elsewhere `asm()` is glibc specific. Thus, use `__asm__` as it is done elsewhere and fix compilation under non glibc, such as musl. Change-Id: I834fa6e171d2b20e1a5faa5a2e8f54caf107171a Signed-off-by: Rosen Penev <rosenp(a)gmail.com> Signed-off-by: Felix Singer <felixsinger(a)posteo.net> --- M hwaccess_physmap.c 1 file changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/87/63487/2 -- To view, visit https://review.coreboot.org/c/flashrom/+/63487 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I834fa6e171d2b20e1a5faa5a2e8f54caf107171a Gerrit-Change-Number: 63487 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-MessageType: newpatchset

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Change in flashrom[master]: hwaccess: use __asm__ as it is done elsewhere
by Felix Singer (Code Review) 08 Apr '22

08 Apr '22

Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/63487 ) Change subject: hwaccess: use __asm__ as it is done elsewhere ...................................................................... hwaccess: use __asm__ as it is done elsewhere `asm()` is glibc specific. Thus, use `__asm__` as it is done elsewhere and fix compilation under non glibc, such as musl. Signed-off-by: Rosen Penev <rosenp(a)gmail.com> Signed-off-by: Felix Singer <felixsinger(a)posteo.net> Change-Id: I834fa6e171d2b20e1a5faa5a2e8f54caf107171a --- M hwaccess_physmap.c 1 file changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/87/63487/1 diff --git a/hwaccess_physmap.c b/hwaccess_physmap.c index b1b9c64..880d6ce 100644 --- a/hwaccess_physmap.c +++ b/hwaccess_physmap.c @@ -382,18 +382,18 @@ #if defined(__powerpc) || defined(__powerpc__) || defined(__powerpc64__) || defined(__POWERPC__) || \ defined(__ppc__) || defined(__ppc64__) || defined(_M_PPC) || defined(_ARCH_PPC) || \ defined(_ARCH_PPC64) || defined(__ppc) - asm("eieio" : : : "memory"); + __asm__("eieio" : : : "memory"); #elif (__sparc__) || defined (__sparc) #if defined(__sparc_v9__) || defined(__sparcv9) /* Sparc V9 CPUs support three different memory orderings that range from x86-like TSO to PowerPC-like * RMO. The modes can be switched at runtime thus to make sure we maintain the right order of access we * use the strongest hardware memory barriers that exist on Sparc V9. */ - asm volatile ("membar #Sync" ::: "memory"); + __asm__ volatile ("membar #Sync" ::: "memory"); #elif defined(__sparc_v8__) || defined(__sparcv8) /* On SPARC V8 there is no RMO just PSO and that does not apply to I/O accesses... but if V8 code is run * on V9 CPUs it might apply... or not... we issue a write barrier anyway. That's the most suitable * operation in the V8 instruction set anyway. If you know better then please tell us. */ - asm volatile ("stbar"); + __asm__ volatile ("stbar"); #else #error Unknown and/or unsupported SPARC instruction set version detected. #endif -- To view, visit https://review.coreboot.org/c/flashrom/+/63487 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I834fa6e171d2b20e1a5faa5a2e8f54caf107171a Gerrit-Change-Number: 63487 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-MessageType: newchange

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Change in flashrom[master]: ichspi: Add Jasper Lake support
by Edward O'Callaghan (Code Review) 08 Apr '22

08 Apr '22

Attention is currently required from: Nico Huber, Subrata Banik, Angel Pons. Edward O'Callaghan has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/62282 ) Change subject: ichspi: Add Jasper Lake support ...................................................................... Patch Set 10: (1 comment) Patchset: PS4: > > You are right `NM` is confusing, can we comment it better? Possibly copy what you just said there […] Yes, everything has been re-tested. Here is the diff of the log: ``` localhost ~ # diff -u /tmp/log /tmp/log1 | grep -E '^(\+|-)' --- /tmp/log 2022-04-07 18:37:54.765981410 -0700 +++ /tmp/log1 2022-04-07 18:55:48.066354412 -0700 -pre-rounding: start=0x00007f600ac74040, len=0x348, end=0x00007f600ac74388 -post-rounding: start=0x00007f600ac74000, len=0x1000, end=0x00007f600ac75000 +pre-rounding: start=0x00007b5026fbe040, len=0x348, end=0x00007b5026fbe388 +post-rounding: start=0x00007b5026fbe000, len=0x1000, end=0x00007b5026fbf000 -pre-rounding: start=0x00007f600aa0f000, len=0x10000, end=0x00007f600aa1f000 -post-rounding: start=0x00007f600aa0f000, len=0x10000, end=0x00007f600aa1f000 +pre-rounding: start=0x00007b5026d59000, len=0x10000, end=0x00007b5026d69000 +post-rounding: start=0x00007b5026d59000, len=0x10000, end=0x00007b5026d69000 -SPIBAR = 0x00007f600ac74000 (phys = 0xfe010000) +SPIBAR = 0x00007b5026fbe000 (phys = 0xfe010000) -NM (Number of Masters): 2 +NM (Number of Masters): 3 +FLMSTR3 0x00000000 +GbE -programmer_map_flash_region: mapping GD25Q127C/GD25Q128C from 0x00000000ff000000 to 0x00007f6009a1f000 +programmer_map_flash_region: mapping GD25Q127C/GD25Q128C from 0x00000000ff000000 to 0x00007b5025d69000 -pre-rounding: start=0x00007f6009a1f000, len=0x1000000, end=0x00007f600aa1f000 -post-rounding: start=0x00007f6009a1f000, len=0x1000000, end=0x00007f600aa1f000 -programmer_unmap_flash_region: unmapped 0x00007f6009a1f000 +pre-rounding: start=0x00007b5025d69000, len=0x1000000, end=0x00007b5026d69000 +post-rounding: start=0x00007b5025d69000, len=0x1000000, end=0x00007b5026d69000 +programmer_unmap_flash_region: unmapped 0x00007b5025d69000 -programmer_map_flash_region: mapping GD25Q127C/GD25Q128C from 0x00000000ff000000 to 0x00007f6008a1e000 +programmer_map_flash_region: mapping GD25Q127C/GD25Q128C from 0x00000000ff000000 to 0x00007b5024d68000 -pre-rounding: start=0x00007f6008a1e000, len=0x1000000, end=0x00007f6009a1e000 -post-rounding: start=0x00007f6008a1e000, len=0x1000000, end=0x00007f6009a1e000 -programmer_unmap_flash_region: unmapped 0x00007f6008a1e000 +pre-rounding: start=0x00007b5024d68000, len=0x1000000, end=0x00007b5025d68000 +post-rounding: start=0x00007b5024d68000, len=0x1000000, end=0x00007b5025d68000 +programmer_unmap_flash_region: unmapped 0x00007b5024d68000 ``` with the diff: ``` diff --git a/ich_descriptors.c b/ich_descriptors.c index 832ca949..51e5c292 100644 --- a/ich_descriptors.c +++ b/ich_descriptors.c @@ -76,7 +76,7 @@ ssize_t ich_number_of_masters(const enum ich_chipset cs, const struct ich_desc_c case CHIPSET_APOLLO_LAKE: case CHIPSET_600_SERIES_ALDER_POINT: case CHIPSET_GEMINI_LAKE: - case CHIPSET_JASPER_LAKE: + //case CHIPSET_JASPER_LAKE: ``` As can be observed `FLMSTR3 0x00000000` so I think `ich_number_of_masters()` is correct. Full log here of this commit: ``` Laptop detected via DMI. DMI string system-manufacturer: "Google" DMI string system-product-name: "Magolor" DMI string system-version: "rev3" DMI string baseboard-manufacturer: "Google" DMI string baseboard-product-name: "Magolor" DMI string baseboard-version: "rev3" Found chipset "Intel Jasper Lake" with PCI ID 8086:4da4. Enabling flash write... BIOS_SPI_BC = 0x8b: BIOS Interface Lock-Down: enabled, Boot BIOS Straps: 0x0 (SPI) Top Swap: not enabled SPI Read Configuration: prefetching enabled, caching enabled, BIOS_CNTL = 0x8b: BIOS Lock Enable: enabled, BIOS Write Enable: enabled page_size=1000 pre-rounding: start=0x00000000fe010000, len=0x1000, end=0x00000000fe011000 post-rounding: start=0x00000000fe010000, len=0x1000, end=0x00000000fe011000 SPIBAR = 0x00007f600ac74000 (phys = 0xfe010000) 0x04: 0xe000 (HSFS) HSFS: FDONE=0, FCERR=0, AEL=0, BERASE=0, SCIP=0, FDOPSS=1, FDV=1, FLOCKDN=1 SPI Configuration is locked down. Reading OPCODES... done OP Type Pre-OP op[0]: 0x01, write w/o addr, none op[1]: 0x02, write w/ addr, none op[2]: 0x03, read w/ addr, none op[3]: 0x05, read w/o addr, none op[4]: 0x20, write w/ addr, none op[5]: 0x9f, read w/o addr, none op[6]: 0xd8, write w/ addr, none op[7]: 0x0b, read w/ addr, none Pre-OP 0: 0x06, Pre-OP 1: 0x50 0x06: 0x3f00 (HSFC) HSFC: FGO=0, FCYCLE=0, FDBC=63, SME=0 0x08: 0x00000fc0 (FADDR) 0x0c: 0x00001f00 (DLOCK) DLOCK: BMWAG_LOCKDN=0, BMRAG_LOCKDN=0, SBMWAG_LOCKDN=0, SBMRAG_LOCKDN=0, PR0_LOCKDN=1, PR1_LOCKDN=1, PR2_LOCKDN=1, PR3_LOCKDN=1, PR4_LOCKDN=1, SSEQ_LOCKDN=0 0x50: 0x000042c7 (FRAP) BMWAG 0x00, BMRAG 0x00, BRWA 0x42, BRRA 0xc7 0x54: 0x00000000 FREG0: Flash Descriptor region (0x00000000-0x00000fff) is read-only. 0x58: 0x0fff0381 FREG1: BIOS region (0x00381000-0x00ffffff) is read-write. 0x5C: 0x03800001 FREG2: Management Engine region (0x00001000-0x00380fff) is read-only. 0x60: 0x00007fff FREG3: Gigabit Ethernet region is unused. 0x64: 0x00007fff FREG4: Platform Data region is unused. 0x68: 0x00007fff FREG5: Device Expansion region is unused. 0x6C: 0x00007fff FREG6: BIOS2 region is unused. 0x70: 0x00007fff FREG7: unknown region is unused. Reading flash descriptors mapped by the chipset via FDOC/FDOD... done. 0x74: 0x3f00e000 FREG8: EC/BMC region is unused. 0x78: 0x00007fff FREG9: unknown region is unused. 0x7C: 0x00007fff FREG10: unknown region is unused. 0x80: 0x00007fff FREG11: unknown region is unused. 0xE0: 0x00007fff FREG12: unknown region is unused. 0xE4: 0x00007fff FREG13: unknown region is unused. 0xE8: 0x00007fff FREG14: unknown region is unused. 0xEC: 0x00007fff FREG15: unknown region is unused. Not all flash regions are freely accessible by flashrom. This is most likely due to an active ME. Please see https://flashrom.org/ME for details. 0x84: 0x00000000 (PR0 is unused) 0x88: 0x00000000 (PR1 is unused) 0x8C: 0x00000000 (PR2 is unused) 0x90: 0x00000000 (PR3 is unused) 0x94: 0x00000000 (PR4 is unused) 0x98: 0x80f50001 0xa0: 0x80 (SSFS) SSFS: SCIP=0, FDONE=0, FCERR=0, AEL=0 0xa1: 0xfe0000 (SSFC) SSFC: SCGO=0, ACS=0, SPOP=0, COP=0, DBC=0, SME=0, SCF=6 0xa4: 0x5006 (PREOP) 0xa6: 0xb32d (OPTYPE) 0xa8: 0x05030201 (OPMENU) 0xac: 0x0bd89f20 (OPMENU+4) 0xc4: 0xf3d82004 (LVSCC) LVSCC: BES=0x0, WG=1, WSR=0, WEWS=0, EO=0x20, VCL=1 0xc8: 0x00002000 (UVSCC) UVSCC: BES=0x0, WG=0, WSR=0, WEWS=0, EO=0x20 Reading flash descriptors mapped by the chipset via FDOC/FDOD... done. === Content Section === FLVALSIG 0x0ff0a55a FLMAP0 0x00040003 FLMAP1 0x2a100208 FLMAP2 0x000301b0 --- Details --- NR (Number of Regions): 16 FRBA (Flash Region Base Address): 0x040 NC (Number of Components): 1 FCBA (Flash Component Base Address): 0x030 ISL (ICH/PCH/SoC Strap Length): 42 FISBA/FPSBA (Flash ICH/PCH/SoC Strap Base Addr): 0x100 NM (Number of Masters): 2 FMBA (Flash Master Base Address): 0x080 MSL/PSL (MCH/PROC Strap Length): 1 FMSBA (Flash MCH/PROC Strap Base Address): 0xb00 === Component Section === FLCOMP 0x12583cf5 FLILL 0xad604221 FLILL1 0xc7c4b9b7 --- Details --- Component 1 density: 16 MB Component 2 is not used. Read Clock Frequency: 30 MHz Read ID and Status Clock Freq.: 48 MHz Write and Erase Clock Freq.: 48 MHz Fast Read is supported. Fast Read Clock Frequency: 48 MHz Dual Output Fast Read Support: disabled Invalid instruction 0: 0x21 Invalid instruction 1: 0x42 Invalid instruction 2: 0x60 Invalid instruction 3: 0xad Invalid instruction 4: 0xb7 Invalid instruction 5: 0xb9 Invalid instruction 6: 0xc4 Invalid instruction 7: 0xc7 === Region Section === FLREG0 0x00000000 FLREG1 0x0fff0381 FLREG2 0x03800001 FLREG3 0x00007fff FLREG4 0x00007fff FLREG5 0x00007fff FLREG6 0x00007fff FLREG7 0x00007fff FLREG8 0x00007fff FLREG9 0x00007fff FLREG10 0x00007fff FLREG11 0x00007fff FLREG12 0x00007fff FLREG13 0x00007fff FLREG14 0x00007fff FLREG15 0x00007fff --- Details --- Region 0 (Descr. ) 0x00000000 - 0x00000fff Region 1 (BIOS ) 0x00381000 - 0x00ffffff Region 2 (ME ) 0x00001000 - 0x00380fff Region 3 (GbE ) is unused. Region 4 (Platf. ) is unused. Region 5 (DevExp ) is unused. Region 6 (BIOS2 ) is unused. Region 7 (unknown) is unused. Region 8 (EC/BMC ) is unused. Region 9 (unknown) is unused. Region 10 (IE ) is unused. Region 11 (10GbE ) is unused. Region 12 (unknown) is unused. Region 13 (unknown) is unused. Region 14 (unknown) is unused. Region 15 (unknown) is unused. === Master Section === FLMSTR1 0x00200700 FLMSTR2 0x00400500 --- Details --- FD BIOS ME GbE Pltf Reg5 Reg6 Reg7 EC Reg9 RegA RegB RegC RegD RegE RegF BIOS r rw r ME r rw checking for opcode 0x03 checking for opcode 0x05 Enabling hardware sequencing by default for 100+ series PCH. OK. No board enable found matching coreboot IDs vendor="Google", model="Magolor". The following protocols are supported: Programmer-specific. Probing for Programmer Opaque flash chip, 0 kB: Chip identified: GD25Q127C/GD25Q128C Hardware sequencing reports 1 attached SPI flash chip with a density of 16384 kB. There is only one partition containing the whole address space (0x000000 - 0xffffff). There are 4096 erase blocks with 4096 B each. Added layout entry 00000000 - 00ffffff named complete flash Found GigaDevice flash chip "GD25Q127C/GD25Q128C" (16384 kB, Programmer-specific) mapped at physical address 0x0000000000000000. Found GigaDevice flash chip "GD25Q127C/GD25Q128C" (16384 kB, Programmer-specific). This chip may contain one-time programmable memory. flashrom cannot read and may never be able to write it, hence it may not be able to completely clone the contents of this chip (see man page for details). page_size=1000 pre-rounding: start=0x00000000ff000000, len=0x1000000, end=0x0000000100000000 post-rounding: start=0x00000000ff000000, len=0x1000000, end=0x0000000100000000 programmer_map_flash_region: mapping GD25Q127C/GD25Q128C from 0x00000000ff000000 to 0x00007f6009a1f000 Reading Status register Block protection is disabled. Reading ich descriptor... Reading 4096 bytes starting at 0x000000. done. Assuming chipset 'Gemini Lake'. Added layout entry 00000000 - 00000fff named fd Added layout entry 00381000 - 00ffffff named bios Added layout entry 00001000 - 00380fff named me page_size=1000 pre-rounding: start=0x00007f6009a1f000, len=0x1000000, end=0x00007f600aa1f000 post-rounding: start=0x00007f6009a1f000, len=0x1000000, end=0x00007f600aa1f000 programmer_unmap_flash_region: unmapped 0x00007f6009a1f000 restore_power_management: Re-enabling power management. Looking for region "bios"... found. Looking for region "fd"... found. Using regions: "bios", "fd". page_size=1000 pre-rounding: start=0x00000000ff000000, len=0x1000000, end=0x0000000100000000 post-rounding: start=0x00000000ff000000, len=0x1000000, end=0x0000000100000000 programmer_map_flash_region: mapping GD25Q127C/GD25Q128C from 0x00000000ff000000 to 0x00007f6008a1e000 Reading Status register Block protection is disabled. Reading flash... 0x381000-0xffffff:R Reading 13103104 bytes starting at 0x381000. 000000-0x0fff:R Reading 4096 bytes starting at 0x000000. done. page_size=1000 pre-rounding: start=0x00007f6008a1e000, len=0x1000000, end=0x00007f6009a1e000 post-rounding: start=0x00007f6008a1e000, len=0x1000000, end=0x00007f6009a1e000 programmer_unmap_flash_region: unmapped 0x00007f6008a1e000 restore_power_management: Re-enabling power management. SUCCESS Restoring PCI config space for 00:1f:5 reg 0xdc ``` -- To view, visit https://review.coreboot.org/c/flashrom/+/62282 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Ib942d0b8942fe0a991b2af0b187414818485153d Gerrit-Change-Number: 62282 Gerrit-PatchSet: 10 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Sam McNally <sammc(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Fri, 08 Apr 2022 02:10:21 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: comment

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Change in flashrom[master]: tests/: Add file path and flags validation to open() calls
by Anastasia Klimchuk (Code Review) 08 Apr '22

08 Apr '22

Attention is currently required from: Sam McNally, Edward O'Callaghan, Daniel Campello. Anastasia Klimchuk has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/62320 ) Change subject: tests/: Add file path and flags validation to open() calls ...................................................................... Patch Set 14: (2 comments) File tests/chip.c: https://review.coreboot.org/c/flashrom/+/62320/comment/311bd758_ccbea199 PS14, Line 201: io_mock_register(&chip_io); `io_mock_register(&chip_io)` can be moved into `setup_chip`. That would need one more argument for setup_chip, to pass chip_io, because it is not exactly the same for all tests. But at least registration (and de-registration) can be moved to a common place, setup/teardown. https://review.coreboot.org/c/flashrom/+/62320/comment/f1c26173_6f82bffc PS14, Line 216: io_mock_register(NULL); `io_mock_register(NULL)` can be moved into `teardown` because it just repeats at the end of each test. -- To view, visit https://review.coreboot.org/c/flashrom/+/62320 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I892fa1ecee26ebce9640893edbb228fa9aa7b0b6 Gerrit-Change-Number: 62320 Gerrit-PatchSet: 14 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Daniel Campello <campello(a)chromium.org> Gerrit-Reviewer: Sam McNally <sammc(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Sam McNally <sammc(a)google.com> Gerrit-Attention: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Attention: Daniel Campello <campello(a)chromium.org> Gerrit-Comment-Date: Fri, 08 Apr 2022 00:35:14 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in flashrom[master]: flashrom.8.tmpl: Add raiden_debug_spi doc entry
by Edward O'Callaghan (Code Review) 08 Apr '22

08 Apr '22

Attention is currently required from: Felix Singer, Nico Huber, Martin Roth, Angel Pons, Anastasia Klimchuk, Nikolai Artemiev. Edward O'Callaghan has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/62768 ) Change subject: flashrom.8.tmpl: Add raiden_debug_spi doc entry ...................................................................... Patch Set 1: (9 comments) File flashrom.8.tmpl: https://review.coreboot.org/c/flashrom/+/62768/comment/c28427cb_ce7e20eb PS1, Line 361: .BR "* raiden_debug_spi" " (for SPI flash ROMs attached to a ChromiumOS servo debug board)" > Servo V2 (and maybe V3, which I think is completely obsolete now) uses the FTDI code. […] Done https://review.coreboot.org/c/flashrom/+/62768/comment/d974a0b8_9bf34244 PS1, Line 361: .BR "* raiden_debug_spi" " (for SPI flash ROMs attached to a ChromiumOS servo debug board)" > Servo V2 (and maybe V3, which I think is completely obsolete now) uses the FTDI code. […] Done https://review.coreboot.org/c/flashrom/+/62768/comment/7c648447_9bc335a2 PS1, Line 1137: syntax > Add a comma after syntax Done https://review.coreboot.org/c/flashrom/+/62768/comment/9fcda2ec_49b72792 PS1, Line 1137: syntax > Add a comma after syntax Done https://review.coreboot.org/c/flashrom/+/62768/comment/50970470_51e21226 PS1, Line 1143: servo serial to use > Clarify whether this is by the serial number of the board or a uart: /dev/tty […] Done https://review.coreboot.org/c/flashrom/+/62768/comment/9706e5d0_30159c3b PS1, Line 1147: syntax. > This sounds wrong here. […] Done https://review.coreboot.org/c/flashrom/+/62768/comment/8b06b089_b3c21eda PS1, Line 1147: syntax. > This sounds wrong here. […] Done https://review.coreboot.org/c/flashrom/+/62768/comment/19834387_a0808d6d PS1, Line 1154: custom_rst=(true,false) > I suggest using this scheme, since it is very common I think. […] Done https://review.coreboot.org/c/flashrom/+/62768/comment/b5083811_67a9a393 PS1, Line 1154: custom_rst=(true,false) > I suggest using this scheme, since it is very common I think. […] Done -- To view, visit https://review.coreboot.org/c/flashrom/+/62768 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I186920006bdfcc7a9f89542f84b452dfc72b18e4 Gerrit-Change-Number: 62768 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Attention: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Comment-Date: Fri, 08 Apr 2022 00:28:49 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Singer <felixsinger(a)posteo.net> Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Martin Roth <martinroth(a)google.com> Comment-In-Reply-To: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-MessageType: comment

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Change in flashrom[master]: flashrom.8.tmpl: Add raiden_debug_spi doc entry
by Edward O'Callaghan (Code Review) 08 Apr '22

08 Apr '22

Attention is currently required from: Nico Huber, Edward O'Callaghan, Angel Pons, Anastasia Klimchuk, Nikolai Artemiev. Hello build bot (Jenkins), Martin Roth, Angel Pons, Anastasia Klimchuk, Nikolai Artemiev, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/flashrom/+/62768 to look at the new patch set (#2). Change subject: flashrom.8.tmpl: Add raiden_debug_spi doc entry ...................................................................... flashrom.8.tmpl: Add raiden_debug_spi doc entry BUG=b:224358254 TEST=`man ./flashrom.8.tmpl`. Change-Id: I186920006bdfcc7a9f89542f84b452dfc72b18e4 Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> --- M flashrom.8.tmpl 1 file changed, 41 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/68/62768/2 -- To view, visit https://review.coreboot.org/c/flashrom/+/62768 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I186920006bdfcc7a9f89542f84b452dfc72b18e4 Gerrit-Change-Number: 62768 Gerrit-PatchSet: 2 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Attention: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-MessageType: newpatchset

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Change in flashrom[master]: flashrom.8.tmpl: Add raiden_debug_spi doc entry
by Martin Roth (Code Review) 07 Apr '22

07 Apr '22

Attention is currently required from: Nico Huber, Edward O'Callaghan, Angel Pons, Anastasia Klimchuk, Nikolai Artemiev. Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/62768 ) Change subject: flashrom.8.tmpl: Add raiden_debug_spi doc entry ...................................................................... Patch Set 1: (3 comments) File flashrom.8.tmpl: https://review.coreboot.org/c/flashrom/+/62768/comment/e9abd0f8_6ae729e3 PS1, Line 319: Currently supported are > This is of course not for this patch, but is there any reason programmers are not in alphabetical or […] I was thinking the same thing. Both here and in the flashrom list itself. https://review.coreboot.org/c/flashrom/+/62768/comment/3d8f208e_386a6e1a PS1, Line 361: .BR "* raiden_debug_spi" " (for SPI flash ROMs attached to a ChromiumOS servo debug board)" > ft2232_spi also works with Servo. I guess it's about the version? Also, […] Servo V2 (and maybe V3, which I think is completely obsolete now) uses the FTDI code. For some firmware engineers, the servo V2 is still the preferred flashing method because it's significantly faster than any of the debug tools using the Raiden driver. SuzyQable, Servo V4, uServo, and C2D2 debug tools all use the Raiden driver as they're all based on the Chrome EC codebase in one way or another. Maybe: "* raiden_debug_spi" " (For Chrome EC based debug tools - SuzyQable, Servo V4, C2D2 & uServo) https://review.coreboot.org/c/flashrom/+/62768/comment/2d24c299_1159d7a7 PS1, Line 1143: servo serial to use Clarify whether this is by the serial number of the board or a uart: /dev/tty Add instructions on how to figure out which servo is which. -- To view, visit https://review.coreboot.org/c/flashrom/+/62768 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I186920006bdfcc7a9f89542f84b452dfc72b18e4 Gerrit-Change-Number: 62768 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Attention: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Comment-Date: Thu, 07 Apr 2022 21:25:53 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-MessageType: comment

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Change in flashrom[master]: board_enable.c: Add ME unlock function for Clevo laptops
by Sergii Dmytruk (Code Review) 07 Apr '22

07 Apr '22

Attention is currently required from: Felix Singer, Nico Huber, Michał Żygowski, Paul Menzel, Angel Pons, Arthur Heymans, Michael Niewöhner. Sergii Dmytruk has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/56023 ) Change subject: board_enable.c: Add ME unlock function for Clevo laptops ...................................................................... Patch Set 15: (1 comment) File board_enable.c: https://review.coreboot.org/c/flashrom/+/56023/comment/af4b7f1d_93564f18 PS2, Line 2339: return 0; > That would be one of the little changes, e.g. make calling > register_shutdown() optional, then the tool would have to call > pcidev_shutdown() directly. Except that it's used four times in the file and there is also one use of extract_programmer_param(). These need to not be mentioned at all in order to get rid of the symbols in object files. And then there is invocation of print() from libflashrom.c, which in turn depends on flashrom.c... That said, you're welcome to give it a try :) or suggest alternatives. We might also choose to write a completely standalone tool for unlocking if all our attempts here fail. -- To view, visit https://review.coreboot.org/c/flashrom/+/56023 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I6bf1c40900aa674e3ea4f6add12dae8b73759fbb Gerrit-Change-Number: 56023 Gerrit-PatchSet: 15 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Comment-Date: Thu, 07 Apr 2022 20:55:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Michał Żygowski <michal.zygowski(a)3mdeb.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Comment-In-Reply-To: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-MessageType: comment

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Change in flashrom[master]: sb600spi.c: Use SPI100 bit mappings
by Felix Held (Code Review) 07 Apr '22

07 Apr '22

Attention is currently required from: Robert Zieba, Paul Menzel, Jon Murphy, Edward O'Callaghan, Karthik Ramasubramanian. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/63422 ) Change subject: sb600spi.c: Use SPI100 bit mappings ...................................................................... Patch Set 2: (1 comment) File sb600spi.c: https://review.coreboot.org/c/flashrom/+/63422/comment/5ff704c5_80c12a27 PS1, Line 574: promontory_read_memmapped( > So this hack was added because reading using SPI commands is very slow compared to using the mmap. […] since this is also in the public version of the cezanne ppr, i'll just paste it here: The SPI configuration registers are accessed through SPI base address specified by FCH::LPCPCICFG::spi_base_addr. Software can communicate with the SPI ROM through the default memory or an alternate programming (a.k.a "Indexed mode") method: • Memory access to the BIOS ROM address space is automatically handled by the hardware. The SPI ROM controller translates the memory address onto the SPI bus and accesses the SPI ROM data. Any other commands besides memory read or memory write to the SPI ROM need to go through the alternate programming (a.k.a "Indexed mode") method. SPI ROM access through the memory address is limited to a 24-bit address (16MB addressable space). • With the alternate programming (a.k.a "Indexed mode") method, software needs to program the SpiOpCode, SpiAddress, TxByteCount, RxByteCount, put the data into the transmit FIFO, and then execute the command. The hardware communicates with the SPI ROM using these parameters. This alternate programming (a.k.a "Indexed mode") method basically allows software to issue any flash vendor specific commands such as ERASE and STATUS. The alternate programming method can generate up to 32-bit addresses, but transfers are limited to "normal" (1-bit) mode. i read from that that the indirect access is always in normal spi mode and only the memory mapped reads will use the dual or quad mode. for reads the interface speed is the limiting factor. the prefetching might be another factor. the mmio access is however limited to 16MByte of flash; unsure how this will behave when using 32 bit flash chips -- To view, visit https://review.coreboot.org/c/flashrom/+/63422 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: If42130757331f4294b5a42c848557d3287f24fc3 Gerrit-Change-Number: 63422 Gerrit-PatchSet: 2 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Robert Zieba <robertzieba(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Robert Zieba <robertzieba(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jon Murphy <jpmurphy(a)google.com> Gerrit-Attention: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Thu, 07 Apr 2022 20:13:26 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Comment-In-Reply-To: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: comment

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Change in flashrom[master]: ichspi: Rename HSFC FDBC offset macros
by Subrata Banik (Code Review) 07 Apr '22

07 Apr '22

Attention is currently required from: Subrata Banik, Nico Huber, Angel Pons, Anastasia Klimchuk. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/62894 ) Change subject: ichspi: Rename HSFC FDBC offset macros ...................................................................... Patch Set 7: (1 comment) File ichspi.c: https://review.coreboot.org/c/flashrom/+/62894/comment/58120775_07bce834 PS4, Line 508: FDBC > > `HSFC_FDBC_MASK` exists but there is no macro to resolve this symbol `HSFC_FDBC_MASK_OFF` […] Ack -- To view, visit https://review.coreboot.org/c/flashrom/+/62894 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Ia0ae9a586b5c12f0229334898426175ec246a70c Gerrit-Change-Number: 62894 Gerrit-PatchSet: 7 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Subrata Banik <subi.banik(a)gmail.com> Gerrit-Attention: Subrata Banik <subi.banik(a)gmail.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Comment-Date: Thu, 07 Apr 2022 20:12:07 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subi.banik(a)gmail.com> Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-MessageType: comment

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