Felix Singer has uploaded a new patch set (#2). ( https://review.coreboot.org/c/flashrom/+/63487 )
Change subject: hwaccess: use __asm__ as it is done elsewhere
......................................................................
hwaccess: use __asm__ as it is done elsewhere
`asm()` is glibc specific. Thus, use `__asm__` as it is done elsewhere and
fix compilation under non glibc, such as musl.
Change-Id: I834fa6e171d2b20e1a5faa5a2e8f54caf107171a
Signed-off-by: Rosen Penev <rosenp(a)gmail.com>
Signed-off-by: Felix Singer <felixsinger(a)posteo.net>
---
M hwaccess_physmap.c
1 file changed, 3 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/87/63487/2
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Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/63487 )
Change subject: hwaccess: use __asm__ as it is done elsewhere
......................................................................
hwaccess: use __asm__ as it is done elsewhere
`asm()` is glibc specific. Thus, use `__asm__` as it is done elsewhere and
fix compilation under non glibc, such as musl.
Signed-off-by: Rosen Penev <rosenp(a)gmail.com>
Signed-off-by: Felix Singer <felixsinger(a)posteo.net>
Change-Id: I834fa6e171d2b20e1a5faa5a2e8f54caf107171a
---
M hwaccess_physmap.c
1 file changed, 3 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/87/63487/1
diff --git a/hwaccess_physmap.c b/hwaccess_physmap.c
index b1b9c64..880d6ce 100644
--- a/hwaccess_physmap.c
+++ b/hwaccess_physmap.c
@@ -382,18 +382,18 @@
#if defined(__powerpc) || defined(__powerpc__) || defined(__powerpc64__) || defined(__POWERPC__) || \
defined(__ppc__) || defined(__ppc64__) || defined(_M_PPC) || defined(_ARCH_PPC) || \
defined(_ARCH_PPC64) || defined(__ppc)
- asm("eieio" : : : "memory");
+ __asm__("eieio" : : : "memory");
#elif (__sparc__) || defined (__sparc)
#if defined(__sparc_v9__) || defined(__sparcv9)
/* Sparc V9 CPUs support three different memory orderings that range from x86-like TSO to PowerPC-like
* RMO. The modes can be switched at runtime thus to make sure we maintain the right order of access we
* use the strongest hardware memory barriers that exist on Sparc V9. */
- asm volatile ("membar #Sync" ::: "memory");
+ __asm__ volatile ("membar #Sync" ::: "memory");
#elif defined(__sparc_v8__) || defined(__sparcv8)
/* On SPARC V8 there is no RMO just PSO and that does not apply to I/O accesses... but if V8 code is run
* on V9 CPUs it might apply... or not... we issue a write barrier anyway. That's the most suitable
* operation in the V8 instruction set anyway. If you know better then please tell us. */
- asm volatile ("stbar");
+ __asm__ volatile ("stbar");
#else
#error Unknown and/or unsupported SPARC instruction set version detected.
#endif
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Anastasia Klimchuk has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/62320 )
Change subject: tests/: Add file path and flags validation to open() calls
......................................................................
Patch Set 14:
(2 comments)
File tests/chip.c:
https://review.coreboot.org/c/flashrom/+/62320/comment/311bd758_ccbea199
PS14, Line 201: io_mock_register(&chip_io);
`io_mock_register(&chip_io)` can be moved into `setup_chip`. That would need one more argument for setup_chip, to pass chip_io, because it is not exactly the same for all tests. But at least registration (and de-registration) can be moved to a common place, setup/teardown.
https://review.coreboot.org/c/flashrom/+/62320/comment/f1c26173_6f82bffc
PS14, Line 216: io_mock_register(NULL);
`io_mock_register(NULL)` can be moved into `teardown` because it just repeats at the end of each test.
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Edward O'Callaghan has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/62768 )
Change subject: flashrom.8.tmpl: Add raiden_debug_spi doc entry
......................................................................
Patch Set 1:
(9 comments)
File flashrom.8.tmpl:
https://review.coreboot.org/c/flashrom/+/62768/comment/c28427cb_ce7e20eb
PS1, Line 361: .BR "* raiden_debug_spi" " (for SPI flash ROMs attached to a ChromiumOS servo debug board)"
> Servo V2 (and maybe V3, which I think is completely obsolete now) uses the FTDI code. […]
Done
https://review.coreboot.org/c/flashrom/+/62768/comment/d974a0b8_9bf34244
PS1, Line 361: .BR "* raiden_debug_spi" " (for SPI flash ROMs attached to a ChromiumOS servo debug board)"
> Servo V2 (and maybe V3, which I think is completely obsolete now) uses the FTDI code. […]
Done
https://review.coreboot.org/c/flashrom/+/62768/comment/7c648447_9bc335a2
PS1, Line 1137: syntax
> Add a comma after syntax
Done
https://review.coreboot.org/c/flashrom/+/62768/comment/9fcda2ec_49b72792
PS1, Line 1137: syntax
> Add a comma after syntax
Done
https://review.coreboot.org/c/flashrom/+/62768/comment/50970470_51e21226
PS1, Line 1143: servo serial to use
> Clarify whether this is by the serial number of the board or a uart: /dev/tty […]
Done
https://review.coreboot.org/c/flashrom/+/62768/comment/9706e5d0_30159c3b
PS1, Line 1147: syntax.
> This sounds wrong here. […]
Done
https://review.coreboot.org/c/flashrom/+/62768/comment/8b06b089_b3c21eda
PS1, Line 1147: syntax.
> This sounds wrong here. […]
Done
https://review.coreboot.org/c/flashrom/+/62768/comment/19834387_a0808d6d
PS1, Line 1154: custom_rst=(true,false)
> I suggest using this scheme, since it is very common I think. […]
Done
https://review.coreboot.org/c/flashrom/+/62768/comment/b5083811_67a9a393
PS1, Line 1154: custom_rst=(true,false)
> I suggest using this scheme, since it is very common I think. […]
Done
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Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/62768 )
Change subject: flashrom.8.tmpl: Add raiden_debug_spi doc entry
......................................................................
Patch Set 1:
(3 comments)
File flashrom.8.tmpl:
https://review.coreboot.org/c/flashrom/+/62768/comment/e9abd0f8_6ae729e3
PS1, Line 319: Currently supported are
> This is of course not for this patch, but is there any reason programmers are not in alphabetical or […]
I was thinking the same thing. Both here and in the flashrom list itself.
https://review.coreboot.org/c/flashrom/+/62768/comment/3d8f208e_386a6e1a
PS1, Line 361: .BR "* raiden_debug_spi" " (for SPI flash ROMs attached to a ChromiumOS servo debug board)"
> ft2232_spi also works with Servo. I guess it's about the version? Also, […]
Servo V2 (and maybe V3, which I think is completely obsolete now) uses the FTDI code. For some firmware engineers, the servo V2 is still the preferred flashing method because it's significantly faster than any of the debug tools using the Raiden driver.
SuzyQable, Servo V4, uServo, and C2D2 debug tools all use the Raiden driver as they're all based on the Chrome EC codebase in one way or another.
Maybe:
"* raiden_debug_spi" " (For Chrome EC based debug tools - SuzyQable, Servo V4, C2D2 & uServo)
https://review.coreboot.org/c/flashrom/+/62768/comment/2d24c299_1159d7a7
PS1, Line 1143: servo serial to use
Clarify whether this is by the serial number of the board or a uart: /dev/tty
Add instructions on how to figure out which servo is which.
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Sergii Dmytruk has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/56023 )
Change subject: board_enable.c: Add ME unlock function for Clevo laptops
......................................................................
Patch Set 15:
(1 comment)
File board_enable.c:
https://review.coreboot.org/c/flashrom/+/56023/comment/af4b7f1d_93564f18
PS2, Line 2339: return 0;
> That would be one of the little changes, e.g. make calling
> register_shutdown() optional, then the tool would have to call
> pcidev_shutdown() directly.
Except that it's used four times in the file and there is also one use of extract_programmer_param(). These need to not be mentioned at all in order to get rid of the symbols in object files. And then there is invocation of print() from libflashrom.c, which in turn depends on flashrom.c...
That said, you're welcome to give it a try :) or suggest alternatives. We might also choose to write a completely standalone tool for unlocking if all our attempts here fail.
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Felix Held has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/63422 )
Change subject: sb600spi.c: Use SPI100 bit mappings
......................................................................
Patch Set 2:
(1 comment)
File sb600spi.c:
https://review.coreboot.org/c/flashrom/+/63422/comment/5ff704c5_80c12a27
PS1, Line 574: promontory_read_memmapped(
> So this hack was added because reading using SPI commands is very slow compared to using the mmap. […]
since this is also in the public version of the cezanne ppr, i'll just paste it here:
The SPI configuration registers are accessed through SPI base address specified by FCH::LPCPCICFG::spi_base_addr. Software can communicate with the SPI ROM through the default memory or an alternate programming (a.k.a "Indexed mode") method:
• Memory access to the BIOS ROM address space is automatically handled by the hardware. The SPI ROM controller translates the memory address onto the SPI bus and accesses the SPI ROM data. Any other commands besides memory read or memory write to the SPI ROM need to go through the alternate programming (a.k.a "Indexed mode") method. SPI ROM access through the memory address is limited to a 24-bit address (16MB addressable space).
• With the alternate programming (a.k.a "Indexed mode") method, software needs to program the SpiOpCode, SpiAddress, TxByteCount, RxByteCount, put the data into the transmit FIFO, and then execute the command. The hardware communicates with the SPI ROM using these parameters. This alternate programming (a.k.a "Indexed mode") method basically allows software to issue any flash vendor specific commands such as ERASE and STATUS. The alternate programming method can generate up to 32-bit addresses, but transfers are limited to "normal" (1-bit) mode.
i read from that that the indirect access is always in normal spi mode and only the memory mapped reads will use the dual or quad mode. for reads the interface speed is the limiting factor. the prefetching might be another factor. the mmio access is however limited to 16MByte of flash; unsure how this will behave when using 32 bit flash chips
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