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Hello build bot (Jenkins), Robert Zieba, Raul Rangel, Jon Murphy, Edward O'Callaghan, Felix Held,
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#3).
Change subject: sb600spi.c: Use SPI100 bit mappings
......................................................................
sb600spi.c: Use SPI100 bit mappings
On AMD SoCs that use SPI100 engine, flashrom has been using legacy
spi100 register and bit mappings when programming the engine -
specifically when programming the opcode and triggering their execution.
---------------------------------------------------------------------
| Register Name | Legacy SPI100 mapping | Updated SPI100 mapping |
|---------------|------------------------|--------------------------|
| Opcode | Offset 0 from SPI BAR | Offset 0x45 from SPI BAR |
| | Bits 0:7 | Bits 0:7 |
|---------------|------------------------|--------------------------|
| Execute Cmd | Offset 2 from SPI BAR | Offset 0x47 from SPI BAR |
| | Bit 1 | Bit 7 |
---------------------------------------------------------------------
These legacy register mappings are removed in upcoming generations of
AMD SoCs. Stop using the legacy spi100 registers. For more details about
SPI100 refer to document: 56569-A1 Rev 3.01
BUG=b:228238107
TEST=Build and deploy flashrom in Skyrim. Ensure that flashrom is able
to detect the SPI ROM chip, read from it and write to it successfully.
Ran flashrom_tester on Dewatt (Cezanne SoC), Dalboz (Picasso SoC)
successfully and ensured that all the tests passed.
Change-Id: If42130757331f4294b5a42c848557d3287f24fc3
Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com>
---
M sb600spi.c
1 file changed, 16 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/22/63422/3
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Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/flashrom/+/63416
to look at the new patch set (#2).
Change subject: [WIP] add me_unlock_tool
......................................................................
[WIP] add me_unlock_tool
This is an alternative take on CB:56023 that implement ME unlocking
in a separate tool. The only problem is: it links to a half of flashrom
sources... Another issue is creation of a fake programmer for
register_shutdown() to work.
With the current state of the codebase, it's virtually impossible to do
better. Check SVG file in the commit for a graph depicting
import/export of function symbols from a subset of object files used by
this tool.
Change-Id: Ie8d66f1ee449ce8f2cbdc8c744e9b70428de533d
Signed-off-by: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com>
---
M .gitignore
M Makefile
M board_enable.c
M ichspi.c
M programmer.h
A util/me_unlock_tool/Makefile
A util/me_unlock_tool/call-deps.svg
A util/me_unlock_tool/me_unlock_tool.c
A util/me_unlock_tool/meson.build
M util/meson.build
10 files changed, 2,345 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/16/63416/2
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Felix Held has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/63423 )
Change subject: sb600spi.c: Add Promontory chipset rev 0x71
......................................................................
Patch Set 2: Code-Review+2
(1 comment)
Patchset:
PS2:
the whole detection logic should probably be reworked in the future, but for now adding the new revision id should be fine. i'd expect that we don't need to look at the smbus pci revision id at all for the lpc pci device with the device id 0x790e, since all of those will have the spi100 engine. right now i'd assume that we only need to distinguish between the pre-spi100 and spi100 engine
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Felix Held has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/63422 )
Change subject: sb600spi.c: Use SPI100 bit mappings
......................................................................
Patch Set 2:
(1 comment)
Commit Message:
https://review.coreboot.org/c/flashrom/+/63422/comment/5e238592_0584f7af
PS2, Line 21: deprecated
from looking at the PPRs i'd say that the legacy mappings were already deprecated in picasso and cezanne. on sabrina the legacy mappings have been removed, so flashrom won't work on those chips which this commit fixes
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Thomas Heijligen has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/62405 )
Change subject: board_enable.c: Port to use pcidev_find_vendorclass() helper
......................................................................
Patch Set 3: Code-Review+2
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Thomas Heijligen has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/58561 )
Change subject: Add -W options from Makefile into meson warning_flags
......................................................................
Patch Set 2: Code-Review+1
(2 comments)
Patchset:
PS2:
> My next steps are to sync optimisation option and Werror. […]
Maybe we can combine Werror with the buildtype?
PS2:
Meson has build-in support for warnings. Maybe it's better to use them.
*Consider using the built-in warning_level option instead of using "-Wall"*
*Consider using the built-in warning_level option instead of using "-Wextra"*
https://mesonbuild.com/Builtin-options.html
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Change subject: hwaccess: use __asm__ as it is done elsewhere
......................................................................
Patch Set 4:
(1 comment)
Patchset:
PS4:
> Sounds like it, yes
unresolved
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Change subject: hwaccess: use __asm__ as it is done elsewhere
......................................................................
Patch Set 4:
(1 comment)
Patchset:
PS4:
> I think it's more a gcc thing than glibc thing. […]
Sounds like it, yes
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