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Change subject: hwaccess_x86_io: clean header concept
......................................................................
Patch Set 13:
(1 comment)
File hwaccess_x86_io.c:
https://review.coreboot.org/c/flashrom/+/61276/comment/deb8fa09_3bd989fd
PS13, Line 63: #define IO_PORT_PERMISSION USE_IOPL
> I've may lost this on the way. […]
This restores an error introduced in CB:58278 __linux__ is also true on Android
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Change subject: Makefile: print version info as part of the config target
......................................................................
Patch Set 4:
(1 comment)
File Makefile:
https://review.coreboot.org/c/flashrom/+/62199/comment/f9669bb1_90f6c7cc
PS2, Line 899: PROGRAM
> Dunno, it seems odd. I would just leave it as is. To me $(PROGRAM) is […]
Done
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Hello Felix Singer, build bot (Jenkins), Nico Huber,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/flashrom/+/62199
to look at the new patch set (#4).
Change subject: Makefile: print version info as part of the config target
......................................................................
Makefile: print version info as part of the config target
Change-Id: I1a846acfd8d2e0a9fc8b02c078b6ac0342438490
Signed-off-by: Thomas Heijligen <thomas.heijligen(a)secunet.com>
---
M Makefile
1 file changed, 1 insertion(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/99/62199/4
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Nikolai Artemiev has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/58483 )
Change subject: writeprotect: add {get,set}_wp_mode()
......................................................................
Patch Set 52:
(1 comment)
File writeprotect.c:
https://review.coreboot.org/c/flashrom/+/58483/comment/0af1ab16_7ce2651a
PS25, Line 437: }
> I wonder if it's a good idea to have SRP bits in an array. The intention […]
Yeah, I don't think we'll have to handle more than 2 bits and so the array isn't really necessary.
Personally I'd prefer `srp` over `hwwp` since I've seen `hwwp` used to refer to a few different things in various contexts.
Maybe we can go with srp/srl (status register protect/lock) like some Winbond chips or just srp0/srp1?
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Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/62251 )
Change subject: ichspi: Add Alder Lake support
......................................................................
Patch Set 10:
(1 comment)
File ich_descriptors.c:
https://review.coreboot.org/c/flashrom/+/62251/comment/e9db1c2e_19a97411
PS8, Line 76: case CHIPSET_600_SERIES_ALDER_POINT:
> > I think 500 is perhaps missing here? […]
Alright, thanks for the clarification. Let me know if a patch is made to address this.
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Change subject: ichspi: Add Alder Lake support
......................................................................
Patch Set 10:
(1 comment)
File chipset_enable.c:
https://review.coreboot.org/c/flashrom/+/62251/comment/e452def1_15feae97
PS10, Line 2154: {0x8086, 0x7aa4, B_S, DEP, "Intel", "Alder Lake-S", enable_flash_pch600},
Have all three PCH types been tested?
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Change subject: ichspi: Add Alder Lake support
......................................................................
Patch Set 10:
(1 comment)
File chipset_enable.c:
https://review.coreboot.org/c/flashrom/+/62251/comment/cf0a7c34_fd099a83
PS10, Line 2152:
> one tab less may be ?
Looks like it's aligned properly on my computer.
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