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Change subject: ichspi: Add Jasper Lake support
......................................................................
Set Ready For Review
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Edward O'Callaghan has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/62251 )
Change subject: ichspi: Add Alder Lake support
......................................................................
Patch Set 11:
(1 comment)
File chipset_enable.c:
https://review.coreboot.org/c/flashrom/+/62251/comment/38cc5cef_2144383c
PS10, Line 2154: {0x8086, 0x7aa4, B_S, DEP, "Intel", "Alder Lake-S", enable_flash_pch600},
> > Have all three PCH types been tested? […]
Done. Brya was tested and Nissa we are waiting on partners to return results.
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Hello Sam McNally, build bot (Jenkins), Subrata Banik, Rizwan Qureshi,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/flashrom/+/62251
to look at the new patch set (#11).
Change subject: ichspi: Add Alder Lake support
......................................................................
ichspi: Add Alder Lake support
Does exactly what it says on the tin.
BUG=b:220799648
TEST=```localhost ~ # flashrom --flash-name
<snip>
Found Programmer flash chip "Opaque flash chip" (32768 kB, Programmer-specific) mapped at physical address 0x0000000000000000.
vendor="Programmer" name="Opaque flash chip"
```
Tested on Brya.
Change-Id: Ie66cf519df13f3391c41f5016b16a81ef3dfd4bf
Signed-off-by: Edward O'Callaghan <quasisec(a)google.com>
---
M chipset_enable.c
M ich_descriptors.c
M ichspi.c
M programmer.h
M util/ich_descriptors_tool/ich_descriptors_tool.c
5 files changed, 32 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/51/62251/11
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Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/62251 )
Change subject: ichspi: Add Alder Lake support
......................................................................
Patch Set 10:
(2 comments)
File chipset_enable.c:
https://review.coreboot.org/c/flashrom/+/62251/comment/59c7d63d_3d86031b
PS10, Line 2152:
> Looks like it's aligned properly on my computer.
Ack
https://review.coreboot.org/c/flashrom/+/62251/comment/bdd3f62a_fecc33ca
PS10, Line 2154: {0x8086, 0x7aa4, B_S, DEP, "Intel", "Alder Lake-S", enable_flash_pch600},
> Have all three PCH types been tested?
I think we can drop ADL-S, I will pick the task of removing ADL-S from common code and SoC code if any.
for ADL-P, we have Brya and for ADL-N, we have Nissa to test on.
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Hello build bot (Jenkins), Nico Huber, Edward O'Callaghan, Angel Pons, Anastasia Klimchuk, Sergii Dmytruk,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/flashrom/+/58478
to look at the new patch set (#35).
Change subject: writeprotect.h: add structure to represent chip wp configuration bits
......................................................................
writeprotect.h: add structure to represent chip wp configuration bits
Add `struct wp_bits` for representing values of all WP bits in a chip's
status/config register(s).
It allows most WP code to store and manipulate a chip's configuration
without knowing the exact layout of bits in the chip's status registers.
Supporting other chips may require additional fields to be added to the
structure.
BUG=b:195381327,b:153800563
BRANCH=none
TEST=flashrom --wp-{enable,disable,range,list,status} at end of patch series
Change-Id: I17dee630248ce7b51e624a6e46d7097d5d0de809
Signed-off-by: Nikolai Artemiev <nartemiev(a)google.com>
---
M writeprotect.h
1 file changed, 36 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/78/58478/35
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Hello build bot (Jenkins), Nico Huber, Edward O'Callaghan, Angel Pons, Anastasia Klimchuk, Sergii Dmytruk,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/flashrom/+/58479
to look at the new patch set (#39).
Change subject: libflashrom,writeprotect: add functions for reading/writing WP configs
......................................................................
libflashrom,writeprotect: add functions for reading/writing WP configs
New functions are exposed through the libflashrom API for
reading/writing chip's WP settins: `flashrom_wp_{read,write}_cfg()`.
They read/write an opaque `struct flashrom_wp_cfg` instance, which
includes the flash protection range and status register protection mode.
This commit also adds `{read,write}_wp_bits()` helper functions that
read/write chip-specific WP configuration bits.
BUG=b:195381327,b:153800563
BRANCH=none
TEST=flashrom --wp-{enable,disable,range,list,status} at end of patch series
Change-Id: I3ad25708c3321b8fb0216c3eaf6ffc07616537ad
Signed-off-by: Nikolai Artemiev <nartemiev(a)google.com>
---
M flashchips.c
M libflashrom.c
M libflashrom.h
M writeprotect.c
M writeprotect.h
5 files changed, 364 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/79/58479/39
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Hello build bot (Jenkins), Nico Huber, Edward O'Callaghan, Angel Pons, Anastasia Klimchuk, Sergii Dmytruk,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/flashrom/+/58478
to look at the new patch set (#34).
Change subject: writeprotect.h: add structure to represent chip wp configuration bits
......................................................................
writeprotect.h: add structure to represent chip wp configuration bits
Add `struct wp_bits` for representing values of all WP bits in a chip's
status/config register(s).
It allows most WP code to store and manipulate a chip's configuration
without knowing the exact layout of bits in the chip's status registers.
Supporting other chips may require additional fields to be added to the
structure.
BUG=b:195381327,b:153800563
BRANCH=none
TEST=flashrom --wp-{enable,disable,range,list,status} at end of patch series
Change-Id: I17dee630248ce7b51e624a6e46d7097d5d0de809
Signed-off-by: Nikolai Artemiev <nartemiev(a)google.com>
---
M writeprotect.h
1 file changed, 40 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/78/58478/34
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