Attention is currently required from: Nico Huber, Edward O'Callaghan.
Nikolai Artemiev has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/69195 )
Change subject: ichspi.c: Read chip ID and use it to populate `flash->chip`
......................................................................
Patch Set 13:
(6 comments)
File ichspi.c:
https://review.coreboot.org/c/flashrom/+/69195/comment/69c88667_1e98379d
PS12, Line 1500: flash->chip->tested = TEST_OK_PREWB;
> What if ich_hwseq_get_flash_id() bailed?
Done
https://review.coreboot.org/c/flashrom/+/69195/comment/56764021_52c2054c
PS12, Line 135: #define HSFC_CYCLE_RDID HSFC_FCYCLE_MASK(6)
> My dyslexic brain can hardly keep track of all this pre-processor nonsense going on here but this al […]
Unresolving so I don't forget this.
https://review.coreboot.org/c/flashrom/+/69195/comment/73a14ecd_0f74a675
PS12, Line 1404: if ((chip->manufacture_id == mfg_id) && (chip->model_id == model_id))
> Should check if it's a SPI flash and if the database numbers are for RDID.
Done
https://review.coreboot.org/c/flashrom/+/69195/comment/040b2a42_8ec62e87
PS12, Line 1466: const int len = sizeof(data);
> Why 4?
Done
https://review.coreboot.org/c/flashrom/+/69195/comment/961eeae5_6eebfe46
PS12, Line 1474: if (ich_exec_sync_hwseq_xfer(flash, HSFC_CYCLE_RDID, 1, len, ich_generation,
> Should check if RDID cycle is supported (since PCH100).
Unresolving so I don't forget this.
https://review.coreboot.org/c/flashrom/+/69195/comment/f62fda05_9aa0771b
PS12, Line 1494: return -1;
> Does this break normal read/erase/write operation if there is no matching entry?
Done
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Hello build bot (Jenkins), Subrata Banik, Edward O'Callaghan, Angel Pons,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/flashrom/+/69195
to look at the new patch set (#13).
Change subject: ichspi.c: Read chip ID and use it to populate `flash->chip`
......................................................................
ichspi.c: Read chip ID and use it to populate `flash->chip`
Read the flash chip vendor/device ID using hardware sequencing, find the
corresponding flashchip entry, and copy it over to `flash->chip`.
Identifying the chip was not previously required as ICH hardware
sequencing handles chip-level details related to read/write/erase ops.
However writeprotect operations require the chip entry to be identified
so that chip->reg_bits can be used to compute status register values.
BUG=b:253715389,b:253713774
BRANCH=none
TEST=flashrom on dedede (JSL) identifies "W25Q128.V..M" chip
TEST=flashrom -{r,v} on dedede
TEST=write/erase bios region on dedede:
flashrom -{E,w} --layout <(echo '0x381000:0xffffff bios') -i bios
Change-Id: Ia408e1e45dc6f53c0934afd6558e301abfa48ee6
Signed-off-by: Nikolai Artemiev <nartemiev(a)google.com>
---
M ichspi.c
1 file changed, 95 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/95/69195/13
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Nikolai Artemiev has uploaded a new patch set (#8) to the change originally created by Edward O'Callaghan. ( https://review.coreboot.org/c/flashrom/+/69517 )
Change subject: flashrom.c: Supplement `chip->unlock()` calls with wp unlocking
......................................................................
flashrom.c: Supplement `chip->unlock()` calls with wp unlocking
The full writeprotect implementation has proper support and
ability to unlock flash over spi25_statusreg.c. Therefore if
the required bits are available for the given chip prefer
proper writeprotect support instead of adhoc spi25_statusreg.c
helpers.
BUG=b:237485865
BRANCH=none
TEST=Tested on grunt DUT (prog: sb600spi, flash: W25Q128.W):
`flashrom --wp-range 0x0,0x1000000 \
flashrom --wp-status # Result: range=0x0,0x1000000 \
flashrom -w random.bin # Result: success \
flashrom -v random.bin # Result: success \
flashrom --wp-status # Result: range=0x0,0x1000000`
TEST=Tested that chips without WP support can still be unlocked
by deleting decode_range for W25Q128.W flashchip and
retesting on the grunt DUT.
Change-Id: I74b3f5d3a17749ea60485b916b2d87467a5d8b2f
CoAuthored-by: Nikolai Artemiev <nartemiev(a)google.com>
Signed-off-by: Nikolai Artemiev <nartemiev(a)google.com>
Signed-off-by: Edward O'Callaghan <quasisec(a)google.com>
---
M flashrom.c
1 file changed, 79 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/17/69517/8
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Hello build bot (Jenkins), Edward O'Callaghan, Sergii Dmytruk,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/flashrom/+/70349
to look at the new patch set (#5).
Change subject: tree/: Change chip restore data type from uint8_t to void ptr
......................................................................
tree/: Change chip restore data type from uint8_t to void ptr
Chip restore callbacks currently are used by
- spi25_statusreg.c unlock functions to restore status register 1.
- s25f.c to restore config register 3.
Both of these cases only need to save a single uint8_t value to restore
the original chip state, however storing a void pointer will allow more
flexible chip restore behaviour. In particular, it will allow
flashrom_wp_cfg objects to be saved and restored, enabling
writeprotect-based unlocking.
BUG=b:237485865,b:247421511
BRANCH=none
TEST=Tested on grunt DUT (prog: sb600spi, flash: W25Q128.W):
`flashrom --wp-range 0x0,0x1000000 \
flashrom --wp-status # Result: range=0x0,0x1000000 \
flashrom -w random.bin # Result: success \
flashrom -v random.bin # Result: success \
flashrom --wp-status # Result: range=0x0,0x1000000`
Change-Id: I311b468a4b0349f4da9584c12b36af6ec2394527
Signed-off-by: Nikolai Artemiev <nartemiev(a)google.com>
---
M flashrom.c
M include/flash.h
M s25f.c
M spi25_statusreg.c
4 files changed, 57 insertions(+), 10 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/49/70349/5
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Edward O'Callaghan has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/69195 )
Change subject: ichspi.c: Read chip ID and use it to populate `flash->chip`
......................................................................
Patch Set 12:
(1 comment)
File ichspi.c:
https://review.coreboot.org/c/flashrom/+/69195/comment/5ee81b33_927ba6b4
PS12, Line 135: #define HSFC_CYCLE_RDID HSFC_FCYCLE_MASK(6)
> This belongs to PCH100_HSFC_FCYCLE*. It doesn't fit in the 2 bits for ICH9. […]
My dyslexic brain can hardly keep track of all this pre-processor nonsense going on here but this all looks very suspicious to me;
```
/* Changed HSFC Control bits */
/*
* 4 bits to represents the FCYCLE operation for PCH as:
* 0: SPI Read
* 2: SPI Write
* 3: SPI Erase 4K
* 4: SPI Erase 64K
* 6: SPI RDID
* 7: SPI Write Status
* 8: SPI Read Status
*/
#define PCH100_HSFC_FCYCLE_BIT_WIDTH 0xf
[..]
#define PCH100_HSFC_FCYCLE HSFC_FCYCLE_MASK(PCH100_HSFC_FCYCLE_BIT_WIDTH)
[..]
/*
* 2 bits to represents the FCYCLE operation for ICH9 as:
* 0: SPI Read
* 2: SPI Write
* 3: SPI Block Erase
*/
#define ICH9_HSFC_FCYCLE_BIT_WIDTH 3
#define HSFC_FCYCLE_OFF 1 /* 1-2: FLASH Cycle */
#define HSFC_FCYCLE_MASK(n) ((n) << HSFC_FCYCLE_OFF)
#define HSFC_FCYCLE HSFC_FCYCLE_MASK(ICH9_HSFC_FCYCLE_BIT_WIDTH)
```
At minimum `HSFC_FCYCLE` seems like it should be called `ICH9_HSFC_FCYCLE`, the definitions of `HSFC_FCYCLE_MASK(n) && HSFC_FCYCLE_OFF` moved up? The nomenclature is completely jumbled up as well as the ordering and the two sets of comments for FCYCLE are confusing in their current form.
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Edward O'Callaghan has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/70006 )
Change subject: layout: Check return values for strdup in register_include_arg
......................................................................
Patch Set 5:
(1 comment)
File layout.c:
https://review.coreboot.org/c/flashrom/+/70006/comment/52ae100b_e51cfcea
PS5, Line 134: colon - arg
`if (colon && !colon[1]) {` is no longer checked before this operation.
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Edward O'Callaghan has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/70006 )
Change subject: layout: Check return values for strdup in register_include_arg
......................................................................
Patch Set 5:
(3 comments)
Commit Message:
https://review.coreboot.org/c/flashrom/+/70006/comment/f36b5b30_3c2d576b
PS5, Line 9: strdup return values should be checked for NULL to catch the
: potential error case of out of memory.
This patch does more than this. It refactors, if you are going to do this I suggest splitting the patch into perhaps two patches.
The first should factor out all this C-typical string parsing hand grenade type stuff into its own static function.
The second patch can refactor the inadequate error handling of ternary operators acting on heap allocating functions. Also if you are going to unroll the ternary operators, do all of them to make the function procedurally obvious.
File layout.c:
https://review.coreboot.org/c/flashrom/+/70006/comment/40111dcb_a81f9fde
PS5, Line 136: Could not allocate memory
CB:69472
https://review.coreboot.org/c/flashrom/+/70006/comment/e65aa596_442440a1
PS5, Line 149: Could not allocate memory\
CB:69472
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Evan Benn has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/69770 )
Change subject: test_build.sh: Add build_rust
......................................................................
Patch Set 2:
(2 comments)
File test_build.sh:
https://review.coreboot.org/c/flashrom/+/69770/comment/9e3df2bb_0aba3378
PS1, Line 87: do_for_rust test --offline
> this is not great as a user that has cargo but hasnt run this before needs to manually run the same […]
Discussed with felix on irc, felix pointed out that rust doesnt go online if things are in the cache anyway. So this will work the same with or without --offline.
https://review.coreboot.org/c/flashrom/+/69770/comment/ba29e975_9ae407a1
PS1, Line 94: hash cargo && build_rust
> when jenkins has cargo I would make this […]
Done
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Evan Benn has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/69268 )
Change subject: tests: Add llvm-cov option and run target for code coverage
......................................................................
Patch Set 14:
(2 comments)
Commit Message:
https://review.coreboot.org/c/flashrom/+/69268/comment/bfeace61_dcfba292
PS11, Line 14: TEST=meson test; ninja llvm-cov-tests
> I meant to say, test scenario == "build flashrom and run tests with coverage disabled" […]
yes I also ran without coverage (and so does jenkins! V+1)
File meson.build:
https://review.coreboot.org/c/flashrom/+/69268/comment/5bb531b2_b1ceb172
PS14, Line 625: run_target('llvm-cov-cli', command : ['scripts/llvm-cov', classic_cli])
> But why this is always run? It should only run when feature is enabled?
This is declaring a run target, its not running anything. It can go inside a feature if, it will be less confusing to a user inspecting the ninja run targets. thanks
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Hello build bot (Jenkins), Thomas Heijligen, Edward O'Callaghan, Anastasia Klimchuk,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/flashrom/+/69268
to look at the new patch set (#15).
Change subject: tests: Add llvm-cov option and run target for code coverage
......................................................................
tests: Add llvm-cov option and run target for code coverage
Code coverage can be requested with -Dllvm_cov and run with ninja
llvm-cov-tests or llvm-cov-cli.
BUG=b:187647884
BRANCH=None
TEST=meson test; ninja llvm-cov-tests
TEST=ran test_build.sh with coverage enabled
Change-Id: Id6c73bff46e7b88d425956a80def97082b201f56
Signed-off-by: Evan Benn <evanbenn(a)chromium.org>
---
M Documentation/building.md
M meson.build
M meson_options.txt
A scripts/llvm-cov
M tests/meson.build
5 files changed, 45 insertions(+), 9 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/68/69268/15
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