Attention is currently required from: Edward O'Callaghan, Angel Pons, Nikolai Artemiev.
Hello build bot (Jenkins), Edward O'Callaghan,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/flashrom/+/70128
to look at the new patch set (#19).
Change subject: flashrom: Skip read/write/erase/verify ops on inaccessable flash regions
......................................................................
flashrom: Skip read/write/erase/verify ops on inaccessable flash regions
Skip flash regions that get_region() indicates are inaccessable. This
fixes transaction errors due to accessing unreadable flash regions on
Intel platforms with active an CSME coprocessor.
BUG=b:260440773
BRANCH=none
TEST=flashrom -{r,w,E,v} on dedede (JSL)
Change-Id: I9b96fb04b863625d2c9f9a00b97c35b3ddb0871b
CoAuthored-by: Edward O'Callaghan <quasisec(a)google.com>
Signed-off-by: Edward O'Callaghan <quasisec(a)google.com>
Signed-off-by: Nikolai Artemiev <nartemiev(a)google.com>
---
M flashrom.c
M include/flash.h
M include/libflashrom.h
M libflashrom.c
4 files changed, 234 insertions(+), 26 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/28/70128/19
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Edward O'Callaghan has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/69195 )
Change subject: ichspi.c: Read chip ID and use it to populate `flash->chip`
......................................................................
Patch Set 15: Code-Review+2
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Nikolai Artemiev has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/70128 )
Change subject: flashrom: Skip read/write/erase/verify ops on inaccessable flash regions
......................................................................
Patch Set 18:
(1 comment)
File flashrom.c:
https://review.coreboot.org/c/flashrom/+/70128/comment/42c4edbd_8d1e39e5
PS13, Line 348: region->name = strdup("");
> Oh I see the `strdup()` now in the previous patch to which you are referring to. […]
Done
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Hello build bot (Jenkins), Edward O'Callaghan,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/flashrom/+/70128
to look at the new patch set (#18).
Change subject: flashrom: Skip read/write/erase/verify ops on inaccessable flash regions
......................................................................
flashrom: Skip read/write/erase/verify ops on inaccessable flash regions
Skip flash regions that get_region() indicates are inaccessable. This
fixes transaction errors due to accessing unreadable flash regions on
Intel platforms with active an CSME coprocessor.
BUG=b:260440773
BRANCH=none
TEST=flashrom -{r,w,E,v} on dedede (JSL)
Change-Id: I9b96fb04b863625d2c9f9a00b97c35b3ddb0871b
CoAuthored-by: Edward O'Callaghan <quasisec(a)google.com>
Signed-off-by: Edward O'Callaghan <quasisec(a)google.com>
Signed-off-by: Nikolai Artemiev <nartemiev(a)google.com>
---
M flashrom.c
1 file changed, 188 insertions(+), 17 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/28/70128/18
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Nikolai Artemiev has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/69195 )
Change subject: ichspi.c: Read chip ID and use it to populate `flash->chip`
......................................................................
Patch Set 15:
(2 comments)
File ichspi.c:
https://review.coreboot.org/c/flashrom/+/69195/comment/2858ecda_dac79c1f
PS14, Line 144:
> spurious
Done
https://review.coreboot.org/c/flashrom/+/69195/comment/42414cde_5ba1aad8
PS14, Line 1495: ich_generation
> `ich_gen`
Done
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Hello build bot (Jenkins), Subrata Banik, Edward O'Callaghan, Angel Pons,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/flashrom/+/69195
to look at the new patch set (#15).
Change subject: ichspi.c: Read chip ID and use it to populate `flash->chip`
......................................................................
ichspi.c: Read chip ID and use it to populate `flash->chip`
Read the flash chip vendor/device ID using hardware sequencing, find the
corresponding flashchip entry, and copy it over to `flash->chip`.
Identifying the chip was not previously required as ICH hardware
sequencing handles chip-level details related to read/write/erase ops.
However writeprotect operations require the chip entry to be identified
so that chip->reg_bits can be used to compute status register values.
BUG=b:253715389,b:253713774
BRANCH=none
TEST=flashrom on dedede (JSL) identifies "W25Q128.V..M" chip
TEST=flashrom -{r,v} on dedede
TEST=write/erase bios region on dedede:
flashrom -{E,w} --layout <(echo '0x381000:0xffffff bios') -i bios
Change-Id: Ia408e1e45dc6f53c0934afd6558e301abfa48ee6
Signed-off-by: Nikolai Artemiev <nartemiev(a)google.com>
---
M ichspi.c
1 file changed, 101 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/95/69195/15
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Sergii Dmytruk has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/70349 )
Change subject: tree/: Change chip restore data type from uint8_t to void ptr
......................................................................
Patch Set 5:
(2 comments)
File s25f.c:
https://review.coreboot.org/c/flashrom/+/70349/comment/7d564fbe_d30d1833
PS5, Line 295: if (!data)
: return 1;
Second potential place for "out of memory" message.
File spi25_statusreg.c:
https://review.coreboot.org/c/flashrom/+/70349/comment/9cb0f58f_fd5774cd
PS5, Line 313: if (!data)
: return 1;
Should this print "out of memory" message before returning?
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Thomas Heijligen has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/70176 )
Change subject: README: Add information about meson and link build instructions
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
> I am confused by 2 +1s :) Is there anything that you would like to improve here? (especially, Thomas […]
The README is quite unorganized and I don't think just adding stuff makes it bettet. But the new build informations should somehow get in it.
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