October 2022 - flashrom-gerrit

[S] Change in flashrom[master]: board_enable.c: plumb paralle_bus_size into board_enable_flash() helper
by Edward O'Callaghan (Code Review) 23 Oct '22

23 Oct '22

Edward O'Callaghan has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/68674 ) Change subject: board_enable.c: plumb paralle_bus_size into board_enable_flash() helper ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/c/flashrom/+/68674 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I180b047fc07be946cdc5ba93871f9ff4f4c67df4 Gerrit-Change-Number: 68674 Gerrit-PatchSet: 3 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 23 Oct 2022 10:28:01 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in flashrom[master]: flashrom: Rename 'max_rom_decode' to 'g_max_rom_decode'
by Edward O'Callaghan (Code Review) 23 Oct '22

23 Oct '22

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/flashrom/+/68678 to look at the new patch set (#3). Change subject: flashrom: Rename 'max_rom_decode' to 'g_max_rom_decode' ...................................................................... flashrom: Rename 'max_rom_decode' to 'g_max_rom_decode' The next step appears that g_max_rom_decode is a natural fit into the internal.c driver. Apart from 'wbsio_spi.c' not sure what to do there??? Change-Id: I22785fb196c15dea0500b650bfbc4151983d9d0e Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> --- M cli_classic.c M flashrom.c M include/programmer.h M internal.c M parallel.c M wbsio_spi.c 6 files changed, 25 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/78/68678/3 -- To view, visit https://review.coreboot.org/c/flashrom/+/68678 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I22785fb196c15dea0500b650bfbc4151983d9d0e Gerrit-Change-Number: 68678 Gerrit-PatchSet: 3 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Thomas Heijligen <src(a)posteo.de> Gerrit-MessageType: newpatchset

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[S] Change in flashrom[master]: flashrom: Rename 'max_rom_decode' to 'g_max_rom_decode'
by Edward O'Callaghan (Code Review) 23 Oct '22

23 Oct '22

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/flashrom/+/68678 to look at the new patch set (#2). Change subject: flashrom: Rename 'max_rom_decode' to 'g_max_rom_decode' ...................................................................... flashrom: Rename 'max_rom_decode' to 'g_max_rom_decode' The next step appears that g_max_rom_decode is a natural fit into the internal.c driver. Apart from 'wbsio_spi.c' not sure what to do there??? Change-Id: I22785fb196c15dea0500b650bfbc4151983d9d0e Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> --- M cli_classic.c M flashrom.c M include/programmer.h M internal.c M parallel.c M wbsio_spi.c 6 files changed, 25 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/78/68678/2 -- To view, visit https://review.coreboot.org/c/flashrom/+/68678 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I22785fb196c15dea0500b650bfbc4151983d9d0e Gerrit-Change-Number: 68678 Gerrit-PatchSet: 2 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Thomas Heijligen <src(a)posteo.de> Gerrit-MessageType: newpatchset

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[S] Change in flashrom[master]: it87spi: Plumb par bus size into it8705f_write_enable() helper
by Edward O'Callaghan (Code Review) 23 Oct '22

23 Oct '22

Attention is currently required from: Edward O'Callaghan. Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/flashrom/+/68675 to look at the new patch set (#2). Change subject: it87spi: Plumb par bus size into it8705f_write_enable() helper ...................................................................... it87spi: Plumb par bus size into it8705f_write_enable() helper Allow caller to query the parallel bus size. Change-Id: Iec08cb4d56a8ca62f00b0f7323b36f7d2f850e81 Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> --- M board_enable.c M include/programmer.h M internal.c M it87spi.c 4 files changed, 22 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/75/68675/2 -- To view, visit https://review.coreboot.org/c/flashrom/+/68675 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Iec08cb4d56a8ca62f00b0f7323b36f7d2f850e81 Gerrit-Change-Number: 68675 Gerrit-PatchSet: 2 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: newpatchset

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[S] Change in flashrom[master]: flashrom: Rename 'max_rom_decode' to 'g_max_rom_decode'
by Edward O'Callaghan (Code Review) 23 Oct '22

23 Oct '22

Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/68678 ) Change subject: flashrom: Rename 'max_rom_decode' to 'g_max_rom_decode' ...................................................................... flashrom: Rename 'max_rom_decode' to 'g_max_rom_decode' The next step appears that g_max_rom_decode is a natural fit into the internal.c driver. Apart from 'wbsio_spi.c' not sure what to do there??? Change-Id: I22785fb196c15dea0500b650bfbc4151983d9d0e Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> --- M cli_classic.c M flashrom.c M include/programmer.h M internal.c M parallel.c M wbsio_spi.c 6 files changed, 25 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/78/68678/1 diff --git a/cli_classic.c b/cli_classic.c index ad485a2..795335c 100644 --- a/cli_classic.c +++ b/cli_classic.c @@ -567,7 +567,7 @@ */ static bool max_rom_decode_limitexceeded(const struct flashctx *flash, bool force) { - const unsigned int limitexceeded = count_max_decode_exceedings(flash, &max_rom_decode); + const unsigned int limitexceeded = count_max_decode_exceedings(flash, &g_max_rom_decode); if (limitexceeded > 0 && !force) { enum chipbustype commonbuses = flash->mst->buses_supported & flash->chip->bustype; diff --git a/flashrom.c b/flashrom.c index 0f982c9..531cfb7 100644 --- a/flashrom.c +++ b/flashrom.c @@ -43,7 +43,7 @@ * Programmers supporting multiple buses can have differing size limits on * each bus. Store the limits for each bus in a common struct. */ -struct decode_sizes max_rom_decode; +struct decode_sizes g_max_rom_decode; /* If nonzero, used as the start address of bottom-aligned flash. */ unsigned long flashbase; @@ -136,7 +136,7 @@ programmer = prog; /* Initialize all programmer specific data. */ /* Default to unlimited decode sizes. */ - max_rom_decode = (const struct decode_sizes) { + g_max_rom_decode = (const struct decode_sizes) { .parallel = 0xffffffff, .lpc = 0xffffffff, .fwh = 0xffffffff, diff --git a/include/programmer.h b/include/programmer.h index e8f5ccc..22a50c7 100644 --- a/include/programmer.h +++ b/include/programmer.h @@ -285,7 +285,7 @@ /* flashrom.c */ // FIXME: These need to be local, not global -extern struct decode_sizes max_rom_decode; +extern struct decode_sizes g_max_rom_decode; extern bool programmer_may_write; extern unsigned long flashbase; char *extract_programmer_param_str(const struct programmer_cfg *cfg, const char *param_name); diff --git a/internal.c b/internal.c index 7cd3f22..7868a8d 100644 --- a/internal.c +++ b/internal.c @@ -285,7 +285,7 @@ /* try to enable it. Failure IS an option, since not all motherboards * really need this to be done, etc., etc. */ - ret = chipset_flash_enable(cfg, &max_rom_decode); + ret = chipset_flash_enable(cfg, &g_max_rom_decode); if (ret == -2) { msg_perr("WARNING: No chipset found. Flash detection " "will most likely fail.\n"); @@ -296,9 +296,9 @@ #if defined(__i386__) || defined(__x86_64__) /* Probe unconditionally for ITE Super I/O chips. This enables LPC->SPI translation on IT87* and * parallel writes on IT8705F. Also, this handles the manual chip select for Gigabyte's DualBIOS. */ - init_superio_ite(cfg, &max_rom_decode); + init_superio_ite(cfg, &g_max_rom_decode); - if (board_flash_enable(board_vendor, board_model, cb_vendor, cb_model, &max_rom_decode)) { + if (board_flash_enable(board_vendor, board_model, cb_vendor, cb_model, &g_max_rom_decode)) { msg_perr("Aborting to be safe.\n"); ret = 1; goto internal_init_exit; @@ -306,7 +306,7 @@ #endif if (internal_buses_supported & BUS_NONSPI) - register_par_master(&par_master_internal, internal_buses_supported, NULL, max_rom_decode.parallel); + register_par_master(&par_master_internal, internal_buses_supported, NULL, g_max_rom_decode.parallel); /* Report if a non-whitelisted laptop is detected that likely uses a legacy bus. */ if (is_laptop && !laptop_ok) { diff --git a/parallel.c b/parallel.c index 67e70f6..72ef657 100644 --- a/parallel.c +++ b/parallel.c @@ -97,9 +97,9 @@ } if (max_decode_size) - max_rom_decode.parallel = max_decode_size; + g_max_rom_decode.parallel = max_decode_size; else - max_rom_decode.parallel = 0xffffffff; + g_max_rom_decode.parallel = 0xffffffff; rmst.buses_supported = buses; rmst.par = *mst; diff --git a/wbsio_spi.c b/wbsio_spi.c index 1aa8729..379d6f8 100644 --- a/wbsio_spi.c +++ b/wbsio_spi.c @@ -208,7 +208,7 @@ msg_pdbg("%s: Winbond saved on 4 register bits so max chip size is " "1024 kB!\n", __func__); - max_rom_decode.spi = 1024 * 1024; + g_max_rom_decode.spi = 1024 * 1024; struct wbsio_spi_data *data = calloc(1, sizeof(*data)); if (!data) { -- To view, visit https://review.coreboot.org/c/flashrom/+/68678 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I22785fb196c15dea0500b650bfbc4151983d9d0e Gerrit-Change-Number: 68678 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: newchange

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[M] Change in flashrom[master]: par: plumb max_rom_decode into register func
by Edward O'Callaghan (Code Review) 23 Oct '22

23 Oct '22

Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/68677 ) Change subject: par: plumb max_rom_decode into register func ...................................................................... par: plumb max_rom_decode into register func Change-Id: Id4a4ba09ac493a67aedd3897e7cfc1377e12bdbe Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> --- M atahpt.c M atapromise.c M atavia.c M drkaiser.c M dummyflasher.c M gfxnvidia.c M include/programmer.h M internal.c M it8212.c M nic3com.c M nicintel.c M nicnatsemi.c M nicrealtek.c M parallel.c M satamv.c M satasii.c M serprog.c 17 files changed, 32 insertions(+), 26 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/77/68677/1 diff --git a/atahpt.c b/atahpt.c index 89b44c2..53b2c83 100644 --- a/atahpt.c +++ b/atahpt.c @@ -112,7 +112,7 @@ data->flash_access = pci_read_long(dev, REG_FLASH_ACCESS); pci_write_long(dev, REG_FLASH_ACCESS, data->flash_access | BIT_FLASH_ACCESS); - return register_par_master(&par_master_atahpt, BUS_PARALLEL, data); + return register_par_master(&par_master_atahpt, BUS_PARALLEL, data, 0); } const struct programmer_entry programmer_atahpt = { diff --git a/atapromise.c b/atapromise.c index 625eb83..cda3d42 100644 --- a/atapromise.c +++ b/atapromise.c @@ -175,8 +175,7 @@ data->bar = bar; data->rom_size = rom_size; - max_rom_decode.parallel = rom_size; - return register_par_master(&par_master_atapromise, BUS_PARALLEL, data); + return register_par_master(&par_master_atapromise, BUS_PARALLEL, data, rom_size); } const struct programmer_entry programmer_atapromise = { diff --git a/atavia.c b/atavia.c index b392999..b4c05c4 100644 --- a/atavia.c +++ b/atavia.c @@ -182,7 +182,7 @@ return 1; } - return register_par_master(&lpc_master_atavia, BUS_LPC, NULL); + return register_par_master(&lpc_master_atavia, BUS_LPC, NULL, 0); } const struct programmer_entry programmer_atavia = { diff --git a/drkaiser.c b/drkaiser.c index 96f2c99..443d41e 100644 --- a/drkaiser.c +++ b/drkaiser.c @@ -112,9 +112,7 @@ data->flash_access = pci_read_word(dev, PCI_MAGIC_DRKAISER_ADDR); pci_write_word(dev, PCI_MAGIC_DRKAISER_ADDR, PCI_MAGIC_DRKAISER_VALUE); - max_rom_decode.parallel = 128 * 1024; - - return register_par_master(&par_master_drkaiser, BUS_PARALLEL, data); + return register_par_master(&par_master_drkaiser, BUS_PARALLEL, data, 128 * 1024); } const struct programmer_entry programmer_drkaiser = { diff --git a/dummyflasher.c b/dummyflasher.c index 110a88c..2feecd5 100644 --- a/dummyflasher.c +++ b/dummyflasher.c @@ -1415,7 +1415,7 @@ if (dummy_buses_supported & BUS_NONSPI) register_par_master(&par_master_dummyflasher, dummy_buses_supported & BUS_NONSPI, - data); + data, 0); if (dummy_buses_supported & BUS_SPI) register_spi_master(&spi_master_dummyflasher, data); diff --git a/gfxnvidia.c b/gfxnvidia.c index 1d484ea..9ccf1ad 100644 --- a/gfxnvidia.c +++ b/gfxnvidia.c @@ -142,7 +142,7 @@ /* Write/erase doesn't work. */ programmer_may_write = false; - return register_par_master(&par_master_gfxnvidia, BUS_PARALLEL, data); + return register_par_master(&par_master_gfxnvidia, BUS_PARALLEL, data, 0); } const struct programmer_entry programmer_gfxnvidia = { diff --git a/include/programmer.h b/include/programmer.h index 4da7330..e8f5ccc 100644 --- a/include/programmer.h +++ b/include/programmer.h @@ -438,7 +438,7 @@ int (*shutdown)(void *data); void *data; }; -int register_par_master(const struct par_master *mst, const enum chipbustype buses, void *data); +int register_par_master(const struct par_master *mst, const enum chipbustype buses, void *data, uint32_t max_decode_size); /* programmer.c */ void *fallback_map(const char *descr, uintptr_t phys_addr, size_t len); diff --git a/internal.c b/internal.c index 1b3b8b0..7cd3f22 100644 --- a/internal.c +++ b/internal.c @@ -306,7 +306,7 @@ #endif if (internal_buses_supported & BUS_NONSPI) - register_par_master(&par_master_internal, internal_buses_supported, NULL); + register_par_master(&par_master_internal, internal_buses_supported, NULL, max_rom_decode.parallel); /* Report if a non-whitelisted laptop is detected that likely uses a legacy bus. */ if (is_laptop && !laptop_ok) { diff --git a/it8212.c b/it8212.c index 8fe2b59..c4d5075 100644 --- a/it8212.c +++ b/it8212.c @@ -103,8 +103,7 @@ data->decode_access = pci_read_long(dev, PCI_ROM_ADDRESS); pci_write_long(dev, PCI_ROM_ADDRESS, io_base_addr | 0x01); - max_rom_decode.parallel = IT8212_MEMMAP_SIZE; - return register_par_master(&par_master_it8212, BUS_PARALLEL, data); + return register_par_master(&par_master_it8212, BUS_PARALLEL, data, IT8212_MEMMAP_SIZE); } const struct programmer_entry programmer_it8212 = { .name = "it8212", diff --git a/nic3com.c b/nic3com.c index efba979..537fbfe 100644 --- a/nic3com.c +++ b/nic3com.c @@ -148,9 +148,7 @@ data->internal_conf = internal_conf; data->id = id; - max_rom_decode.parallel = 128 * 1024; - - return register_par_master(&par_master_nic3com, BUS_PARALLEL, data); + return register_par_master(&par_master_nic3com, BUS_PARALLEL, data, 128 * 1024); init_err_cleanup_exit: /* 3COM 3C90xB cards need a special fixup. */ diff --git a/nicintel.c b/nicintel.c index 47edbb7..ef806d9 100644 --- a/nicintel.c +++ b/nicintel.c @@ -124,8 +124,7 @@ data->nicintel_bar = bar; data->nicintel_control_bar = control_bar; - max_rom_decode.parallel = NICINTEL_MEMMAP_SIZE; - return register_par_master(&par_master_nicintel, BUS_PARALLEL, data); + return register_par_master(&par_master_nicintel, BUS_PARALLEL, data, NICINTEL_MEMMAP_SIZE); } const struct programmer_entry programmer_nicintel = { diff --git a/nicnatsemi.c b/nicnatsemi.c index efa879a..d291770 100644 --- a/nicnatsemi.c +++ b/nicnatsemi.c @@ -117,8 +117,7 @@ * max_rom_decode.parallel = 65536; and the mask in the read/write * functions below wants to be 0x0000FFFF. */ - max_rom_decode.parallel = 131072; - return register_par_master(&par_master_nicnatsemi, BUS_PARALLEL, data); + return register_par_master(&par_master_nicnatsemi, BUS_PARALLEL, data, 131072); } diff --git a/nicrealtek.c b/nicrealtek.c index 103ea9e..6a41519 100644 --- a/nicrealtek.c +++ b/nicrealtek.c @@ -138,7 +138,7 @@ data->bios_rom_addr = bios_rom_addr; data->bios_rom_data = bios_rom_data; - return register_par_master(&par_master_nicrealtek, BUS_PARALLEL, data); + return register_par_master(&par_master_nicrealtek, BUS_PARALLEL, data, 0); } const struct programmer_entry programmer_nicrealtek = { diff --git a/parallel.c b/parallel.c index e635088..67e70f6 100644 --- a/parallel.c +++ b/parallel.c @@ -65,7 +65,7 @@ int register_par_master(const struct par_master *mst, const enum chipbustype buses, - void *data) + void *data, uint32_t max_decode_size) { struct registered_master rmst = {0}; @@ -96,6 +96,11 @@ return ERROR_FLASHROM_BUG; } + if (max_decode_size) + max_rom_decode.parallel = max_decode_size; + else + max_rom_decode.parallel = 0xffffffff; + rmst.buses_supported = buses; rmst.par = *mst; if (data) diff --git a/satamv.c b/satamv.c index dcd53c7..1a33ee3 100644 --- a/satamv.c +++ b/satamv.c @@ -202,8 +202,7 @@ /* 512 kByte with two 8-bit latches, and * 4 MByte with additional 3-bit latch. */ - max_rom_decode.parallel = 4 * 1024 * 1024; - return register_par_master(&par_master_satamv, BUS_PARALLEL, data); + return register_par_master(&par_master_satamv, BUS_PARALLEL, data, 4 * 1024 * 1024); } const struct programmer_entry programmer_satamv = { diff --git a/satasii.c b/satasii.c index 011562e..5517fd7 100644 --- a/satasii.c +++ b/satasii.c @@ -146,7 +146,7 @@ } data->bar = bar; - return register_par_master(&par_master_satasii, BUS_PARALLEL, data); + return register_par_master(&par_master_satasii, BUS_PARALLEL, data, 0); } const struct programmer_entry programmer_satasii = { .name = "satasii", diff --git a/serprog.c b/serprog.c index a3a3db3..afe8fdf 100644 --- a/serprog.c +++ b/serprog.c @@ -933,7 +933,7 @@ if (serprog_buses_supported & BUS_SPI) register_spi_master(&spi_master_serprog, NULL); if (serprog_buses_supported & BUS_NONSPI) - register_par_master(&par_master_serprog, serprog_buses_supported & BUS_NONSPI, NULL); + register_par_master(&par_master_serprog, serprog_buses_supported & BUS_NONSPI, NULL, 0); return 0; init_err_cleanup_exit: -- To view, visit https://review.coreboot.org/c/flashrom/+/68677 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Id4a4ba09ac493a67aedd3897e7cfc1377e12bdbe Gerrit-Change-Number: 68677 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: newchange

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[M] Change in flashrom[master]: chipset_enable.c: plumb max_rom_decodes from internal.c
by Edward O'Callaghan (Code Review) 23 Oct '22

23 Oct '22

Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/68676 ) Change subject: chipset_enable.c: plumb max_rom_decodes from internal.c ...................................................................... chipset_enable.c: plumb max_rom_decodes from internal.c Change-Id: If2692f272fb454a200a238109178e48857964439 Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> --- M chipset_enable.c M include/programmer.h M internal.c 3 files changed, 114 insertions(+), 103 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/76/68676/1 diff --git a/chipset_enable.c b/chipset_enable.c index d6103c1..a5f0c42 100644 --- a/chipset_enable.c +++ b/chipset_enable.c @@ -44,7 +44,7 @@ #include "hwaccess_x86_io.h" #include "hwaccess_x86_msr.h" -static int enable_flash_ali_m1533(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name) +static int enable_flash_ali_m1533(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name, struct decode_sizes *max_rom_decode_) { uint8_t tmp; @@ -59,7 +59,7 @@ return 0; } -static int enable_flash_rdc_r8610(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name) +static int enable_flash_rdc_r8610(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name, struct decode_sizes *max_rom_decode_) { uint8_t tmp; @@ -85,7 +85,7 @@ return 0; } -static int enable_flash_sis85c496(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name) +static int enable_flash_sis85c496(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name, struct decode_sizes *max_rom_decode_) { uint8_t tmp; @@ -135,7 +135,7 @@ return sbdev; } -static int enable_flash_sis501(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name) +static int enable_flash_sis501(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name, struct decode_sizes *max_rom_decode_) { uint8_t tmp; int ret = 0; @@ -160,7 +160,7 @@ return ret; } -static int enable_flash_sis5511(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name) +static int enable_flash_sis5511(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name, struct decode_sizes *max_rom_decode_) { uint8_t tmp; int ret = 0; @@ -207,12 +207,12 @@ return ret; } -static int enable_flash_sis530(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name) +static int enable_flash_sis530(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name, struct decode_sizes *max_rom_decode_) { return enable_flash_sis5x0(cfg, dev, name, 0x20, 0x04); } -static int enable_flash_sis540(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name) +static int enable_flash_sis540(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name, struct decode_sizes *max_rom_decode_) { return enable_flash_sis5x0(cfg, dev, name, 0x80, 0x40); } @@ -223,7 +223,7 @@ * - PDF: http://www.intel.com/design/intarch/datashts/29056201.pdf * - Order Number: 290562-001 */ -static int enable_flash_piix4(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name) +static int enable_flash_piix4(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name, struct decode_sizes *max_rom_decode_) { uint16_t old, new; uint16_t xbcs = 0x4e; /* X-Bus Chip Select register. */ @@ -380,7 +380,7 @@ return enable_flash_ich_bios_cntl_common(ich_generation, addr, NULL, 0); } -static int enable_flash_ich_fwh_decode(const struct programmer_cfg *cfg, struct pci_dev *dev, enum ich_chipset ich_generation) +static int enable_flash_ich_fwh_decode(const struct programmer_cfg *cfg, struct pci_dev *dev, enum ich_chipset ich_generation, struct decode_sizes *max_rom_decode_) { uint8_t fwh_sel1 = 0, fwh_sel2 = 0, fwh_dec_en_lo = 0, fwh_dec_en_hi = 0; /* silence compilers */ bool implemented = 0; @@ -549,42 +549,42 @@ contiguous = 0; } } - max_rom_decode.fwh = min(max_decode_fwh_idsel, max_decode_fwh_decode); - msg_pdbg("Maximum FWH chip size: 0x%x bytes\n", max_rom_decode.fwh); + max_rom_decode_->fwh = min(max_decode_fwh_idsel, max_decode_fwh_decode); + msg_pdbg("Maximum FWH chip size: 0x%x bytes\n", max_rom_decode_->fwh); return 0; } -static int enable_flash_ich_fwh(const struct programmer_cfg *cfg, struct pci_dev *dev, enum ich_chipset ich_generation, uint8_t bios_cntl) +static int enable_flash_ich_fwh(const struct programmer_cfg *cfg, struct pci_dev *dev, enum ich_chipset ich_generation, uint8_t bios_cntl, struct decode_sizes *max_rom_decode_) { int err; /* Configure FWH IDSEL decoder maps. */ - if ((err = enable_flash_ich_fwh_decode(cfg, dev, ich_generation)) != 0) + if ((err = enable_flash_ich_fwh_decode(cfg, dev, ich_generation, max_rom_decode_)) != 0) return err; internal_buses_supported &= BUS_FWH; return enable_flash_ich_bios_cntl_config_space(dev, ich_generation, bios_cntl); } -static int enable_flash_ich0(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name) +static int enable_flash_ich0(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name, struct decode_sizes *max_rom_decode_) { - return enable_flash_ich_fwh(cfg, dev, CHIPSET_ICH, 0x4e); + return enable_flash_ich_fwh(cfg, dev, CHIPSET_ICH, 0x4e, max_rom_decode_); } -static int enable_flash_ich2345(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name) +static int enable_flash_ich2345(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name, struct decode_sizes *max_rom_decode_) { - return enable_flash_ich_fwh(cfg, dev, CHIPSET_ICH2345, 0x4e); + return enable_flash_ich_fwh(cfg, dev, CHIPSET_ICH2345, 0x4e, max_rom_decode_); } -static int enable_flash_ich6(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name) +static int enable_flash_ich6(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name, struct decode_sizes *max_rom_decode_) { - return enable_flash_ich_fwh(cfg, dev, CHIPSET_ICH6, 0xdc); + return enable_flash_ich_fwh(cfg, dev, CHIPSET_ICH6, 0xdc, max_rom_decode_); } -static int enable_flash_poulsbo(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name) +static int enable_flash_poulsbo(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name, struct decode_sizes *max_rom_decode_) { - return enable_flash_ich_fwh(cfg, dev, CHIPSET_POULSBO, 0xd8); + return enable_flash_ich_fwh(cfg, dev, CHIPSET_POULSBO, 0xd8, max_rom_decode_); } static enum chipbustype enable_flash_ich_report_gcs( @@ -770,7 +770,7 @@ return boot_straps[bbs].bus; } -static int enable_flash_ich_spi(const struct programmer_cfg *cfg, struct pci_dev *dev, enum ich_chipset ich_generation, uint8_t bios_cntl) +static int enable_flash_ich_spi(const struct programmer_cfg *cfg, struct pci_dev *dev, enum ich_chipset ich_generation, uint8_t bios_cntl, struct decode_sizes *max_rom_decode_) { /* Get physical address of Root Complex Register Block */ uint32_t rcra = pci_read_long(dev, 0xf0) & 0xffffc000; @@ -784,7 +784,7 @@ const enum chipbustype boot_buses = enable_flash_ich_report_gcs(dev, ich_generation, rcrb); /* Handle FWH-related parameters and initialization */ - int ret_fwh = enable_flash_ich_fwh(cfg, dev, ich_generation, bios_cntl); + int ret_fwh = enable_flash_ich_fwh(cfg, dev, ich_generation, bios_cntl, max_rom_decode_); if (ret_fwh == ERROR_FATAL) return ret_fwh; @@ -831,82 +831,82 @@ return 0; } -static int enable_flash_tunnelcreek(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name) +static int enable_flash_tunnelcreek(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name, struct decode_sizes *max_rom_decode_) { - return enable_flash_ich_spi(cfg, dev, CHIPSET_TUNNEL_CREEK, 0xd8); + return enable_flash_ich_spi(cfg, dev, CHIPSET_TUNNEL_CREEK, 0xd8, max_rom_decode_); } -static int enable_flash_s12x0(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name) +static int enable_flash_s12x0(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name, struct decode_sizes *max_rom_decode_) { - return enable_flash_ich_spi(cfg, dev, CHIPSET_CENTERTON, 0xd8); + return enable_flash_ich_spi(cfg, dev, CHIPSET_CENTERTON, 0xd8, max_rom_decode_); } -static int enable_flash_ich7(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name) +static int enable_flash_ich7(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name, struct decode_sizes *max_rom_decode_) { - return enable_flash_ich_spi(cfg, dev, CHIPSET_ICH7, 0xdc); + return enable_flash_ich_spi(cfg, dev, CHIPSET_ICH7, 0xdc, max_rom_decode_); } -static int enable_flash_ich8(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name) +static int enable_flash_ich8(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name, struct decode_sizes *max_rom_decode_) { - return enable_flash_ich_spi(cfg, dev, CHIPSET_ICH8, 0xdc); + return enable_flash_ich_spi(cfg, dev, CHIPSET_ICH8, 0xdc, max_rom_decode_); } -static int enable_flash_ich9(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name) +static int enable_flash_ich9(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name, struct decode_sizes *max_rom_decode_) { - return enable_flash_ich_spi(cfg, dev, CHIPSET_ICH9, 0xdc); + return enable_flash_ich_spi(cfg, dev, CHIPSET_ICH9, 0xdc, max_rom_decode_); } -static int enable_flash_ich10(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name) +static int enable_flash_ich10(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name, struct decode_sizes *max_rom_decode_) { - return enable_flash_ich_spi(cfg, dev, CHIPSET_ICH10, 0xdc); + return enable_flash_ich_spi(cfg, dev, CHIPSET_ICH10, 0xdc, max_rom_decode_); } /* Ibex Peak aka. 5 series & 3400 series */ -static int enable_flash_pch5(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name) +static int enable_flash_pch5(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name, struct decode_sizes *max_rom_decode_) { - return enable_flash_ich_spi(cfg, dev, CHIPSET_5_SERIES_IBEX_PEAK, 0xdc); + return enable_flash_ich_spi(cfg, dev, CHIPSET_5_SERIES_IBEX_PEAK, 0xdc, max_rom_decode_); } /* Cougar Point aka. 6 series & c200 series */ -static int enable_flash_pch6(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name) +static int enable_flash_pch6(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name, struct decode_sizes *max_rom_decode_) { - return enable_flash_ich_spi(cfg, dev, CHIPSET_6_SERIES_COUGAR_POINT, 0xdc); + return enable_flash_ich_spi(cfg, dev, CHIPSET_6_SERIES_COUGAR_POINT, 0xdc, max_rom_decode_); } /* Panther Point aka. 7 series */ -static int enable_flash_pch7(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name) +static int enable_flash_pch7(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name, struct decode_sizes *max_rom_decode_) { - return enable_flash_ich_spi(cfg, dev, CHIPSET_7_SERIES_PANTHER_POINT, 0xdc); + return enable_flash_ich_spi(cfg, dev, CHIPSET_7_SERIES_PANTHER_POINT, 0xdc, max_rom_decode_); } /* Lynx Point aka. 8 series */ -static int enable_flash_pch8(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name) +static int enable_flash_pch8(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name, struct decode_sizes *max_rom_decode_) { - return enable_flash_ich_spi(cfg, dev, CHIPSET_8_SERIES_LYNX_POINT, 0xdc); + return enable_flash_ich_spi(cfg, dev, CHIPSET_8_SERIES_LYNX_POINT, 0xdc, max_rom_decode_); } /* Lynx Point LP aka. 8 series low-power */ -static int enable_flash_pch8_lp(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name) +static int enable_flash_pch8_lp(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name, struct decode_sizes *max_rom_decode_) { - return enable_flash_ich_spi(cfg, dev, CHIPSET_8_SERIES_LYNX_POINT_LP, 0xdc); + return enable_flash_ich_spi(cfg, dev, CHIPSET_8_SERIES_LYNX_POINT_LP, 0xdc, max_rom_decode_); } /* Wellsburg (for Haswell-EP Xeons) */ -static int enable_flash_pch8_wb(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name) +static int enable_flash_pch8_wb(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name, struct decode_sizes *max_rom_decode_) { - return enable_flash_ich_spi(cfg, dev, CHIPSET_8_SERIES_WELLSBURG, 0xdc); + return enable_flash_ich_spi(cfg, dev, CHIPSET_8_SERIES_WELLSBURG, 0xdc, max_rom_decode_); } /* Wildcat Point */ -static int enable_flash_pch9(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name) +static int enable_flash_pch9(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name, struct decode_sizes *max_rom_decode_) { - return enable_flash_ich_spi(cfg, dev, CHIPSET_9_SERIES_WILDCAT_POINT, 0xdc); + return enable_flash_ich_spi(cfg, dev, CHIPSET_9_SERIES_WILDCAT_POINT, 0xdc, max_rom_decode_); } /* Wildcat Point LP */ -static int enable_flash_pch9_lp(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name) +static int enable_flash_pch9_lp(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name, struct decode_sizes *max_rom_decode_) { - return enable_flash_ich_spi(cfg, dev, CHIPSET_9_SERIES_WILDCAT_POINT_LP, 0xdc); + return enable_flash_ich_spi(cfg, dev, CHIPSET_9_SERIES_WILDCAT_POINT_LP, 0xdc, max_rom_decode_); } /* Sunrise Point */ @@ -979,57 +979,57 @@ return ret; } -static int enable_flash_pch100(const struct programmer_cfg *cfg, struct pci_dev *const dev, const char *const name) +static int enable_flash_pch100(const struct programmer_cfg *cfg, struct pci_dev *const dev, const char *const name, struct decode_sizes *max_rom_decode_) { return enable_flash_pch100_or_c620(cfg, dev, name, 0x1f, 5, CHIPSET_100_SERIES_SUNRISE_POINT); } -static int enable_flash_c620(const struct programmer_cfg *cfg, struct pci_dev *const dev, const char *const name) +static int enable_flash_c620(const struct programmer_cfg *cfg, struct pci_dev *const dev, const char *const name, struct decode_sizes *max_rom_decode_) { return enable_flash_pch100_or_c620(cfg, dev, name, 0x1f, 5, CHIPSET_C620_SERIES_LEWISBURG); } -static int enable_flash_pch300(const struct programmer_cfg *cfg, struct pci_dev *const dev, const char *const name) +static int enable_flash_pch300(const struct programmer_cfg *cfg, struct pci_dev *const dev, const char *const name, struct decode_sizes *max_rom_decode_) { return enable_flash_pch100_or_c620(cfg, dev, name, 0x1f, 5, CHIPSET_300_SERIES_CANNON_POINT); } -static int enable_flash_pch400(const struct programmer_cfg *cfg, struct pci_dev *const dev, const char *const name) +static int enable_flash_pch400(const struct programmer_cfg *cfg, struct pci_dev *const dev, const char *const name, struct decode_sizes *max_rom_decode_) { return enable_flash_pch100_or_c620(cfg, dev, name, 0x1f, 5, CHIPSET_400_SERIES_COMET_POINT); } -static int enable_flash_pch500(const struct programmer_cfg *cfg, struct pci_dev *const dev, const char *const name) +static int enable_flash_pch500(const struct programmer_cfg *cfg, struct pci_dev *const dev, const char *const name, struct decode_sizes *max_rom_decode_) { return enable_flash_pch100_or_c620(cfg, dev, name, 0x1f, 5, CHIPSET_500_SERIES_TIGER_POINT); } -static int enable_flash_pch600(const struct programmer_cfg *cfg, struct pci_dev *const dev, const char *const name) +static int enable_flash_pch600(const struct programmer_cfg *cfg, struct pci_dev *const dev, const char *const name, struct decode_sizes *max_rom_decode_) { return enable_flash_pch100_or_c620(cfg, dev, name, 0x1f, 5, CHIPSET_600_SERIES_ALDER_POINT); } -static int enable_flash_mtl(const struct programmer_cfg *cfg, struct pci_dev *const dev, const char *const name) +static int enable_flash_mtl(const struct programmer_cfg *cfg, struct pci_dev *const dev, const char *const name, struct decode_sizes *max_rom_decode_) { return enable_flash_pch100_or_c620(cfg, dev, name, 0x1f, 5, CHIPSET_METEOR_LAKE); } -static int enable_flash_mcc(const struct programmer_cfg *cfg, struct pci_dev *const dev, const char *const name) +static int enable_flash_mcc(const struct programmer_cfg *cfg, struct pci_dev *const dev, const char *const name, struct decode_sizes *max_rom_decode_) { return enable_flash_pch100_or_c620(cfg, dev, name, 0x1f, 5, CHIPSET_ELKHART_LAKE); } -static int enable_flash_jsl(const struct programmer_cfg *cfg, struct pci_dev *const dev, const char *const name) +static int enable_flash_jsl(const struct programmer_cfg *cfg, struct pci_dev *const dev, const char *const name, struct decode_sizes *max_rom_decode_) { return enable_flash_pch100_or_c620(cfg, dev, name, 0x1f, 5, CHIPSET_JASPER_LAKE); } -static int enable_flash_apl(const struct programmer_cfg *cfg, struct pci_dev *const dev, const char *const name) +static int enable_flash_apl(const struct programmer_cfg *cfg, struct pci_dev *const dev, const char *const name, struct decode_sizes *max_rom_decode_) { return enable_flash_pch100_or_c620(cfg, dev, name, 0x0d, 2, CHIPSET_APOLLO_LAKE); } -static int enable_flash_glk(const struct programmer_cfg *cfg, struct pci_dev *const dev, const char *const name) +static int enable_flash_glk(const struct programmer_cfg *cfg, struct pci_dev *const dev, const char *const name, struct decode_sizes *max_rom_decode_) { return enable_flash_pch100_or_c620(cfg, dev, name, 0x0d, 2, CHIPSET_GEMINI_LAKE); } @@ -1044,7 +1044,7 @@ * - SPIBAR (coined SBASE) at LPC config 0x54 (instead of [RCRB] + 0x3800). * - BIOS_CNTL (coined BCR) at [SPIBAR] + 0xFC (instead of LPC config 0xDC). */ -static int enable_flash_silvermont(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name) +static int enable_flash_silvermont(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name, struct decode_sizes *max_rom_decode_) { enum ich_chipset ich_generation = CHIPSET_BAYTRAIL; @@ -1060,7 +1060,7 @@ physunmap(rcrb, 4); /* Handle fwh_idsel parameter */ - int ret_fwh = enable_flash_ich_fwh_decode(cfg, dev, ich_generation); + int ret_fwh = enable_flash_ich_fwh_decode(cfg, dev, ich_generation, max_rom_decode_); if (ret_fwh == ERROR_FATAL) return ret_fwh; @@ -1092,7 +1092,7 @@ return 0; } -static int via_no_byte_merge(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name) +static int via_no_byte_merge(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name, struct decode_sizes *max_rom_decode_) { uint8_t val; @@ -1105,7 +1105,7 @@ return NOT_DONE_YET; /* need to find south bridge, too */ } -static int enable_flash_vt823x(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name) +static int enable_flash_vt823x(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name, struct decode_sizes *max_rom_decode_) { uint8_t val; @@ -1132,7 +1132,7 @@ return 0; } -static int enable_flash_vt_vx(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name) +static int enable_flash_vt_vx(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name, struct decode_sizes *max_rom_decode_) { struct pci_dev *south_north = pcidev_find(0x1106, 0xa353); if (south_north == NULL) { @@ -1143,7 +1143,7 @@ msg_pdbg("Strapped to "); if ((pci_read_byte(south_north, 0x56) & 0x01) == 0) { msg_pdbg("LPC.\n"); - return enable_flash_vt823x(cfg, dev, name); + return enable_flash_vt823x(cfg, dev, name, max_rom_decode_); } msg_pdbg("SPI.\n"); @@ -1196,12 +1196,12 @@ return via_init_spi(spi0_mm_base); } -static int enable_flash_vt8237s_spi(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name) +static int enable_flash_vt8237s_spi(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name, struct decode_sizes *max_rom_decode_) { return via_init_spi(pci_read_long(dev, 0xbc) << 8); } -static int enable_flash_cs5530(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name) +static int enable_flash_cs5530(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name, struct decode_sizes *max_rom_decode_) { uint8_t reg8; @@ -1239,18 +1239,18 @@ reg8 = pci_read_byte(dev, CS5530_RESET_CONTROL_REG); if (reg8 & CS5530_ISA_MASTER) { /* We have A0-A23 available. */ - max_rom_decode.parallel = 16 * 1024 * 1024; + max_rom_decode_->parallel = 16 * 1024 * 1024; } else { reg8 = pci_read_byte(dev, CS5530_USB_SHADOW_REG); if (reg8 & CS5530_ENABLE_SA2320) { /* We have A0-19, A20-A23 available. */ - max_rom_decode.parallel = 16 * 1024 * 1024; + max_rom_decode_->parallel = 16 * 1024 * 1024; } else if (reg8 & CS5530_ENABLE_SA20) { /* We have A0-19, A20 available. */ - max_rom_decode.parallel = 2 * 1024 * 1024; + max_rom_decode_->parallel = 2 * 1024 * 1024; } else { /* A20 and above are not active. */ - max_rom_decode.parallel = 1024 * 1024; + max_rom_decode_->parallel = 1024 * 1024; } } @@ -1265,7 +1265,7 @@ * To enable write to NOR Boot flash for the benefit of systems that have such * a setup, raise MSR 0x51400018 WE_CS3 (write enable Boot Flash Chip Select). */ -static int enable_flash_cs5536(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name) +static int enable_flash_cs5536(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name, struct decode_sizes *max_rom_decode_) { #define MSR_RCONF_DEFAULT 0x1808 #define MSR_NORF_CTL 0x51400018 @@ -1294,7 +1294,7 @@ return 0; } -static int enable_flash_sc1100(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name) +static int enable_flash_sc1100(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name, struct decode_sizes *max_rom_decode_) { #define SC_REG 0x52 uint8_t new; @@ -1353,29 +1353,29 @@ return 0; } -static int enable_flash_amd_768_8111(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name) +static int enable_flash_amd_768_8111(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name, struct decode_sizes *max_rom_decode_) { /* Enable decoding of 0xFFB00000 to 0xFFFFFFFF (5 MB). */ - max_rom_decode.lpc = 5 * 1024 * 1024; + max_rom_decode_->lpc = 5 * 1024 * 1024; return enable_flash_amd_via(cfg, dev, name, 0xC0); } -static int enable_flash_vt82c586(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name) +static int enable_flash_vt82c586(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name, struct decode_sizes *max_rom_decode_) { /* Enable decoding of 0xFFF80000 to 0xFFFFFFFF. (512 kB) */ - max_rom_decode.parallel = 512 * 1024; + max_rom_decode_->parallel = 512 * 1024; return enable_flash_amd_via(cfg, dev, name, 0xC0); } /* Works for VT82C686A/B too. */ -static int enable_flash_vt82c596(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name) +static int enable_flash_vt82c596(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name, struct decode_sizes *max_rom_decode_) { /* Enable decoding of 0xFFF00000 to 0xFFFFFFFF. (1 MB) */ - max_rom_decode.parallel = 1024 * 1024; + max_rom_decode_->parallel = 1024 * 1024; return enable_flash_amd_via(cfg, dev, name, 0xE0); } -static int enable_flash_sb600(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name) +static int enable_flash_sb600(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name, struct decode_sizes *max_rom_decode_) { uint32_t prot; uint8_t reg; @@ -1466,7 +1466,7 @@ return 0; } -static int enable_flash_nvidia_nforce2(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name) +static int enable_flash_nvidia_nforce2(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name, struct decode_sizes *max_rom_decode_) { rpci_write_byte(dev, 0x92, 0); if (enable_flash_nvidia_common(cfg, dev, name)) @@ -1475,7 +1475,7 @@ return 0; } -static int enable_flash_ck804(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name) +static int enable_flash_ck804(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name, struct decode_sizes *max_rom_decode_) { uint32_t segctrl; uint8_t reg, old, new; @@ -1550,7 +1550,7 @@ return 0; } -static int enable_flash_osb4(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name) +static int enable_flash_osb4(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name, struct decode_sizes *max_rom_decode_) { uint8_t tmp; @@ -1568,7 +1568,7 @@ } /* ATI Technologies Inc IXP SB400 PCI-ISA Bridge (rev 80) */ -static int enable_flash_sb400(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name) +static int enable_flash_sb400(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name, struct decode_sizes *max_rom_decode_) { uint8_t tmp; struct pci_dev *smbusdev; @@ -1603,7 +1603,7 @@ return 0; } -static int enable_flash_mcp55(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name) +static int enable_flash_mcp55(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name, struct decode_sizes *max_rom_decode_) { uint8_t val; uint16_t wordval; @@ -1630,7 +1630,7 @@ * It is assumed that LPC chips need the MCP55 code and SPI chips need the * code provided in enable_flash_mcp6x_7x_common. */ -static int enable_flash_mcp6x_7x(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name) +static int enable_flash_mcp6x_7x(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name, struct decode_sizes *max_rom_decode_) { int ret = 0, want_spi = 0; uint8_t val; @@ -1642,7 +1642,7 @@ switch ((val >> 5) & 0x3) { case 0x0: - ret = enable_flash_mcp55(cfg, dev, name); + ret = enable_flash_mcp55(cfg, dev, name, max_rom_decode_); internal_buses_supported &= BUS_LPC; msg_pdbg("Flash bus type is LPC\n"); break; @@ -1681,7 +1681,7 @@ return ret; } -static int enable_flash_ht1000(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name) +static int enable_flash_ht1000(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name, struct decode_sizes *max_rom_decode_) { uint8_t val; @@ -1704,7 +1704,7 @@ * complete flash is mapped somewhere below 1G. The position can be determined * by the BOOTCS PAR register. */ -static int get_flashbase_sc520(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name) +static int get_flashbase_sc520(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name, struct decode_sizes *max_rom_decode_) { int i, bootcs_found = 0; uint32_t parx = 0; @@ -2183,7 +2183,7 @@ {0}, }; -int chipset_flash_enable(const struct programmer_cfg *cfg) +int chipset_flash_enable(const struct programmer_cfg *cfg, struct decode_sizes *max_rom_decode_) { struct pci_dev *dev = NULL; int ret = -2; /* Nothing! */ @@ -2232,7 +2232,7 @@ continue; } msg_pinfo("Enabling flash write... "); - ret = chipset_enables[i].doit(cfg, dev, chipset_enables[i].device_name); + ret = chipset_enables[i].doit(cfg, dev, chipset_enables[i].device_name, max_rom_decode_); if (ret == NOT_DONE_YET) { ret = -2; msg_pinfo("OK - searching further chips.\n"); diff --git a/include/programmer.h b/include/programmer.h index d5338d9..4da7330 100644 --- a/include/programmer.h +++ b/include/programmer.h @@ -32,6 +32,13 @@ }; struct programmer_cfg; +struct decode_sizes { + uint32_t parallel; + uint32_t lpc; + uint32_t fwh; + uint32_t spi; +}; + struct dev_entry { uint16_t vendor_id; uint16_t device_id; @@ -149,7 +156,7 @@ const enum test_state status; const char *vendor_name; const char *device_name; - int (*doit) (const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name); + int (*doit) (const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name, struct decode_sizes *max_rom_decode_); }; extern const struct penable chipset_enables[]; @@ -231,7 +238,7 @@ struct decode_sizes *max_rom_decode_); /* chipset_enable.c */ -int chipset_flash_enable(const struct programmer_cfg *cfg); +int chipset_flash_enable(const struct programmer_cfg *cfg, struct decode_sizes *); /* processor_enable.c */ int processor_flash_enable(void); @@ -277,12 +284,6 @@ /* flashrom.c */ -struct decode_sizes { - uint32_t parallel; - uint32_t lpc; - uint32_t fwh; - uint32_t spi; -}; // FIXME: These need to be local, not global extern struct decode_sizes max_rom_decode; extern bool programmer_may_write; diff --git a/internal.c b/internal.c index a4710ee..1b3b8b0 100644 --- a/internal.c +++ b/internal.c @@ -285,7 +285,7 @@ /* try to enable it. Failure IS an option, since not all motherboards * really need this to be done, etc., etc. */ - ret = chipset_flash_enable(cfg); + ret = chipset_flash_enable(cfg, &max_rom_decode); if (ret == -2) { msg_perr("WARNING: No chipset found. Flash detection " "will most likely fail.\n"); -- To view, visit https://review.coreboot.org/c/flashrom/+/68676 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: If2692f272fb454a200a238109178e48857964439 Gerrit-Change-Number: 68676 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: newchange

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[S] Change in flashrom[master]: it87spi: Plumb max_rom_decode into it8705f_write_enable() helper
by Edward O'Callaghan (Code Review) 23 Oct '22

23 Oct '22

Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/68675 ) Change subject: it87spi: Plumb max_rom_decode into it8705f_write_enable() helper ...................................................................... it87spi: Plumb max_rom_decode into it8705f_write_enable() helper Change-Id: Iec08cb4d56a8ca62f00b0f7323b36f7d2f850e81 Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> --- M board_enable.c M include/programmer.h M internal.c M it87spi.c 4 files changed, 20 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/75/68675/1 diff --git a/board_enable.c b/board_enable.c index ad6e63a..fe891a4 100644 --- a/board_enable.c +++ b/board_enable.c @@ -601,7 +601,7 @@ * Suited for all boards with ITE IT8705F. * The SIS950 Super I/O probably requires a similar flash write enable. */ -int it8705f_write_enable(uint8_t port) +int it8705f_write_enable(uint8_t port, struct decode_sizes *max_rom_decode_) { uint8_t tmp; int ret = 0; @@ -620,16 +620,16 @@ msg_pdbg("Enabling IT8705F flash ROM interface write.\n"); if (tmp & 0x02) { /* The data sheet contradicts itself about max size. */ - max_rom_decode.parallel = 1024 * 1024; + max_rom_decode_->parallel = 1024 * 1024; msg_pinfo("IT8705F with very unusual settings.\n" "Please send the output of \"flashrom -V -p internal\" to flashrom(a)flashrom.org\n" "with \"IT8705: your board name: flashrom -V\" as the subject to help us finish\n" "support for your Super I/O. Thanks.\n"); ret = 1; } else if (tmp & 0x08) { - max_rom_decode.parallel = 512 * 1024; + max_rom_decode_->parallel = 512 * 1024; } else { - max_rom_decode.parallel = 256 * 1024; + max_rom_decode_->parallel = 256 * 1024; } /* Safety checks. The data sheet is unclear here: Segments 1+3 * overlap, no segment seems to cover top - 1MB to top - 512kB. @@ -673,7 +673,7 @@ ret = 1; } msg_pdbg("Maximum IT8705F parallel flash decode size is %u.\n", - max_rom_decode.parallel); + max_rom_decode_->parallel); if (ret) { msg_pinfo("Not enabling IT8705F flash write.\n"); } else { diff --git a/include/programmer.h b/include/programmer.h index dba701f..d5338d9 100644 --- a/include/programmer.h +++ b/include/programmer.h @@ -221,7 +221,7 @@ void w836xx_ext_enter(uint16_t port); void w836xx_ext_leave(uint16_t port); void probe_superio_winbond(void); -int it8705f_write_enable(uint8_t port); +int it8705f_write_enable(uint8_t port, struct decode_sizes *max_rom_decode_); uint8_t sio_read(uint16_t port, uint8_t reg); void sio_write(uint16_t port, uint8_t reg, uint8_t data); void sio_mask(uint16_t port, uint8_t reg, uint8_t data, uint8_t mask); @@ -373,7 +373,7 @@ void enter_conf_mode_ite(uint16_t port); void exit_conf_mode_ite(uint16_t port); void probe_superio_ite(void); -int init_superio_ite(const struct programmer_cfg *cfg); +int init_superio_ite(const struct programmer_cfg *cfg, struct decode_sizes *max_rom_decode_); /* trivial wrapper to avoid cluttering internal_init() with #if */ static inline int try_mtd(const struct programmer_cfg *cfg) diff --git a/internal.c b/internal.c index d12fb1b..a4710ee 100644 --- a/internal.c +++ b/internal.c @@ -296,7 +296,7 @@ #if defined(__i386__) || defined(__x86_64__) /* Probe unconditionally for ITE Super I/O chips. This enables LPC->SPI translation on IT87* and * parallel writes on IT8705F. Also, this handles the manual chip select for Gigabyte's DualBIOS. */ - init_superio_ite(cfg); + init_superio_ite(cfg, &max_rom_decode); if (board_flash_enable(board_vendor, board_model, cb_vendor, cb_model, &max_rom_decode)) { msg_perr("Aborting to be safe.\n"); diff --git a/it87spi.c b/it87spi.c index a022041..a9f9a64 100644 --- a/it87spi.c +++ b/it87spi.c @@ -443,7 +443,7 @@ return register_spi_master(&spi_master_it87xx, data); } -int init_superio_ite(const struct programmer_cfg *cfg) +int init_superio_ite(const struct programmer_cfg *cfg, struct decode_sizes *max_rom_decode_) { int i; int ret = 0; @@ -454,7 +454,7 @@ switch (superios[i].model) { case 0x8705: - ret |= it8705f_write_enable(superios[i].port); + ret |= it8705f_write_enable(superios[i].port, max_rom_decode_); break; case 0x8686: case 0x8716: -- To view, visit https://review.coreboot.org/c/flashrom/+/68675 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Iec08cb4d56a8ca62f00b0f7323b36f7d2f850e81 Gerrit-Change-Number: 68675 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: newchange

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[S] Change in flashrom[master]: plumb max_rom_decode into board_enable_flash() helper
by Edward O'Callaghan (Code Review) 23 Oct '22

23 Oct '22

Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/68674 ) Change subject: plumb max_rom_decode into board_enable_flash() helper ...................................................................... plumb max_rom_decode into board_enable_flash() helper Change-Id: I180b047fc07be946cdc5ba93871f9ff4f4c67df4 Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> --- M board_enable.c M include/programmer.h M internal.c 3 files changed, 16 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/74/68674/1 diff --git a/board_enable.c b/board_enable.c index 4903c0f..ad6e63a 100644 --- a/board_enable.c +++ b/board_enable.c @@ -2735,7 +2735,8 @@ board_handle_phase(P2); } -int board_flash_enable(const char *vendor, const char *model, const char *cb_vendor, const char *cb_model) +int board_flash_enable(const char *vendor, const char *model, const char *cb_vendor, const char *cb_model, + struct decode_sizes *max_rom_decode_) { const struct board_match *board = NULL; int ret = 0; @@ -2766,7 +2767,7 @@ /* limit the maximum size of the parallel bus */ if (board->max_rom_decode_parallel) - max_rom_decode.parallel = board->max_rom_decode_parallel * 1024; + max_rom_decode_->parallel = board->max_rom_decode_parallel * 1024; if (board->enable != NULL) { msg_pinfo("Enabling full flash access for board \"%s %s\"... ", diff --git a/include/programmer.h b/include/programmer.h index 386e6ec..dba701f 100644 --- a/include/programmer.h +++ b/include/programmer.h @@ -227,7 +227,8 @@ void sio_mask(uint16_t port, uint8_t reg, uint8_t data, uint8_t mask); void board_handle_before_superio(void); void board_handle_before_laptop(void); -int board_flash_enable(const char *vendor, const char *model, const char *cb_vendor, const char *cb_model); +int board_flash_enable(const char *vendor, const char *model, const char *cb_vendor, const char *cb_model, + struct decode_sizes *max_rom_decode_); /* chipset_enable.c */ int chipset_flash_enable(const struct programmer_cfg *cfg); diff --git a/internal.c b/internal.c index 8c834e2..d12fb1b 100644 --- a/internal.c +++ b/internal.c @@ -298,7 +298,7 @@ * parallel writes on IT8705F. Also, this handles the manual chip select for Gigabyte's DualBIOS. */ init_superio_ite(cfg); - if (board_flash_enable(board_vendor, board_model, cb_vendor, cb_model)) { + if (board_flash_enable(board_vendor, board_model, cb_vendor, cb_model, &max_rom_decode)) { msg_perr("Aborting to be safe.\n"); ret = 1; goto internal_init_exit; -- To view, visit https://review.coreboot.org/c/flashrom/+/68674 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I180b047fc07be946cdc5ba93871f9ff4f4c67df4 Gerrit-Change-Number: 68674 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: newchange

1 0

[L] Change in flashrom[master]: flashrom.c: Add wrapper function to use the erase algorithm
by Aarya (Code Review) 22 Oct '22

22 Oct '22

Attention is currently required from: Simon Buhrow, Nico Huber, Thomas Heijligen. Hello build bot (Jenkins), Simon Buhrow, Thomas Heijligen, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/flashrom/+/66104 to look at the new patch set (#65). Change subject: flashrom.c: Add wrapper function to use the erase algorithm ...................................................................... flashrom.c: Add wrapper function to use the erase algorithm Add a function to call the erase algorithm. Change-Id: I29e3f2bd796759794184b125741a5abaac6f3ce8 Signed-off-by: Aarya Chaumal <aarya.chaumal(a)gmail.com> --- M flashrom.c M tests/chip_wp.c 2 files changed, 144 insertions(+), 289 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/04/66104/65 -- To view, visit https://review.coreboot.org/c/flashrom/+/66104 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I29e3f2bd796759794184b125741a5abaac6f3ce8 Gerrit-Change-Number: 66104 Gerrit-PatchSet: 65 Gerrit-Owner: Aarya <aarya.chaumal(a)gmail.com> Gerrit-Reviewer: Simon Buhrow Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Simon Buhrow Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Thomas Heijligen <src(a)posteo.de> Gerrit-MessageType: newpatchset

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