Attention is currently required from: Alan Green, Samir Ibradžić.
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/55695 )
Change subject: ft2232_spi: Revise comments about output pin states
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
Alan, Samir, I'm sorry about the reverts. I think it's best to
restart from a sound code base. If you think it's easier to fix
everything on top of the current TOT, please go ahead and ignore
the reverts.
It seems you were both working on the same feature, general GPIO
control indipendent from CS#. But that's not what the original
`csgpiol` code intended (hence the `cs` in its name).
--
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Attention is currently required from: Alan Green, Edward O'Callaghan, Angel Pons, Samir Ibradžić.
Hello Alan Green, Edward O'Callaghan, Angel Pons, Samir Ibradžić,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/flashrom/+/55695
to review the following change.
Change subject: ft2232_spi: Revise comments about output pin states
......................................................................
ft2232_spi: Revise comments about output pin states
The meaning of the variables is easy to misunderstand as some
states are merely implicit: All output pins that are not set
in the `cs_bits` mask will be constantly driven low. This may
be sheer coincidence as all programmers that need additional
pins driven use active-low signals to enable buffers.
While other pins stay low, *all* pins set in the `cs_bits`
mask are supposed to be toggled during SPI transactions.
Also drop some irritating dead code and try to explain things
in a comment.
Change-Id: I2b84ede01759c80f69d5ad17e43783d09ecd1107
Signed-off-by: Nico Huber <nico.h(a)gmx.de>
---
M ft2232_spi.c
1 file changed, 21 insertions(+), 9 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/95/55695/1
diff --git a/ft2232_spi.c b/ft2232_spi.c
index dba979b..e546f6c 100644
--- a/ft2232_spi.c
+++ b/ft2232_spi.c
@@ -86,15 +86,27 @@
#define BITMODE_BITBANG_NORMAL 1
#define BITMODE_BITBANG_SPI 2
-/* The variables cs_bits and pindir store the values for the "set data bits low byte" MPSSE command that
- * sets the initial state and the direction of the I/O pins. The pin offsets are as follows:
- * SCK is bit 0.
- * DO is bit 1.
- * DI is bit 2.
- * CS is bit 3.
+/*
+ * The variables `cs_bits` and `pindir` store the values for the
+ * "set data bits low byte" MPSSE command that sets the initial
+ * state and the direction of the I/O pins. `cs_bits` pins default
+ * to high and will be toggled during SPI transactions. All other
+ * output pins will be kept low all the time. On exit, all pins
+ * will be reconfigured as inputs.
*
- * The default values (set below in ft2232_spi_init) are used for most devices:
- * value: 0x08 CS=high, DI=low, DO=low, SK=low
+ * The pin offsets are as follows:
+ * TCK/SK is bit 0.
+ * TDI/DO is bit 1.
+ * TDO/DI is bit 2.
+ * TMS/CS is bit 3.
+ * GPIOL0 is bit 4.
+ * GPIOL1 is bit 5.
+ * GPIOL2 is bit 6.
+ * GPIOL3 is bit 7.
+ *
+ * The default values (set below in ft2232_spi_init) are used for
+ * most devices:
+ * value: 0x08 CS=high, DI=low, DO=low, SK=low
* dir: 0x0b CS=output, DI=input, DO=output, SK=output
*/
struct ft2232_data {
@@ -218,7 +230,7 @@
msg_pspew("Assert CS#\n");
buf[i++] = SET_BITS_LOW;
- buf[i++] = 0 & ~spi_data->cs_bits; /* assertive */
+ buf[i++] = 0; /* assert CS# pins, all other output pins stay low */
buf[i++] = spi_data->pindir;
/* WREN, OP(PROGRAM, ERASE), ADDR, DATA */
--
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Gerrit-MessageType: newchange
Attention is currently required from: Alan Green, Edward O'Callaghan, Angel Pons, Samir Ibradžić.
Hello Alan Green, Edward O'Callaghan, Angel Pons, Samir Ibradžić,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/flashrom/+/55694
to review the following change.
Change subject: Revert "ft2232_spi: Enhance csgpiol parameter for FT2232"
......................................................................
Revert "ft2232_spi: Enhance csgpiol parameter for FT2232"
This reverts commit ba6575de82f091b97ea0f2efcf2f79ef3739d64f.
Technically, the only thing that is wrong here is the lack of docu-
mentation (manpage update). However, as this change was succeeded by
a regressing fixup patch, it seems likely that the meaning of the
`csgpiol` parameter was just misunderstood and these changes were
not what the author intended.
Change-Id: I460237b9d275b1cd1d8a069f852d17dea393b14e
Signed-off-by: Nico Huber <nico.h(a)gmx.de>
---
M ft2232_spi.c
1 file changed, 14 insertions(+), 26 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/94/55694/1
diff --git a/ft2232_spi.c b/ft2232_spi.c
index 4a3a5a4..dba979b 100644
--- a/ft2232_spi.c
+++ b/ft2232_spi.c
@@ -88,17 +88,10 @@
/* The variables cs_bits and pindir store the values for the "set data bits low byte" MPSSE command that
* sets the initial state and the direction of the I/O pins. The pin offsets are as follows:
- * TCK/SK is bit 0.
- * TDI/DO is bit 1.
- * TDO/DI is bit 2.
- * TMS/CS is bit 3.
- * GPIOL0 is bit 4.
- * GPIOL1 is bit 5.
- * GPIOL2 is bit 6.
- * GPIOL3 is bit 7.
- *
- * The pin signal direction bit offsets follow the same order; 0 means that
- * pin at the matching bit index is an input, 1 means pin is an output.
+ * SCK is bit 0.
+ * DO is bit 1.
+ * DI is bit 2.
+ * CS is bit 3.
*
* The default values (set below in ft2232_spi_init) are used for most devices:
* value: 0x08 CS=high, DI=low, DO=low, SK=low
@@ -459,24 +452,19 @@
}
free(arg);
- /* Allows setting multiple GPIOL states, for example: csgpiol=012 */
arg = extract_programmer_param("csgpiol");
if (arg) {
- unsigned int ngpios = strlen(arg);
- for (unsigned int i = 0; i <= ngpios; i++) {
- int temp = arg[i] - '0';
- if (ngpios == 0 || (ngpios != i && (temp < 0 || temp > 3))) {
- msg_perr("Error: Invalid GPIOLs specified: \"%s\".\n"
- "Valid values are numbers between 0 and 3. "
- "Multiple GPIOLs can be specified.\n", arg);
- free(arg);
- return -2;
- } else {
- unsigned int pin = temp + 4;
- cs_bits |= 1 << pin;
- pindir |= 1 << pin;
- }
+ char *endptr;
+ unsigned int temp = strtoul(arg, &endptr, 10);
+ if (*endptr || endptr == arg || temp > 3) {
+ msg_perr("Error: Invalid GPIOL specified: \"%s\".\n"
+ "Valid values are between 0 and 3.\n", arg);
+ free(arg);
+ return -2;
}
+ unsigned int pin = temp + 4;
+ cs_bits |= 1 << pin;
+ pindir |= 1 << pin;
}
free(arg);
--
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Attention is currently required from: Alan Green, Edward O'Callaghan, Angel Pons, Samir Ibradžić.
Hello Alan Green, Edward O'Callaghan, Angel Pons, Samir Ibradžić,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/flashrom/+/55693
to review the following change.
Change subject: Revert "ft2232_spi: Fix broken GPIOL cs_bits state (#126)"
......................................................................
Revert "ft2232_spi: Fix broken GPIOL cs_bits state (#126)"
This reverts commit a43e44b6abbe8381be3f3dd20a430973cf8b8ab5.
Nothing was broken. So this breaks everything. Well, actually only
the `csgpiol` parameter. But that is very obvious.
`csgpiol` was added to use a GPIO pin as /CS. But this change impli-
citly hardcoded /CS to ADBUS3.
Change-Id: I9ecdfe227585dda74658c16c96a57dd42d1d78b4
Signed-off-by: Nico Huber <nico.h(a)gmx.de>
---
M ft2232_spi.c
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/93/55693/1
diff --git a/ft2232_spi.c b/ft2232_spi.c
index 2eb735a..4a3a5a4 100644
--- a/ft2232_spi.c
+++ b/ft2232_spi.c
@@ -225,7 +225,7 @@
msg_pspew("Assert CS#\n");
buf[i++] = SET_BITS_LOW;
- buf[i++] = ~ 0x08 & spi_data->cs_bits; /* assert CS (3rd) bit only */
+ buf[i++] = 0 & ~spi_data->cs_bits; /* assertive */
buf[i++] = spi_data->pindir;
/* WREN, OP(PROGRAM, ERASE), ADDR, DATA */
--
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