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Change subject: lspcon_i2c_spi: Extract I2C bus parameter handling
......................................................................
Patch Set 1: Code-Review+2
(1 comment)
File i2c_helper_linux.c:
https://review.coreboot.org/c/flashrom/+/52830/comment/3126eac7_579391b2
PS1, Line 80: * TODO: Move this function to a common place, it is not specific to I2C */
I guess this todo is fixed now in this commit?
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Change subject: nicintel_eeprom.c: Mark 8086:1531 as tested
......................................................................
Patch Set 1:
(1 comment)
Commit Message:
https://review.coreboot.org/c/flashrom/+/52825/comment/05a5c5f1_afbbf165
PS1, Line 9: Reading, erasing and writing works on an i210 NIC of an Asus Z10PA-D8.
> Is it important to have TEST=something something line in commit message? I noticed that some commits […]
The BUG+BRANCH+TEST lines is a Chromium requirement, upstream does not generally care for it so this is optional for them.
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Change subject: nicintel_eeprom.c: Mark 8086:1531 as tested
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Patch Set 1: Code-Review+2
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Change subject: nicintel_eeprom.c: Mark 8086:1531 as tested
......................................................................
Patch Set 1: Code-Review+1
(1 comment)
Commit Message:
https://review.coreboot.org/c/flashrom/+/52825/comment/33534280_8587e226
PS1, Line 9: Reading, erasing and writing works on an i210 NIC of an Asus Z10PA-D8.
Is it important to have TEST=something something line in commit message? I noticed that some commits have it, some don't.
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Change subject: ft2232_spi.c: Implement spi_send_multicommand()
......................................................................
Patch Set 32:
(1 comment)
Patchset:
PS32:
> Not sure if I'm doing something wrong. The patch works so far, but […]
I wondered what device was used for testing so far and
stumbled over this picture[1] mentioned in the original
commit message. There's some 1.36MHz shown in it, so I
tried again with such a low speed (divisor=44) and, tada,
it makes a difference. No idea what is going on inside
that chip. My numbers[2] even suggest that sending the
commands in two packets (original chunksize) is faster
*in my setup*.
[1] https://ibb.co/0c1J25d
[2] https://paste.flashrom.org/view.php?id=3472
NB. What would really increase speed in the tested
scenario (writing random data, hence everything needs
to be erased) is to choose a bigger erase block size.
I have this on my todo list since my very first days
with flashrom. If I drop 4K and 32K blocks from
`flashchips.c`, it's about twice as fast. But as this
is not a common use case, I did not see it as a
priority. OTOH, it always bugs me, for instance when
I switch back and forth between coreboot and another
firmware.
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Change subject: ft2232_spi.c: Implement spi_send_multicommand()
......................................................................
Patch Set 32:
(1 comment)
Patchset:
PS32:
Not sure if I'm doing something wrong. The patch works so far, but
I don't see any speed increase in my setup. This is with an FT2232H,
bcdDevice 7.00 (not sure if that means something) according to lsusb.
Running it at 15MHz (divisor=4) with a W25Q128FV. Read/erase/write
with random data takes about 11:30min. Maybe it's about 1s faster
with these patches, but that could be just noise. I did most tests
on a 256KiB layout region, and there was no visible difference ~12.3s.
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