April 2021 - flashrom-gerrit - mail.coreboot.org

Change in flashrom[master]: Enable dynamic memory allocation checks for cmocka unit tests
by Anastasia Klimchuk (Code Review) March 31, 2021

March 31, 2021

Attention is currently required from: David Hendricks, Edward O'Callaghan. Anastasia Klimchuk has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/51243 ) Change subject: Enable dynamic memory allocation checks for cmocka unit tests ...................................................................... Patch Set 7: (1 comment) Patchset: PS7: I wanted to say thank you to all my reviewers! I see +2s so if you think this can be submitted, could you please submit? (I can’t do it myself). -- To view, visit https://review.coreboot.org/c/flashrom/+/51243 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I0c6b6b8dc17aaee28640e3fca3d1fc9f7feabf5f Gerrit-Change-Number: 51243 Gerrit-PatchSet: 7 Gerrit-Owner: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Daniel Kurtz <djkurtz(a)google.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Daniel Kurtz <djkurtz(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Thomas Heijligen <src(a)posteo.de> Gerrit-CC: Victor Ding <victording(a)chromium.org> Gerrit-Attention: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Attention: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Comment-Date: Thu, 01 Apr 2021 01:59:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in flashrom[master]: tree: Remove forward-declarations of structs for spi masters
by Edward O'Callaghan (Code Review) March 31, 2021

March 31, 2021

Edward O'Callaghan has submitted this change. ( https://review.coreboot.org/c/flashrom/+/51731 ) Change subject: tree: Remove forward-declarations of structs for spi masters ...................................................................... tree: Remove forward-declarations of structs for spi masters Reorder functions to avoid forward-declarations of structs. Similar thing was done earlier for functions declarations, this patch takes care of structs declarations. BUG=b:140394053 TEST=builds objdump -d is identical objdump -s only difference is version number Change-Id: I256bd7c763efc010fc1f29f7c5853f150ac10739 Signed-off-by: Anastasia Klimchuk <aklm(a)chromium.org> Reviewed-on: https://review.coreboot.org/c/flashrom/+/51731 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Nico Huber <nico.h(a)gmx.de> Reviewed-by: Edward O'Callaghan <quasisec(a)chromium.org> --- M mstarddc_spi.c M ni845x_spi.c M usbblaster_spi.c 3 files changed, 218 insertions(+), 225 deletions(-) Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved Edward O'Callaghan: Looks good to me, approved diff --git a/mstarddc_spi.c b/mstarddc_spi.c index 48d6204..c041bd3 100644 --- a/mstarddc_spi.c +++ b/mstarddc_spi.c @@ -31,8 +31,6 @@ #include "programmer.h" #include "spi.h" -static const struct spi_master spi_master_mstarddc; - static int mstarddc_fd; static int mstarddc_addr; static int mstarddc_doreset = 1; @@ -68,6 +66,83 @@ } /* Returns 0 upon success, a negative number upon errors. */ +static int mstarddc_spi_send_command(const struct flashctx *flash, + unsigned int writecnt, + unsigned int readcnt, + const unsigned char *writearr, + unsigned char *readarr) +{ + int ret = 0; + uint8_t *cmd = malloc((writecnt + 1) * sizeof(uint8_t)); + if (cmd == NULL) { + msg_perr("Error allocating memory: errno %d.\n", errno); + ret = -1; + } + + if (!ret && writecnt) { + cmd[0] = MSTARDDC_SPI_WRITE; + memcpy(cmd + 1, writearr, writecnt); + if (write(mstarddc_fd, cmd, writecnt + 1) < 0) { + msg_perr("Error sending write command: errno %d.\n", + errno); + ret = -1; + } + } + + if (!ret && readcnt) { + struct i2c_rdwr_ioctl_data i2c_data; + struct i2c_msg msg[2]; + + cmd[0] = MSTARDDC_SPI_READ; + i2c_data.nmsgs = 2; + i2c_data.msgs = msg; + i2c_data.msgs[0].addr = mstarddc_addr; + i2c_data.msgs[0].len = 1; + i2c_data.msgs[0].flags = 0; + i2c_data.msgs[0].buf = cmd; + i2c_data.msgs[1].addr = mstarddc_addr; + i2c_data.msgs[1].len = readcnt; + i2c_data.msgs[1].flags = I2C_M_RD; + i2c_data.msgs[1].buf = readarr; + + if (ioctl(mstarddc_fd, I2C_RDWR, &i2c_data) < 0) { + msg_perr("Error sending read command: errno %d.\n", + errno); + ret = -1; + } + } + + if (!ret && (writecnt || readcnt)) { + cmd[0] = MSTARDDC_SPI_END; + if (write(mstarddc_fd, cmd, 1) < 0) { + msg_perr("Error sending end command: errno %d.\n", + errno); + ret = -1; + } + } + + /* Do not reset if something went wrong, as it might prevent from + * retrying flashing. */ + if (ret != 0) + mstarddc_doreset = 0; + + if (cmd) + free(cmd); + + return ret; +} + +static const struct spi_master spi_master_mstarddc = { + .max_data_read = 256, + .max_data_write = 256, + .command = mstarddc_spi_send_command, + .multicommand = default_spi_send_multicommand, + .read = default_spi_read, + .write_256 = default_spi_write_256, + .write_aai = default_spi_write_aai, +}; + +/* Returns 0 upon success, a negative number upon errors. */ int mstarddc_spi_init(void) { int ret = 0; @@ -152,81 +227,4 @@ return ret; } -/* Returns 0 upon success, a negative number upon errors. */ -static int mstarddc_spi_send_command(const struct flashctx *flash, - unsigned int writecnt, - unsigned int readcnt, - const unsigned char *writearr, - unsigned char *readarr) -{ - int ret = 0; - uint8_t *cmd = malloc((writecnt + 1) * sizeof(uint8_t)); - if (cmd == NULL) { - msg_perr("Error allocating memory: errno %d.\n", errno); - ret = -1; - } - - if (!ret && writecnt) { - cmd[0] = MSTARDDC_SPI_WRITE; - memcpy(cmd + 1, writearr, writecnt); - if (write(mstarddc_fd, cmd, writecnt + 1) < 0) { - msg_perr("Error sending write command: errno %d.\n", - errno); - ret = -1; - } - } - - if (!ret && readcnt) { - struct i2c_rdwr_ioctl_data i2c_data; - struct i2c_msg msg[2]; - - cmd[0] = MSTARDDC_SPI_READ; - i2c_data.nmsgs = 2; - i2c_data.msgs = msg; - i2c_data.msgs[0].addr = mstarddc_addr; - i2c_data.msgs[0].len = 1; - i2c_data.msgs[0].flags = 0; - i2c_data.msgs[0].buf = cmd; - i2c_data.msgs[1].addr = mstarddc_addr; - i2c_data.msgs[1].len = readcnt; - i2c_data.msgs[1].flags = I2C_M_RD; - i2c_data.msgs[1].buf = readarr; - - if (ioctl(mstarddc_fd, I2C_RDWR, &i2c_data) < 0) { - msg_perr("Error sending read command: errno %d.\n", - errno); - ret = -1; - } - } - - if (!ret && (writecnt || readcnt)) { - cmd[0] = MSTARDDC_SPI_END; - if (write(mstarddc_fd, cmd, 1) < 0) { - msg_perr("Error sending end command: errno %d.\n", - errno); - ret = -1; - } - } - - /* Do not reset if something went wrong, as it might prevent from - * retrying flashing. */ - if (ret != 0) - mstarddc_doreset = 0; - - if (cmd) - free(cmd); - - return ret; -} - -static const struct spi_master spi_master_mstarddc = { - .max_data_read = 256, - .max_data_write = 256, - .command = mstarddc_spi_send_command, - .multicommand = default_spi_send_multicommand, - .read = default_spi_read, - .write_256 = default_spi_write_256, - .write_aai = default_spi_write_aai, -}; - #endif diff --git a/ni845x_spi.c b/ni845x_spi.c index 153e03e..765da8a 100644 --- a/ni845x_spi.c +++ b/ni845x_spi.c @@ -40,8 +40,6 @@ USE_HIGHER }; -static const struct spi_master spi_programmer_ni845x; - static unsigned char CS_number; // use chip select 0 as default static enum USB845x_type device_pid = Unknown_NI845X_Device; @@ -403,103 +401,6 @@ return 0; } -int ni845x_spi_init(void) -{ - char *speed_str = NULL; - char *CS_str = NULL; - char *voltage = NULL; - char *endptr = NULL; - int requested_io_voltage_mV = 1200; // default the IO voltage to 1.2V - int spi_speed_KHz = 1000; // selecting 1 MHz SCK is a good bet - char *serial_number = NULL; // by default open the first connected device - char *ignore_io_voltage_limits_str = NULL; - int32 tmp = 0; - - // read the cs parameter (which Chip select should we use) - CS_str = extract_programmer_param("cs"); - if (CS_str) { - CS_number = CS_str[0] - '0'; - free(CS_str); - if (strlen(CS_str) > 1 || CS_number < 0 || 7 < CS_number) { - msg_perr("Only CS 0-7 supported\n"); - return 1; - } - } - - voltage = extract_programmer_param("voltage"); - if (voltage != NULL) { - requested_io_voltage_mV = parse_voltage(voltage); - free(voltage); - if (requested_io_voltage_mV < 0) - return 1; - } - - serial_number = extract_programmer_param("serial"); - - speed_str = extract_programmer_param("spispeed"); - if (speed_str) { - spi_speed_KHz = strtoul(speed_str, &endptr, 0); - if (*endptr) { - msg_perr("The spispeed parameter passed with invalid format: %s\n", - speed_str); - msg_perr("Please pass the parameter with a simple number in kHz\n"); - return 1; - } - free(speed_str); - } - - ignore_io_voltage_limits = false; - ignore_io_voltage_limits_str = extract_programmer_param("ignore_io_voltage_limits"); - if (ignore_io_voltage_limits_str - && strcmp(ignore_io_voltage_limits_str, "yes") == 0) { - ignore_io_voltage_limits = true; - } - - if (ni845x_spi_open(serial_number, &device_handle)) { - if (serial_number) { - msg_pinfo("Could not find any connected NI USB-8451/8452 with serialnumber: %s!\n", - serial_number); - ni845x_spi_print_available_devices(); - msg_pinfo("Check the S/N field on the bottom of the device,\n" - "or use 'lsusb -v -d 3923:7166 | grep Serial' for USB-8451\n" - "or 'lsusb -v -d 3923:7514 | grep Serial' for USB-8452\n"); - free(serial_number); - } else { - msg_pinfo("Could not find any connected NI USB-845x device!\n"); - } - return 1; - } - free(serial_number); - - // open the SPI config handle - tmp = ni845xSpiConfigurationOpen(&configuration_handle); - if (tmp != 0) { - ni845x_report_error("ni845xSpiConfigurationOpen", tmp); - ni845x_spi_shutdown(NULL); - return 1; - } - - if (usb8452_spi_set_io_voltage(requested_io_voltage_mV, &io_voltage_in_mV, USE_LOWER) < 0) { - ni845x_spi_shutdown(NULL); - return 1; // no alert here usb8452_spi_set_io_voltage already printed that - } - - if (ni845x_spi_set_speed(spi_speed_KHz)) { - msg_perr("Unable to set SPI speed\n"); - ni845x_spi_shutdown(NULL); - return 1; - } - - if (register_shutdown(ni845x_spi_shutdown, NULL)) { - ni845x_spi_shutdown(NULL); - return 1; - } - - register_spi_master(&spi_programmer_ni845x); - - return 0; -} - static void ni845x_warn_over_max_voltage(const struct flashctx *flash) { if (device_pid == USB8451) { @@ -636,3 +537,100 @@ .write_256 = default_spi_write_256, .write_aai = default_spi_write_aai, }; + +int ni845x_spi_init(void) +{ + char *speed_str = NULL; + char *CS_str = NULL; + char *voltage = NULL; + char *endptr = NULL; + int requested_io_voltage_mV = 1200; // default the IO voltage to 1.2V + int spi_speed_KHz = 1000; // selecting 1 MHz SCK is a good bet + char *serial_number = NULL; // by default open the first connected device + char *ignore_io_voltage_limits_str = NULL; + int32 tmp = 0; + + // read the cs parameter (which Chip select should we use) + CS_str = extract_programmer_param("cs"); + if (CS_str) { + CS_number = CS_str[0] - '0'; + free(CS_str); + if (strlen(CS_str) > 1 || CS_number < 0 || 7 < CS_number) { + msg_perr("Only CS 0-7 supported\n"); + return 1; + } + } + + voltage = extract_programmer_param("voltage"); + if (voltage != NULL) { + requested_io_voltage_mV = parse_voltage(voltage); + free(voltage); + if (requested_io_voltage_mV < 0) + return 1; + } + + serial_number = extract_programmer_param("serial"); + + speed_str = extract_programmer_param("spispeed"); + if (speed_str) { + spi_speed_KHz = strtoul(speed_str, &endptr, 0); + if (*endptr) { + msg_perr("The spispeed parameter passed with invalid format: %s\n", + speed_str); + msg_perr("Please pass the parameter with a simple number in kHz\n"); + return 1; + } + free(speed_str); + } + + ignore_io_voltage_limits = false; + ignore_io_voltage_limits_str = extract_programmer_param("ignore_io_voltage_limits"); + if (ignore_io_voltage_limits_str + && strcmp(ignore_io_voltage_limits_str, "yes") == 0) { + ignore_io_voltage_limits = true; + } + + if (ni845x_spi_open(serial_number, &device_handle)) { + if (serial_number) { + msg_pinfo("Could not find any connected NI USB-8451/8452 with serialnumber: %s!\n", + serial_number); + ni845x_spi_print_available_devices(); + msg_pinfo("Check the S/N field on the bottom of the device,\n" + "or use 'lsusb -v -d 3923:7166 | grep Serial' for USB-8451\n" + "or 'lsusb -v -d 3923:7514 | grep Serial' for USB-8452\n"); + free(serial_number); + } else { + msg_pinfo("Could not find any connected NI USB-845x device!\n"); + } + return 1; + } + free(serial_number); + + // open the SPI config handle + tmp = ni845xSpiConfigurationOpen(&configuration_handle); + if (tmp != 0) { + ni845x_report_error("ni845xSpiConfigurationOpen", tmp); + ni845x_spi_shutdown(NULL); + return 1; + } + + if (usb8452_spi_set_io_voltage(requested_io_voltage_mV, &io_voltage_in_mV, USE_LOWER) < 0) { + ni845x_spi_shutdown(NULL); + return 1; // no alert here usb8452_spi_set_io_voltage already printed that + } + + if (ni845x_spi_set_speed(spi_speed_KHz)) { + msg_perr("Unable to set SPI speed\n"); + ni845x_spi_shutdown(NULL); + return 1; + } + + if (register_shutdown(ni845x_spi_shutdown, NULL)) { + ni845x_spi_shutdown(NULL); + return 1; + } + + register_spi_master(&spi_programmer_ni845x); + + return 0; +} diff --git a/usbblaster_spi.c b/usbblaster_spi.c index 58a8a0e..020c3bf 100644 --- a/usbblaster_spi.c +++ b/usbblaster_spi.c @@ -51,8 +51,6 @@ {0} }; -static const struct spi_master spi_master_usbblaster; - static struct ftdi_context ftdic; // command bytes @@ -72,51 +70,6 @@ return ((b * 0x0802LU & 0x22110LU) | (b * 0x8020LU & 0x88440LU)) * 0x10101LU >> 16; } - -/* Returns 0 upon success, a negative number upon errors. */ -int usbblaster_spi_init(void) -{ - uint8_t buf[BUF_SIZE + 1]; - - if (ftdi_init(&ftdic) < 0) - return -1; - - if (ftdi_usb_open(&ftdic, ALTERA_VID, ALTERA_USBBLASTER_PID) < 0) { - msg_perr("Failed to open USB-Blaster: %s\n", ftdic.error_str); - return -1; - } - - if (ftdi_usb_reset(&ftdic) < 0) { - msg_perr("USB-Blaster reset failed\n"); - return -1; - } - - if (ftdi_set_latency_timer(&ftdic, 2) < 0) { - msg_perr("USB-Blaster set latency timer failed\n"); - return -1; - } - - if (ftdi_write_data_set_chunksize(&ftdic, 4096) < 0 || - ftdi_read_data_set_chunksize(&ftdic, BUF_SIZE) < 0) { - msg_perr("USB-Blaster set chunk size failed\n"); - return -1; - } - - memset(buf, 0, sizeof(buf)); - buf[sizeof(buf)-1] = BIT_LED | BIT_CS; - if (ftdi_write_data(&ftdic, buf, sizeof(buf)) < 0) { - msg_perr("USB-Blaster reset write failed\n"); - return -1; - } - if (ftdi_read_data(&ftdic, buf, sizeof(buf)) < 0) { - msg_perr("USB-Blaster reset read failed\n"); - return -1; - } - - register_spi_master(&spi_master_usbblaster); - return 0; -} - static int send_write(unsigned int writecnt, const unsigned char *writearr) { uint8_t buf[BUF_SIZE]; @@ -217,4 +170,48 @@ .write_aai = default_spi_write_aai, }; +/* Returns 0 upon success, a negative number upon errors. */ +int usbblaster_spi_init(void) +{ + uint8_t buf[BUF_SIZE + 1]; + + if (ftdi_init(&ftdic) < 0) + return -1; + + if (ftdi_usb_open(&ftdic, ALTERA_VID, ALTERA_USBBLASTER_PID) < 0) { + msg_perr("Failed to open USB-Blaster: %s\n", ftdic.error_str); + return -1; + } + + if (ftdi_usb_reset(&ftdic) < 0) { + msg_perr("USB-Blaster reset failed\n"); + return -1; + } + + if (ftdi_set_latency_timer(&ftdic, 2) < 0) { + msg_perr("USB-Blaster set latency timer failed\n"); + return -1; + } + + if (ftdi_write_data_set_chunksize(&ftdic, 4096) < 0 || + ftdi_read_data_set_chunksize(&ftdic, BUF_SIZE) < 0) { + msg_perr("USB-Blaster set chunk size failed\n"); + return -1; + } + + memset(buf, 0, sizeof(buf)); + buf[sizeof(buf)-1] = BIT_LED | BIT_CS; + if (ftdi_write_data(&ftdic, buf, sizeof(buf)) < 0) { + msg_perr("USB-Blaster reset write failed\n"); + return -1; + } + if (ftdi_read_data(&ftdic, buf, sizeof(buf)) < 0) { + msg_perr("USB-Blaster reset read failed\n"); + return -1; + } + + register_spi_master(&spi_master_usbblaster); + return 0; +} + #endif -- To view, visit https://review.coreboot.org/c/flashrom/+/51731 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I256bd7c763efc010fc1f29f7c5853f150ac10739 Gerrit-Change-Number: 51731 Gerrit-PatchSet: 3 Gerrit-Owner: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in flashrom[master]: tree: Remove forward-declarations of structs for spi masters
by Edward O'Callaghan (Code Review) March 31, 2021

March 31, 2021

Attention is currently required from: Anastasia Klimchuk. Edward O'Callaghan has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/51731 ) Change subject: tree: Remove forward-declarations of structs for spi masters ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/flashrom/+/51731 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I256bd7c763efc010fc1f29f7c5853f150ac10739 Gerrit-Change-Number: 51731 Gerrit-PatchSet: 2 Gerrit-Owner: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Comment-Date: Thu, 01 Apr 2021 01:17:39 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in flashrom[master]: Enable dynamic memory allocation checks for cmocka unit tests
by Anastasia Klimchuk (Code Review) March 31, 2021

March 31, 2021

Attention is currently required from: David Hendricks, Edward O'Callaghan. Anastasia Klimchuk has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/51243 ) Change subject: Enable dynamic memory allocation checks for cmocka unit tests ...................................................................... Patch Set 7: (1 comment) File meson.build: https://review.coreboot.org/c/flashrom/+/51243/comment/af2e565f_3972543d PS6, Line 477: -include > Ah, sorry. I'm still very used to the comfort and pain of having […] I am fine with no-spaces, it aligns with -D definitions (like the ones above -DCONFIG_DEFAULT_PROGRAMMER_ARGS="" there is no space between D and the rest). -- To view, visit https://review.coreboot.org/c/flashrom/+/51243 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I0c6b6b8dc17aaee28640e3fca3d1fc9f7feabf5f Gerrit-Change-Number: 51243 Gerrit-PatchSet: 7 Gerrit-Owner: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Daniel Kurtz <djkurtz(a)google.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Daniel Kurtz <djkurtz(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Thomas Heijligen <src(a)posteo.de> Gerrit-CC: Victor Ding <victording(a)chromium.org> Gerrit-Attention: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Attention: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Comment-Date: Thu, 01 Apr 2021 00:49:47 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-MessageType: comment

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Change in flashrom[master]: lspcon_i2c_spi: support a devpath option
by Peter Marheine (Code Review) March 31, 2021

March 31, 2021

Attention is currently required from: Angel Pons. Peter Marheine has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/51967 ) Change subject: lspcon_i2c_spi: support a devpath option ...................................................................... Patch Set 2: (4 comments) File i2c_helper_linux.c: https://review.coreboot.org/c/flashrom/+/51967/comment/f3f869b9_d6696f3e PS1, Line 46: goto err; > `goto` isn't necessary here, just return `fd`. Done https://review.coreboot.org/c/flashrom/+/51967/comment/bd0b9247_22fa4da3 PS1, Line 54: goto err; > Same here, just return `err`. Done https://review.coreboot.org/c/flashrom/+/51967/comment/ea7c850c_6bde3ec2 PS1, Line 58: return ret ? ret : fd; > And return `fd` here. Done File lspcon_i2c_spi.c: https://review.coreboot.org/c/flashrom/+/51967/comment/0b3378f0_060292fc PS1, Line 486: msg_perr("%s: one of devpath or bus must be specified\n", __func__); > If both arguments are specified, `bus` is silently ignored. […] Revised further so invalid bus values are distinct from unspecified, allowing the two options to be mutually exclusive. -- To view, visit https://review.coreboot.org/c/flashrom/+/51967 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Id2adf8a307b9205ce5e5804a6c3e22f19d0c34c9 Gerrit-Change-Number: 51967 Gerrit-PatchSet: 2 Gerrit-Owner: Peter Marheine <pmarheine(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Daniel Campello <campello(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Thu, 01 Apr 2021 00:12:15 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in flashrom[master]: lspcon_i2c_spi: support a devpath option
by Peter Marheine (Code Review) March 31, 2021

March 31, 2021

Hello build bot (Jenkins), Edward O'Callaghan, Angel Pons, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/flashrom/+/51967 to look at the new patch set (#2). Change subject: lspcon_i2c_spi: support a devpath option ...................................................................... lspcon_i2c_spi: support a devpath option Some callers may find it easier to provide the path to an I2C device at which to communicate with the device, rather than specify the bus number- doing so might involve trying to parse a path to extract the number only for flashrom to do the reverse, which is error-prone and unnecessary. This change adds support for a `devpath` option, continuing to allow `bus` and requiring only one of them be specified. TEST=Verified --flash-size outputs correct values with both devpath=/dev/i2c-7 and bus=7, as well as noting that one is required if neither is specified and only one may be specified if both are given. Signed-off-by: Peter Marheine <pmarheine(a)chromium.org> Change-Id: Id2adf8a307b9205ce5e5804a6c3e22f19d0c34c9 --- M i2c_helper.h M i2c_helper_linux.c M lspcon_i2c_spi.c 3 files changed, 79 insertions(+), 50 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/67/51967/2 -- To view, visit https://review.coreboot.org/c/flashrom/+/51967 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Id2adf8a307b9205ce5e5804a6c3e22f19d0c34c9 Gerrit-Change-Number: 51967 Gerrit-PatchSet: 2 Gerrit-Owner: Peter Marheine <pmarheine(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Daniel Campello <campello(a)chromium.org> Gerrit-MessageType: newpatchset

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