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Edward O'Callaghan has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/23021 )
Change subject: layout: Add -i <region>[:<file>] support
......................................................................
Patch Set 25: Code-Review+1
(2 comments)
File cli_classic.c:
https://review.coreboot.org/c/flashrom/+/23021/comment/46cecdf0_6bc96ece
PS25, Line 140: static char *get_optional_filename(char *argv[])
: {
: char *filename = NULL;
:
: if (optarg == NULL && argv[optind] != NULL && argv[optind][0] != '-')
: filename = strdup(argv[optind++]);
: else if (optarg != NULL)
: filename = strdup(optarg);
:
: return filename;
: }
Not a overtly strong feeling here however should this part of the story perhaps be a separate patch? Even if it is small, it is however a specific singular purpose change to the cli that perhaps stands on its own merit.
https://review.coreboot.org/c/flashrom/+/23021/comment/586f1201_e6a64de9
PS25, Line 203: 'i'}
I guess this would be a breaking change, I would defer to Nico and Angels judgement here.
However my suggestion is that we use capital `I` for "include" as to avoid changing lower case `i` from meaning "image".
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Thomas Walker has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/52310 )
Change subject: flashchips: Add Spansion/Cypress S25FL256L
......................................................................
Patch Set 3:
(9 comments)
Commit Message:
https://review.coreboot.org/c/flashrom/+/52310/comment/d1e115b2_b4fc578d
PS1, Line 7: Added support for Spansion/Cypress chip S25FL256L.
> Commit messages are written in present tense, do not end with a period and usually have a prefix. […]
Done
https://review.coreboot.org/c/flashrom/+/52310/comment/280e510d_abd2482c
PS1, Line 9: Testing has been conducted on ~60 individual chips and confirmed as working.
> One thing about write tests: flashrom compares the current contents of the flash chip to the provide […]
I wont provide the full log of the random write test, however I have confirmed that it worked correctly and stated VERIFIED at the end.
Patchset:
PS1:
> Welcome!
Thank you, I'm pretty new to contributing to public repositories, and this review process is a little daunting, so forgive me for my mistakes!
Patchset:
PS3:
Changes made as per Angel's suggestions.
File flashchips.c:
https://review.coreboot.org/c/flashrom/+/52310/comment/40522d42_ee2ef3aa
PS1, Line 16387: |
> Please add spaces around `|`
Done
https://review.coreboot.org/c/flashrom/+/52310/comment/1249e735_5e51ca8c
PS1, Line 16391: .block_erasers =
> Many block erasers are missing, and only the first entry is correct. […]
Added spi_block_erase_53, let me know if there are any corrections that need to be made.
https://review.coreboot.org/c/flashrom/+/52310/comment/98fafb0d_5e60d641
PS1, Line 16401: spi_prettyprint_status_register_plain
> spi_prettyprint_status_register_bp3_srwd
Done
https://review.coreboot.org/c/flashrom/+/52310/comment/7e51e5b6_08229493
PS1, Line 16402: spi_disable_blockprotect
> spi_disable_blockprotect_bp3_srwd
Done
https://review.coreboot.org/c/flashrom/+/52310/comment/e026d2f7_4a143e1d
PS1, Line 16406: },
> Please use tabs for indentation
Done
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Hello build bot (Jenkins), Nico Huber,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/flashrom/+/52310
to look at the new patch set (#3).
Change subject: flashchips: Add Spansion/Cypress S25FL256L
......................................................................
flashchips: Add Spansion/Cypress S25FL256L
Conducted random write test using Adafruit FT232H programmer.
Confirmed read/write/erase/probe and VERIFIED on completion.
Signed-off-by: Thomas Walker <thh.walker(a)gmail.com>
Change-Id: I4e8cba554d0590c94dac92aa91e9ab400efca281
---
M chipdrivers.h
M flashchips.c
M flashchips.h
M spi.h
M spi25.c
5 files changed, 60 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/10/52310/3
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Attention is currently required from: Nico Huber, Thomas Walker.
Hello build bot (Jenkins), Nico Huber,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/flashrom/+/52310
to look at the new patch set (#2).
Change subject: Added support for Spansion/Cypress chip S25FL256L.
......................................................................
Added support for Spansion/Cypress chip S25FL256L.
Conducted random write test using Adafruit FT232H programmer.
Confirmed read/write/erase/probe and VERIFIED on completion.
Signed-off-by: Thomas Walker <thh.walker(a)gmail.com>
Change-Id: I4e8cba554d0590c94dac92aa91e9ab400efca281
---
M chipdrivers.h
M flashchips.c
M flashchips.h
M spi.h
M spi25.c
5 files changed, 60 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/10/52310/2
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Nico Huber has submitted this change. ( https://review.coreboot.org/c/flashrom/+/51978 )
Change subject: test_build.sh: use sh from env
......................................................................
test_build.sh: use sh from env
Change-Id: I3897b8d980425ecbb89b238d4a766f628cf9d3e6
Signed-off-by: Thomas Heijligen <thomas.heijligen(a)secunet.de>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/51978
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---
M test_build.sh
1 file changed, 1 insertion(+), 1 deletion(-)
Approvals:
build bot (Jenkins): Verified
Paul Menzel: Looks good to me, but someone else must approve
Angel Pons: Looks good to me, approved
diff --git a/test_build.sh b/test_build.sh
index 0e43cd3..8f11ccd 100755
--- a/test_build.sh
+++ b/test_build.sh
@@ -1,4 +1,4 @@
-#!/bin/sh
+#!/usr/bin/env sh
set -e
make CONFIG_EVERYTHING=yes WARNERROR=yes
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Change subject: test_build.sh: use sh from env
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
Given that we exactly know the environment in which
test_build.sh runs (cf. CB:46894), I don't think this
makes any difference.
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Change subject: test_build.sh: use sh from env
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
> Which ones? I'm curious. […]
with an absolute path as interpreter you are sure that your script will run by that binary, or the linked one. With /usr/bin/env the first suitable binary with this name in your path is chosen to run the script.
On "/bin/sh" it's not this necessary, since most distributions provide /bin/sh for compatibility. Other interpreter may be only available though PATH and not as /bin/xyz
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Change subject: Added support for Spansion/Cypress chip S25FL256L.
......................................................................
Patch Set 1:
(8 comments)
Commit Message:
https://review.coreboot.org/c/flashrom/+/52310/comment/d1e017ff_a91c06e1
PS1, Line 7: Added support for Spansion/Cypress chip S25FL256L.
Commit messages are written in present tense, do not end with a period and usually have a prefix. I'd suggest:
flashchips: Add Spansion/Cypress S25FL256L
https://review.coreboot.org/c/flashrom/+/52310/comment/69990759_7a45c3f5
PS1, Line 9: Testing has been conducted on ~60 individual chips and confirmed as working.
One thing about write tests: flashrom compares the current contents of the flash chip to the provided data. If they are equal, flashrom does nothing.
For example, you may see something like this in a verbose log:
0x000000-0x000fff:S
The S tells us that the block was *S*kipped. To really test writes, one could use random data, e.g.
dd if=/dev/urandom bs=1M count=32 of=random.rom
flashrom -p ... -w random.rom
If flashrom says VERIFIED, we're all good.
Patchset:
PS1:
Welcome!
File flashchips.c:
https://review.coreboot.org/c/flashrom/+/52310/comment/b82cff71_03b288fa
PS1, Line 16387: |
Please add spaces around `|`
https://review.coreboot.org/c/flashrom/+/52310/comment/af561af6_19e55bfd
PS1, Line 16391: .block_erasers =
Many block erasers are missing, and only the first entry is correct. This happened to work because flashrom only uses the other block erasers when the first one fails.
From the datasheet, the correct block erasers should be, in order:
.block_erasers =
{
{
.eraseblocks = { {4 * 1024, 8192} },
.block_erase = spi_block_erase_21,
}, {
.eraseblocks = { {4 * 1024, 8192} },
.block_erase = spi_block_erase_20,
}, {
.eraseblocks = { {32 * 1024, 1024} },
.block_erase = spi_block_erase_53,
}, {
.eraseblocks = { {32 * 1024, 1024} },
.block_erase = spi_block_erase_52,
}, {
.eraseblocks = { {64 * 1024, 512} },
.block_erase = spi_block_erase_dc,
}, {
.eraseblocks = { {64 * 1024, 512} },
.block_erase = spi_block_erase_d8,
}, {
.eraseblocks = { {32 * 1024 * 1024, 1} },
.block_erase = spi_block_erase_60,
}, {
.eraseblocks = { {32 * 1024 * 1024, 1} },
.block_erase = spi_block_erase_c7,
}
},
Other chips place the 4BA (4-Byte Address) opcodes first, so I did the same here.
https://review.coreboot.org/c/flashrom/+/52310/comment/7fe33be1_b808e25f
PS1, Line 16401: spi_prettyprint_status_register_plain
spi_prettyprint_status_register_bp3_srwd
https://review.coreboot.org/c/flashrom/+/52310/comment/49e4ffce_f6adb287
PS1, Line 16402: spi_disable_blockprotect
spi_disable_blockprotect_bp3_srwd
https://review.coreboot.org/c/flashrom/+/52310/comment/225fd020_3bb6432c
PS1, Line 16406: },
Please use tabs for indentation
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