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Change subject: chipset_enable.c: Add IDs for H310C and B365 PCHs
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Patch Set 1: Code-Review+2
(1 comment)
Commit Message:
https://review.coreboot.org/c/flashrom/+/52605/comment/16f5d2cc_1cc9892c
PS1, Line 7: chipset_enable.c: Add IDs for H310C and B365 PCHs
As it's not in the datasheet, please mention where the 0xa2cc was
found.
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Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/52470 )
Change subject: hwaccess.c: Fix PowerPC memory barrier
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Patch Set 3:
(1 comment)
Commit Message:
https://review.coreboot.org/c/flashrom/+/52470/comment/919b1eca_51ba6857
PS1, Line 10: rotten link.
> That seems extremely likely Angel, good spot! It is very unfortunate the toolchain defaults of a giv […]
If you know any alternative to papering over the deficiencies of all the
environments flashrom supports, I'd be happy to listen. Just stating that
the current practice isn't ideal doesn't fix anything.
For sparc we got one emulation target working: CB:52485.
The infrastructure to build test flashrom on many targets exists since
the 1.0 release. That you chose to ignore it over the last years is very
unfortunate.
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