September 2020 - flashrom-gerrit

Change in flashrom[master]: ft2232_spi.c: Pack WREN and op in one ftdi_write_data() call
by Angel Pons (Code Review) 21 Sep '20

21 Sep '20

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/40477 ) Change subject: ft2232_spi.c: Pack WREN and op in one ftdi_write_data() call ...................................................................... Patch Set 14: Code-Review+1 (3 comments) > Patch Set 14: > > @AngelPons: > Would be great to get some feedback and/or get this merged. See my last post to get a quick overview of this change. Sorry, I've forgotten about these changes. I'll take a look as soon as I can, because it's been a long while. https://review.coreboot.org/c/flashrom/+/40477/8/ft2232_spi.c File ft2232_spi.c: https://review.coreboot.org/c/flashrom/+/40477/8/ft2232_spi.c@473 PS8, Line 473: static > This is related to Line 541 and following lines. It is explained (shortly) in Line 542. […] Ack https://review.coreboot.org/c/flashrom/+/40477/14/ft2232_spi.c File ft2232_spi.c: https://review.coreboot.org/c/flashrom/+/40477/14/ft2232_spi.c@480 PS14, Line 480: /* : * 280 bytes = : * + 9 B (CMD) : * + 1 B (WREN) : * + 9 B (CMD) : * + 1 B (op) \ : * + 4 B (addr) | = writecnt : * + 256 B (page data) / : * : * With op: PageProgram or Erase; CMD: FTDI-Chip commands : */ nit: I'd place this before the assignment to `bufsize`. And please align correctly (there's one tab too many) https://review.coreboot.org/c/flashrom/+/40477/14/ft2232_spi.c@555 PS14, Line 555: /* Return to get second op (Program or Erase) without : * resetting buf nor i*/ Comment style should be: /* * Return to get second op (Program or Erase) * without resetting buf nor i */ -- To view, visit https://review.coreboot.org/c/flashrom/+/40477 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Ie4a07499ec5ef0af23818593f45dc427285a9e8a Gerrit-Change-Number: 40477 Gerrit-PatchSet: 14 Gerrit-Owner: Simon Buhrow Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Georgi <pgeorgi(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Mon, 21 Sep 2020 11:34:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Simon Buhrow Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in flashrom[master]: ft2232_spi.c: Pack WREN and op in one ftdi_write_data() call
by Simon Buhrow (Code Review) 21 Sep '20

21 Sep '20

Simon Buhrow has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/40477 ) Change subject: ft2232_spi.c: Pack WREN and op in one ftdi_write_data() call ...................................................................... Patch Set 14: @AngelPons: Would be great to get some feedback and/or get this merged. See my last post to get a quick overview of this change. -- To view, visit https://review.coreboot.org/c/flashrom/+/40477 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Ie4a07499ec5ef0af23818593f45dc427285a9e8a Gerrit-Change-Number: 40477 Gerrit-PatchSet: 14 Gerrit-Owner: Simon Buhrow Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Georgi <pgeorgi(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Mon, 21 Sep 2020 08:10:28 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in flashrom[master]: cbtable.c: don't assume high addresses can fully map 1MB
by Edward O'Callaghan (Code Review) 18 Sep '20

18 Sep '20

Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/45521 ) Change subject: cbtable.c: don't assume high addresses can fully map 1MB ...................................................................... cbtable.c: don't assume high addresses can fully map 1MB I do not know a clean way to compose find_lb_table() and find_lb_table_remap() or why this cannot always been done. However this is a fix ported from downstream found here: https://chromium-review.googlesource.com/685608 Change-Id: Ibf2323a0a793f693928b81c64acd09bb932a6b98 Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> --- M cbtable.c 1 file changed, 61 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/21/45521/1 diff --git a/cbtable.c b/cbtable.c index 6185f12..6dd4059 100644 --- a/cbtable.c +++ b/cbtable.c @@ -205,8 +205,68 @@ msg_pdbg("Found coreboot table at 0x%08lx.\n", addr); return head; + }; + + return NULL; +} + +static struct lb_header *find_lb_table_remap(unsigned long start_addr, + uint8_t **table_area) +{ + size_t offset; + unsigned long addr, end; + size_t mapping_size; + void *base; + + mapping_size = getpagesize(); + offset = start_addr % getpagesize(); + start_addr -= offset; + + base = physmap_ro("high tables", start_addr, mapping_size); + if (ERROR_PTR == base) { + msg_perr("Failed getting access to coreboot high tables.\n"); + return NULL; } + for (addr = offset, end = getpagesize(); addr < end; addr += 16) { + struct lb_record *recs; + struct lb_header *head; + + /* No more headers to check. */ + if (end - addr < sizeof(*head)) + return NULL; + + head = (struct lb_header *)(((char *)base) + addr); + + if (!lb_header_valid(head, addr)) + continue; + + if (mapping_size - addr < head->table_bytes + sizeof(*head)) { + size_t prev_mapping_size = mapping_size; + mapping_size = head->table_bytes + sizeof(*head); + mapping_size += addr; + mapping_size += getpagesize() - + (mapping_size % getpagesize()); + physunmap(base, prev_mapping_size); + base = physmap_ro("high tables", start_addr, + mapping_size); + if (ERROR_PTR == base) { + msg_perr("Failed getting access to coreboot high tables.\n"); + return NULL; + } + } + + head = (struct lb_header *)(((char *)base) + addr); + recs = + (struct lb_record *)(((char *)base) + addr + sizeof(*head)); + if (!lb_table_valid(head, recs)) + continue; + msg_pdbg("Found coreboot table at 0x%08lx.\n", addr); + *table_area = base; + return head; + } + + physunmap(base, mapping_size); return NULL; } @@ -283,15 +343,9 @@ (((char *)lb_table) + lb_table->header_bytes); if (forward->tag == LB_TAG_FORWARD) { start = forward->forward; - start &= ~(getpagesize() - 1); physunmap_unaligned(table_area, BYTES_TO_MAP); // FIXME: table_area is never unmapped below, nor is it unmapped above in the no-forward case - table_area = physmap_ro_unaligned("high tables", start, BYTES_TO_MAP); - if (ERROR_PTR == table_area) { - msg_perr("Failed getting access to coreboot high tables.\n"); - return -1; - } - lb_table = find_lb_table(table_area, 0x00000, 0x1000); + lb_table = find_lb_table_remap(start, &table_area); } } -- To view, visit https://review.coreboot.org/c/flashrom/+/45521 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Ibf2323a0a793f693928b81c64acd09bb932a6b98 Gerrit-Change-Number: 45521 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: newchange

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Change in flashrom[master]: tests: Update licence headers
by Nikolai Artemiev (Code Review) 17 Sep '20

17 Sep '20

Nikolai Artemiev has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/45438 ) Change subject: tests: Update licence headers ...................................................................... tests: Update licence headers Signed-off-by: Nikolai Artemiev <nartemiev(a)google.com> Change-Id: Ia964279ace569b4b93f4e2919c1c228a9b621745 --- M tests/flashrom.c M tests/helpers.c M tests/include/test.h M tests/meson.build M tests/spi25.c M tests/tests.c M tests/tests.h 7 files changed, 101 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/38/45438/1 diff --git a/tests/flashrom.c b/tests/flashrom.c index ad46dd8..50464dd 100644 --- a/tests/flashrom.c +++ b/tests/flashrom.c @@ -1,3 +1,18 @@ +/* + * This file is part of the flashrom project. + * + * Copyright 2020 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + #include <include/test.h> #include "programmer.h" diff --git a/tests/helpers.c b/tests/helpers.c index ab0863f..a920c15 100644 --- a/tests/helpers.c +++ b/tests/helpers.c @@ -1,3 +1,18 @@ +/* + * This file is part of the flashrom project. + * + * Copyright 2020 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + #include <include/test.h> #include "flash.h" diff --git a/tests/include/test.h b/tests/include/test.h index b4e0dd2..24fa963 100644 --- a/tests/include/test.h +++ b/tests/include/test.h @@ -1,5 +1,17 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* This file is part of the coreboot project. */ +/* + * This file is part of the flashrom project. + * + * Copyright 2020 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ #ifndef _TESTS_TEST_H #define _TESTS_TEST_H diff --git a/tests/meson.build b/tests/meson.build index b1f9fda..f0cb76d 100644 --- a/tests/meson.build +++ b/tests/meson.build @@ -1,3 +1,16 @@ +# This file is part of the flashrom project. +# +# Copyright 2020 Google LLC +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. + root_includes = include_directories('../subprojects') srcs = [ diff --git a/tests/spi25.c b/tests/spi25.c index aa1eea0..6ad0357 100644 --- a/tests/spi25.c +++ b/tests/spi25.c @@ -1,3 +1,18 @@ +/* + * This file is part of the flashrom project. + * + * Copyright 2020 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + #include <include/test.h> #include "programmer.h" diff --git a/tests/tests.c b/tests/tests.c index 1a6b65f..3124607 100644 --- a/tests/tests.c +++ b/tests/tests.c @@ -1,5 +1,17 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* This file is part of the coreboot project. */ +/* + * This file is part of the flashrom project. + * + * Copyright 2020 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ #include <include/test.h> #include "tests.h" diff --git a/tests/tests.h b/tests/tests.h index 107cb51..cb905fd 100644 --- a/tests/tests.h +++ b/tests/tests.h @@ -1,3 +1,18 @@ +/* + * This file is part of the flashrom project. + * + * Copyright 2020 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + #ifndef TESTS_H #define TESTS_H -- To view, visit https://review.coreboot.org/c/flashrom/+/45438 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Ia964279ace569b4b93f4e2919c1c228a9b621745 Gerrit-Change-Number: 45438 Gerrit-PatchSet: 1 Gerrit-Owner: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-MessageType: newchange

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Change in flashrom[master]: tests: Clear ID cache before trying to fetch chip ID a second time
by Patrick Georgi (Code Review) 16 Sep '20

16 Sep '20

Patrick Georgi has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/45431 ) Change subject: tests: Clear ID cache before trying to fetch chip ID a second time ...................................................................... tests: Clear ID cache before trying to fetch chip ID a second time Without that, the code never calls into spi_send_command (because everything's known already) and so the expected return values are never returned. Change-Id: Iba6a56774ce5b51e0f7072b4600a9479cdabf8c7 Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> --- M tests/spi25.c 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/31/45431/1 diff --git a/tests/spi25.c b/tests/spi25.c index aa1eea0..362f5c6 100644 --- a/tests/spi25.c +++ b/tests/spi25.c @@ -129,6 +129,7 @@ (void) state; /* unused */ /* setup initial test state. */ + clear_spi_id_cache(); struct flashctx flashctx = { .chip = &mock_chip }; expect_memory(__wrap_spi_send_command, flash, &flashctx, sizeof(flashctx)); -- To view, visit https://review.coreboot.org/c/flashrom/+/45431 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Iba6a56774ce5b51e0f7072b4600a9479cdabf8c7 Gerrit-Change-Number: 45431 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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Change in flashrom[master]: dummyflasher.c: Factor out global state
by Lachlan Bishop (Code Review) 14 Sep '20

14 Sep '20

Lachlan Bishop has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/45230 ) Change subject: dummyflasher.c: Factor out global state ...................................................................... dummyflasher.c: Factor out global state Moves global state into spi_master data. Change-Id: I972b085875f1277d9ff33326669d2676a3bcd3aa Signed-off-by: Lachlan Bishop <lxb(a)google.com> --- M dummyflasher.c 1 file changed, 189 insertions(+), 169 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/30/45230/1 diff --git a/dummyflasher.c b/dummyflasher.c index 85908af..236861d 100644 --- a/dummyflasher.c +++ b/dummyflasher.c @@ -47,24 +47,29 @@ EMULATE_WINBOND_W25Q128FV, EMULATE_VARIABLE_SIZE, }; -static enum emu_chip emu_chip = EMULATE_NONE; -static char *emu_persistent_image = NULL; -static unsigned int emu_chip_size = 0; -static int emu_modified = 0; /* is the image modified since reading it? */ -#if EMULATE_SPI_CHIP -static unsigned int emu_max_byteprogram_size = 0; -static unsigned int emu_max_aai_size = 0; -static unsigned int emu_jedec_se_size = 0; -static unsigned int emu_jedec_be_52_size = 0; -static unsigned int emu_jedec_be_d8_size = 0; -static unsigned int emu_jedec_ce_60_size = 0; -static unsigned int emu_jedec_ce_c7_size = 0; -static unsigned char spi_blacklist[256]; -static unsigned char spi_ignorelist[256]; -static unsigned int spi_blacklist_size = 0; -static unsigned int spi_ignorelist_size = 0; -static uint8_t emu_status = 0; +struct emu_data { + enum emu_chip emu_chip; + char *emu_persistent_image; + unsigned int emu_chip_size; + int emu_modified; /* is the image modified since reading it? */ +#if EMULATE_SPI_CHIP + unsigned int emu_max_byteprogram_size; + unsigned int emu_max_aai_size; + unsigned int emu_jedec_se_size; + unsigned int emu_jedec_be_52_size; + unsigned int emu_jedec_be_d8_size; + unsigned int emu_jedec_ce_60_size; + unsigned int emu_jedec_ce_c7_size; + unsigned char spi_blacklist[256]; + unsigned char spi_ignorelist[256]; + unsigned int spi_blacklist_size; + unsigned int spi_ignorelist_size; + uint8_t emu_status; +#endif +}; + +#if EMULATE_SPI_CHIP /* A legit complete SFDP table based on the MX25L6436E (rev. 1.8) datasheet. */ static const uint8_t sfdp_table[] = { 0x53, 0x46, 0x44, 0x50, // @0x00: SFDP signature @@ -109,7 +114,7 @@ static uint32_t dummy_chip_readl(const struct flashctx *flash, const chipaddr addr); static void dummy_chip_readn(const struct flashctx *flash, uint8_t *buf, const chipaddr addr, size_t len); -static const struct spi_master spi_master_dummyflasher = { +static struct spi_master spi_master_dummyflasher = { .features = SPI_MASTER_4BA, .max_data_read = MAX_DATA_READ_UNLIMITED, .max_data_write = MAX_DATA_UNSPECIFIED, @@ -137,12 +142,15 @@ { msg_pspew("%s\n", __func__); #if EMULATE_CHIP - if (emu_chip != EMULATE_NONE) { - if (emu_persistent_image && emu_modified) { - msg_pdbg("Writing %s\n", emu_persistent_image); - write_buf_to_file(flashchip_contents, emu_chip_size, emu_persistent_image); - free(emu_persistent_image); - emu_persistent_image = NULL; + struct emu_data *emu_data = (struct emu_data *)data; + if (emu_data->emu_chip != EMULATE_NONE) { + if (emu_data->emu_persistent_image && emu_data->emu_modified) { + msg_pdbg("Writing %s\n", emu_data->emu_persistent_image); + write_buf_to_file(flashchip_contents, + emu_data->emu_chip_size, + emu_data->emu_persistent_image); + free(emu_data->emu_persistent_image); + emu_data->emu_persistent_image = NULL; } free(flashchip_contents); } @@ -163,6 +171,14 @@ struct stat image_stat; #endif + struct emu_data *data = calloc(1, sizeof(struct emu_data)); + data->emu_chip = EMULATE_NONE; + if (!data) { + msg_perr("Out of memory!\n"); + return 1; + } + spi_master_dummyflasher.data = data; + msg_pspew("%s\n", __func__); bustext = extract_programmer_param("bus"); @@ -215,8 +231,8 @@ free(tmp); return 1; } - spi_blacklist_size = i / 2; - for (i = 0; i < spi_blacklist_size * 2; i++) { + data->spi_blacklist_size = i / 2; + for (i = 0; i < data->spi_blacklist_size * 2; i++) { if (!isxdigit((unsigned char)tmp[i])) { msg_perr("Invalid char \"%c\" in SPI command " "blacklist\n", tmp[i]); @@ -224,18 +240,18 @@ return 1; } } - for (i = 0; i < spi_blacklist_size; i++) { + for (i = 0; i < data->spi_blacklist_size; i++) { unsigned int tmp2; /* SCNx8 is apparently not supported by MSVC (and thus * MinGW), so work around it with an extra variable */ sscanf(tmp + i * 2, "%2x", &tmp2); - spi_blacklist[i] = (uint8_t)tmp2; + data->spi_blacklist[i] = (uint8_t)tmp2; } msg_pdbg("SPI blacklist is "); - for (i = 0; i < spi_blacklist_size; i++) - msg_pdbg("%02x ", spi_blacklist[i]); - msg_pdbg(", size %u\n", spi_blacklist_size); + for (i = 0; i < data->spi_blacklist_size; i++) + msg_pdbg("%02x ", data->spi_blacklist[i]); + msg_pdbg(", size %u\n", data->spi_blacklist_size); } free(tmp); @@ -251,8 +267,8 @@ free(tmp); return 1; } - spi_ignorelist_size = i / 2; - for (i = 0; i < spi_ignorelist_size * 2; i++) { + data->spi_ignorelist_size = i / 2; + for (i = 0; i < data->spi_ignorelist_size * 2; i++) { if (!isxdigit((unsigned char)tmp[i])) { msg_perr("Invalid char \"%c\" in SPI command " "ignorelist\n", tmp[i]); @@ -260,18 +276,18 @@ return 1; } } - for (i = 0; i < spi_ignorelist_size; i++) { + for (i = 0; i < data->spi_ignorelist_size; i++) { unsigned int tmp2; /* SCNx8 is apparently not supported by MSVC (and thus * MinGW), so work around it with an extra variable */ sscanf(tmp + i * 2, "%2x", &tmp2); - spi_ignorelist[i] = (uint8_t)tmp2; + data->spi_ignorelist[i] = (uint8_t)tmp2; } msg_pdbg("SPI ignorelist is "); - for (i = 0; i < spi_ignorelist_size; i++) - msg_pdbg("%02x ", spi_ignorelist[i]); - msg_pdbg(", size %u\n", spi_ignorelist_size); + for (i = 0; i < data->spi_ignorelist_size; i++) + msg_pdbg("%02x ", data->spi_ignorelist[i]); + msg_pdbg(", size %u\n", data->spi_ignorelist_size); } free(tmp); @@ -301,67 +317,67 @@ } #if EMULATE_SPI_CHIP if (!strcmp(tmp, "M25P10.RES")) { - emu_chip = EMULATE_ST_M25P10_RES; - emu_chip_size = 128 * 1024; - emu_max_byteprogram_size = 128; - emu_max_aai_size = 0; - emu_jedec_se_size = 0; - emu_jedec_be_52_size = 0; - emu_jedec_be_d8_size = 32 * 1024; - emu_jedec_ce_60_size = 0; - emu_jedec_ce_c7_size = emu_chip_size; + data->emu_chip = EMULATE_ST_M25P10_RES; + data->emu_chip_size = 128 * 1024; + data->emu_max_byteprogram_size = 128; + data->emu_max_aai_size = 0; + data->emu_jedec_se_size = 0; + data->emu_jedec_be_52_size = 0; + data->emu_jedec_be_d8_size = 32 * 1024; + data->emu_jedec_ce_60_size = 0; + data->emu_jedec_ce_c7_size = data->emu_chip_size; msg_pdbg("Emulating ST M25P10.RES SPI flash chip (RES, page " "write)\n"); } if (!strcmp(tmp, "SST25VF040.REMS")) { - emu_chip = EMULATE_SST_SST25VF040_REMS; - emu_chip_size = 512 * 1024; - emu_max_byteprogram_size = 1; - emu_max_aai_size = 0; - emu_jedec_se_size = 4 * 1024; - emu_jedec_be_52_size = 32 * 1024; - emu_jedec_be_d8_size = 0; - emu_jedec_ce_60_size = emu_chip_size; - emu_jedec_ce_c7_size = 0; + data->emu_chip = EMULATE_SST_SST25VF040_REMS; + data->emu_chip_size = 512 * 1024; + data->emu_max_byteprogram_size = 1; + data->emu_max_aai_size = 0; + data->emu_jedec_se_size = 4 * 1024; + data->emu_jedec_be_52_size = 32 * 1024; + data->emu_jedec_be_d8_size = 0; + data->emu_jedec_ce_60_size = data->emu_chip_size; + data->emu_jedec_ce_c7_size = 0; msg_pdbg("Emulating SST SST25VF040.REMS SPI flash chip (REMS, " "byte write)\n"); } if (!strcmp(tmp, "SST25VF032B")) { - emu_chip = EMULATE_SST_SST25VF032B; - emu_chip_size = 4 * 1024 * 1024; - emu_max_byteprogram_size = 1; - emu_max_aai_size = 2; - emu_jedec_se_size = 4 * 1024; - emu_jedec_be_52_size = 32 * 1024; - emu_jedec_be_d8_size = 64 * 1024; - emu_jedec_ce_60_size = emu_chip_size; - emu_jedec_ce_c7_size = emu_chip_size; + data->emu_chip = EMULATE_SST_SST25VF032B; + data->emu_chip_size = 4 * 1024 * 1024; + data->emu_max_byteprogram_size = 1; + data->emu_max_aai_size = 2; + data->emu_jedec_se_size = 4 * 1024; + data->emu_jedec_be_52_size = 32 * 1024; + data->emu_jedec_be_d8_size = 64 * 1024; + data->emu_jedec_ce_60_size = data->emu_chip_size; + data->emu_jedec_ce_c7_size = data->emu_chip_size; msg_pdbg("Emulating SST SST25VF032B SPI flash chip (RDID, AAI " "write)\n"); } if (!strcmp(tmp, "MX25L6436")) { - emu_chip = EMULATE_MACRONIX_MX25L6436; - emu_chip_size = 8 * 1024 * 1024; - emu_max_byteprogram_size = 256; - emu_max_aai_size = 0; - emu_jedec_se_size = 4 * 1024; - emu_jedec_be_52_size = 32 * 1024; - emu_jedec_be_d8_size = 64 * 1024; - emu_jedec_ce_60_size = emu_chip_size; - emu_jedec_ce_c7_size = emu_chip_size; + data->emu_chip = EMULATE_MACRONIX_MX25L6436; + data->emu_chip_size = 8 * 1024 * 1024; + data->emu_max_byteprogram_size = 256; + data->emu_max_aai_size = 0; + data->emu_jedec_se_size = 4 * 1024; + data->emu_jedec_be_52_size = 32 * 1024; + data->emu_jedec_be_d8_size = 64 * 1024; + data->emu_jedec_ce_60_size = data->emu_chip_size; + data->emu_jedec_ce_c7_size = data->emu_chip_size; msg_pdbg("Emulating Macronix MX25L6436 SPI flash chip (RDID, " "SFDP)\n"); } if (!strcmp(tmp, "W25Q128FV")) { - emu_chip = EMULATE_WINBOND_W25Q128FV; - emu_chip_size = 16 * 1024 * 1024; - emu_max_byteprogram_size = 256; - emu_max_aai_size = 0; - emu_jedec_se_size = 4 * 1024; - emu_jedec_be_52_size = 32 * 1024; - emu_jedec_be_d8_size = 64 * 1024; - emu_jedec_ce_60_size = emu_chip_size; - emu_jedec_ce_c7_size = emu_chip_size; + data->emu_chip = EMULATE_WINBOND_W25Q128FV; + data->emu_chip_size = 16 * 1024 * 1024; + data->emu_max_byteprogram_size = 256; + data->emu_max_aai_size = 0; + data->emu_jedec_se_size = 4 * 1024; + data->emu_jedec_be_52_size = 32 * 1024; + data->emu_jedec_be_d8_size = 64 * 1024; + data->emu_jedec_ce_60_size = data->emu_chip_size; + data->emu_jedec_ce_c7_size = data->emu_chip_size; msg_pdbg("Emulating Winbond W25Q128FV SPI flash chip (RDID)\n"); } @@ -369,26 +385,26 @@ * flashrom -p dummy:emulate=VARIABLE_SIZE,size=4194304 */ if (!strcmp(tmp, "VARIABLE_SIZE")) { - emu_chip = EMULATE_VARIABLE_SIZE; - emu_chip_size = size; - emu_max_byteprogram_size = 256; - emu_max_aai_size = 0; - emu_jedec_se_size = 4 * 1024; - emu_jedec_be_52_size = 32 * 1024; - emu_jedec_be_d8_size = 64 * 1024; - emu_jedec_ce_60_size = emu_chip_size; - emu_jedec_ce_c7_size = emu_chip_size; + data->emu_chip = EMULATE_VARIABLE_SIZE; + data->emu_chip_size = size; + data->emu_max_byteprogram_size = 256; + data->emu_max_aai_size = 0; + data->emu_jedec_se_size = 4 * 1024; + data->emu_jedec_be_52_size = 32 * 1024; + data->emu_jedec_be_d8_size = 64 * 1024; + data->emu_jedec_ce_60_size = data->emu_chip_size; + data->emu_jedec_ce_c7_size = data->emu_chip_size; msg_pdbg("Emulating generic SPI flash chip (size=%d bytes)\n", - emu_chip_size); + data->emu_chip_size); } #endif - if (emu_chip == EMULATE_NONE) { + if (data->emu_chip == EMULATE_NONE) { msg_perr("Invalid chip specified for emulation: %s\n", tmp); free(tmp); return 1; } free(tmp); - flashchip_contents = malloc(emu_chip_size); + flashchip_contents = malloc(data->emu_chip_size); if (!flashchip_contents) { msg_perr("Out of memory!\n"); return 1; @@ -399,7 +415,7 @@ if (status) { char *endptr; errno = 0; - emu_status = strtoul(status, &endptr, 0); + data->emu_status = strtoul(status, &endptr, 0); free(status); if (errno != 0 || status == endptr) { msg_perr("Error: initial status register specified, " @@ -407,30 +423,30 @@ return 1; } msg_pdbg("Initial status register is set to 0x%02x.\n", - emu_status); + data->emu_status); } #endif - msg_pdbg("Filling fake flash chip with 0xff, size %i\n", emu_chip_size); - memset(flashchip_contents, 0xff, emu_chip_size); + msg_pdbg("Filling fake flash chip with 0xff, size %i\n", data->emu_chip_size); + memset(flashchip_contents, 0xff, data->emu_chip_size); /* Will be freed by shutdown function if necessary. */ - emu_persistent_image = extract_programmer_param("image"); - if (!emu_persistent_image) { + data->emu_persistent_image = extract_programmer_param("image"); + if (!data->emu_persistent_image) { /* Nothing else to do. */ goto dummy_init_out; } /* We will silently (in default verbosity) ignore the file if it does not exist (yet) or the size does * not match the emulated chip. */ - if (!stat(emu_persistent_image, &image_stat)) { + if (!stat(data->emu_persistent_image, &image_stat)) { msg_pdbg("Found persistent image %s, %jd B ", - emu_persistent_image, (intmax_t)image_stat.st_size); - if ((uintmax_t)image_stat.st_size == emu_chip_size) { + data->emu_persistent_image, (intmax_t)image_stat.st_size); + if ((uintmax_t)image_stat.st_size == data->emu_chip_size) { msg_pdbg("matches.\n"); - msg_pdbg("Reading %s\n", emu_persistent_image); - if (read_buf_from_file(flashchip_contents, emu_chip_size, - emu_persistent_image)) { - msg_perr("Unable to read %s\n", emu_persistent_image); + msg_pdbg("Reading %s\n", data->emu_persistent_image); + if (read_buf_from_file(flashchip_contents, data->emu_chip_size, + data->emu_persistent_image)) { + msg_perr("Unable to read %s\n", data->emu_persistent_image); free(flashchip_contents); return 1; } @@ -441,15 +457,16 @@ #endif dummy_init_out: - if (register_shutdown(dummy_shutdown, NULL)) { + if (register_shutdown(dummy_shutdown, data)) { free(flashchip_contents); return 1; } if (dummy_buses_supported & (BUS_PARALLEL | BUS_LPC | BUS_FWH)) register_par_master(&par_master_dummy, dummy_buses_supported & (BUS_PARALLEL | BUS_LPC | BUS_FWH)); - if (dummy_buses_supported & BUS_SPI) + if (dummy_buses_supported & BUS_SPI) { register_spi_master(&spi_master_dummyflasher); + } return 0; } @@ -521,7 +538,8 @@ static int emulate_spi_chip_response(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, - unsigned char *readarr) + unsigned char *readarr, + struct emu_data *emu_data) { unsigned int offs, i, toread; static int unsigned aai_offs; @@ -535,17 +553,17 @@ return 1; } /* spi_blacklist has precedence over spi_ignorelist. */ - for (i = 0; i < spi_blacklist_size; i++) { - if (writearr[0] == spi_blacklist[i]) { + for (i = 0; i < emu_data->spi_blacklist_size; i++) { + if (writearr[0] == emu_data->spi_blacklist[i]) { msg_pdbg("Refusing blacklisted SPI command 0x%02x\n", - spi_blacklist[i]); + emu_data->spi_blacklist[i]); return SPI_INVALID_OPCODE; } } - for (i = 0; i < spi_ignorelist_size; i++) { - if (writearr[0] == spi_ignorelist[i]) { + for (i = 0; i < emu_data->spi_ignorelist_size; i++) { + if (writearr[0] == emu_data->spi_ignorelist[i]) { msg_cdbg("Ignoring ignorelisted SPI command 0x%02x\n", - spi_ignorelist[i]); + emu_data->spi_ignorelist[i]); /* Return success because the command does not fail, * it is simply ignored. */ @@ -553,7 +571,7 @@ } } - if (emu_max_aai_size && (emu_status & SPI_SR_AAI)) { + if (emu_data->emu_max_aai_size && (emu_data->emu_status & SPI_SR_AAI)) { if (writearr[0] != JEDEC_AAI_WORD_PROGRAM && writearr[0] != JEDEC_WRDI && writearr[0] != JEDEC_RDSR) { @@ -570,7 +588,7 @@ /* offs calculation is only needed for SST chips which treat RES like REMS. */ offs = writearr[1] << 16 | writearr[2] << 8 | writearr[3]; offs += writecnt - JEDEC_REMS_OUTSIZE; - switch (emu_chip) { + switch (emu_data->emu_chip) { case EMULATE_ST_M25P10_RES: if (readcnt > 0) memset(readarr, 0x10, readcnt); @@ -601,7 +619,7 @@ break; offs = writearr[1] << 16 | writearr[2] << 8 | writearr[3]; offs += writecnt - JEDEC_REMS_OUTSIZE; - switch (emu_chip) { + switch (emu_data->emu_chip) { case EMULATE_SST_SST25VF040_REMS: for (i = 0; i < readcnt; i++) readarr[i] = sst25vf040_rems_response[(offs + i) % 2]; @@ -623,7 +641,7 @@ } break; case JEDEC_RDID: - switch (emu_chip) { + switch (emu_data->emu_chip) { case EMULATE_SST_SST25VF032B: if (readcnt > 0) readarr[0] = 0xbf; @@ -663,70 +681,70 @@ } break; case JEDEC_RDSR: - memset(readarr, emu_status, readcnt); + memset(readarr, emu_data->emu_status, readcnt); break; /* FIXME: this should be chip-specific. */ case JEDEC_EWSR: case JEDEC_WREN: - emu_status |= SPI_SR_WEL; + emu_data->emu_status |= SPI_SR_WEL; break; case JEDEC_WRSR: - if (!(emu_status & SPI_SR_WEL)) { + if (!(emu_data->emu_status & SPI_SR_WEL)) { msg_perr("WRSR attempted, but WEL is 0!\n"); break; } /* FIXME: add some reasonable simulation of the busy flag */ - emu_status = writearr[1] & ~SPI_SR_WIP; - msg_pdbg2("WRSR wrote 0x%02x.\n", emu_status); + emu_data->emu_status = writearr[1] & ~SPI_SR_WIP; + msg_pdbg2("WRSR wrote 0x%02x.\n", emu_data->emu_status); break; case JEDEC_READ: offs = writearr[1] << 16 | writearr[2] << 8 | writearr[3]; /* Truncate to emu_chip_size. */ - offs %= emu_chip_size; + offs %= emu_data->emu_chip_size; if (readcnt > 0) memcpy(readarr, flashchip_contents + offs, readcnt); break; case JEDEC_READ_4BA: offs = writearr[1] << 24 | writearr[2] << 16 | writearr[3] << 8 | writearr[4]; /* Truncate to emu_chip_size. */ - offs %= emu_chip_size; + offs %= emu_data->emu_chip_size; if (readcnt > 0) memcpy(readarr, flashchip_contents + offs, readcnt); break; case JEDEC_BYTE_PROGRAM: offs = writearr[1] << 16 | writearr[2] << 8 | writearr[3]; /* Truncate to emu_chip_size. */ - offs %= emu_chip_size; + offs %= emu_data->emu_chip_size; if (writecnt < 5) { msg_perr("BYTE PROGRAM size too short!\n"); return 1; } - if (writecnt - 4 > emu_max_byteprogram_size) { + if (writecnt - 4 > emu_data->emu_max_byteprogram_size) { msg_perr("Max BYTE PROGRAM size exceeded!\n"); return 1; } memcpy(flashchip_contents + offs, writearr + 4, writecnt - 4); - emu_modified = 1; + emu_data->emu_modified = 1; break; case JEDEC_BYTE_PROGRAM_4BA: offs = writearr[1] << 24 | writearr[2] << 16 | writearr[3] << 8 | writearr[4]; /* Truncate to emu_chip_size. */ - offs %= emu_chip_size; + offs %= emu_data->emu_chip_size; if (writecnt < 6) { msg_perr("BYTE PROGRAM size too short!\n"); return 1; } - if (writecnt - 5 > emu_max_byteprogram_size) { + if (writecnt - 5 > emu_data->emu_max_byteprogram_size) { msg_perr("Max BYTE PROGRAM size exceeded!\n"); return 1; } memcpy(flashchip_contents + offs, writearr + 5, writecnt - 5); - emu_modified = 1; + emu_data->emu_modified = 1; break; case JEDEC_AAI_WORD_PROGRAM: - if (!emu_max_aai_size) + if (!emu_data->emu_max_aai_size) break; - if (!(emu_status & SPI_SR_AAI)) { + if (!(emu_data->emu_status & SPI_SR_AAI)) { if (writecnt < JEDEC_AAI_WORD_PROGRAM_OUTSIZE) { msg_perr("Initial AAI WORD PROGRAM size too " "short!\n"); @@ -737,11 +755,11 @@ "long!\n"); return 1; } - emu_status |= SPI_SR_AAI; + emu_data->emu_status |= SPI_SR_AAI; aai_offs = writearr[1] << 16 | writearr[2] << 8 | writearr[3]; /* Truncate to emu_chip_size. */ - aai_offs %= emu_chip_size; + aai_offs %= emu_data->emu_chip_size; memcpy(flashchip_contents + aai_offs, writearr + 4, 2); aai_offs += 2; } else { @@ -758,14 +776,14 @@ memcpy(flashchip_contents + aai_offs, writearr + 1, 2); aai_offs += 2; } - emu_modified = 1; + emu_data->emu_modified = 1; break; case JEDEC_WRDI: - if (emu_max_aai_size) - emu_status &= ~SPI_SR_AAI; + if (emu_data->emu_max_aai_size) + emu_data->emu_status &= ~SPI_SR_AAI; break; case JEDEC_SE: - if (!emu_jedec_se_size) + if (!emu_data->emu_jedec_se_size) break; if (writecnt != JEDEC_SE_OUTSIZE) { msg_perr("SECTOR ERASE 0x20 outsize invalid!\n"); @@ -776,14 +794,14 @@ return 1; } offs = writearr[1] << 16 | writearr[2] << 8 | writearr[3]; - if (offs & (emu_jedec_se_size - 1)) + if (offs & (emu_data->emu_jedec_se_size - 1)) msg_pdbg("Unaligned SECTOR ERASE 0x20: 0x%x\n", offs); - offs &= ~(emu_jedec_se_size - 1); - memset(flashchip_contents + offs, 0xff, emu_jedec_se_size); - emu_modified = 1; + offs &= ~(emu_data->emu_jedec_se_size - 1); + memset(flashchip_contents + offs, 0xff, emu_data->emu_jedec_se_size); + emu_data->emu_modified = 1; break; case JEDEC_BE_52: - if (!emu_jedec_be_52_size) + if (!emu_data->emu_jedec_be_52_size) break; if (writecnt != JEDEC_BE_52_OUTSIZE) { msg_perr("BLOCK ERASE 0x52 outsize invalid!\n"); @@ -794,14 +812,14 @@ return 1; } offs = writearr[1] << 16 | writearr[2] << 8 | writearr[3]; - if (offs & (emu_jedec_be_52_size - 1)) + if (offs & (emu_data->emu_jedec_be_52_size - 1)) msg_pdbg("Unaligned BLOCK ERASE 0x52: 0x%x\n", offs); - offs &= ~(emu_jedec_be_52_size - 1); - memset(flashchip_contents + offs, 0xff, emu_jedec_be_52_size); - emu_modified = 1; + offs &= ~(emu_data->emu_jedec_be_52_size - 1); + memset(flashchip_contents + offs, 0xff, emu_data->emu_jedec_be_52_size); + emu_data->emu_modified = 1; break; case JEDEC_BE_D8: - if (!emu_jedec_be_d8_size) + if (!emu_data->emu_jedec_be_d8_size) break; if (writecnt != JEDEC_BE_D8_OUTSIZE) { msg_perr("BLOCK ERASE 0xd8 outsize invalid!\n"); @@ -812,14 +830,14 @@ return 1; } offs = writearr[1] << 16 | writearr[2] << 8 | writearr[3]; - if (offs & (emu_jedec_be_d8_size - 1)) + if (offs & (emu_data->emu_jedec_be_d8_size - 1)) msg_pdbg("Unaligned BLOCK ERASE 0xd8: 0x%x\n", offs); - offs &= ~(emu_jedec_be_d8_size - 1); - memset(flashchip_contents + offs, 0xff, emu_jedec_be_d8_size); - emu_modified = 1; + offs &= ~(emu_data->emu_jedec_be_d8_size - 1); + memset(flashchip_contents + offs, 0xff, emu_data->emu_jedec_be_d8_size); + emu_data->emu_modified = 1; break; case JEDEC_CE_60: - if (!emu_jedec_ce_60_size) + if (!emu_data->emu_jedec_ce_60_size) break; if (writecnt != JEDEC_CE_60_OUTSIZE) { msg_perr("CHIP ERASE 0x60 outsize invalid!\n"); @@ -831,11 +849,11 @@ } /* JEDEC_CE_60_OUTSIZE is 1 (no address) -> no offset. */ /* emu_jedec_ce_60_size is emu_chip_size. */ - memset(flashchip_contents, 0xff, emu_jedec_ce_60_size); - emu_modified = 1; + memset(flashchip_contents, 0xff, emu_data->emu_jedec_ce_60_size); + emu_data->emu_modified = 1; break; case JEDEC_CE_C7: - if (!emu_jedec_ce_c7_size) + if (!emu_data->emu_jedec_ce_c7_size) break; if (writecnt != JEDEC_CE_C7_OUTSIZE) { msg_perr("CHIP ERASE 0xc7 outsize invalid!\n"); @@ -847,11 +865,11 @@ } /* JEDEC_CE_C7_OUTSIZE is 1 (no address) -> no offset. */ /* emu_jedec_ce_c7_size is emu_chip_size. */ - memset(flashchip_contents, 0xff, emu_jedec_ce_c7_size); - emu_modified = 1; + memset(flashchip_contents, 0xff, emu_data->emu_jedec_ce_c7_size); + emu_data->emu_modified = 1; break; case JEDEC_SFDP: - if (emu_chip != EMULATE_MACRONIX_MX25L6436) + if (emu_data->emu_chip != EMULATE_MACRONIX_MX25L6436) break; if (writecnt < 4) break; @@ -890,7 +908,7 @@ break; } if (writearr[0] != JEDEC_WREN && writearr[0] != JEDEC_EWSR) - emu_status &= ~SPI_SR_WEL; + emu_data->emu_status &= ~SPI_SR_WEL; return 0; } #endif @@ -901,6 +919,7 @@ unsigned char *readarr) { unsigned int i; + struct emu_data *emu_data = (struct emu_data *)flash->mst->par.data; msg_pspew("%s:", __func__); @@ -911,7 +930,7 @@ /* Response for unknown commands and missing chip is 0xff. */ memset(readarr, 0xff, readcnt); #if EMULATE_SPI_CHIP - switch (emu_chip) { + switch (emu_data->emu_chip) { case EMULATE_ST_M25P10_RES: case EMULATE_SST_SST25VF040_REMS: case EMULATE_SST_SST25VF032B: @@ -919,7 +938,7 @@ case EMULATE_WINBOND_W25Q128FV: case EMULATE_VARIABLE_SIZE: if (emulate_spi_chip_response(writecnt, readcnt, writearr, - readarr)) { + readarr, emu_data)) { msg_pdbg("Invalid command sent to flash chip!\n"); return 1; } @@ -945,9 +964,10 @@ int probe_variable_size(struct flashctx *flash) { unsigned int i; + const struct emu_data *emu_data = (struct emu_data *)flash->mst->par.data; /* Skip the probing if we don't emulate this chip. */ - if (emu_chip != EMULATE_VARIABLE_SIZE) + if (emu_data->emu_chip != EMULATE_VARIABLE_SIZE) return 0; /* @@ -961,7 +981,7 @@ * * Search "total_size * 1024" in code. */ - flash->chip->total_size = emu_chip_size / 1024; + flash->chip->total_size = emu_data->emu_chip_size / 1024; msg_cdbg("%s: set flash->total_size to %dK bytes.\n", __func__, flash->chip->total_size); @@ -972,7 +992,7 @@ break; eraser->eraseblocks[0].count = 1; - eraser->eraseblocks[0].size = emu_chip_size; + eraser->eraseblocks[0].size = emu_data->emu_chip_size; msg_cdbg("%s: eraser.size=%d, .count=%d\n", __func__, eraser->eraseblocks[0].size, eraser->eraseblocks[0].count); -- To view, visit https://review.coreboot.org/c/flashrom/+/45230 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I972b085875f1277d9ff33326669d2676a3bcd3aa Gerrit-Change-Number: 45230 Gerrit-PatchSet: 1 Gerrit-Owner: Lachlan Bishop <lxb(a)google.com> Gerrit-MessageType: newchange

3 15

Change in flashrom[master]: allow 0x34 as ICCRIBA for CHIPSET_C620_SERIES_LEWISBURG
by Jonathan Zhang (Code Review) 10 Sep '20

10 Sep '20

Jonathan Zhang has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/44621 ) Change subject: allow 0x34 as ICCRIBA for CHIPSET_C620_SERIES_LEWISBURG ...................................................................... allow 0x34 as ICCRIBA for CHIPSET_C620_SERIES_LEWISBURG Intel C621A Lewisburg PCH belongs to C620 series, it has 0x34 as ICCRIBA. Fix guess_ich_chipset_from_content() accordingly. Print error status info for read_ich_descriptors_from_dump(). Change-Id: I363aaccfb90e0a127c0f0bb0072e9e85c210b669 Signed-off-by: Jonathan Zhang <jonzhang(a)fb.com> --- M ich_descriptors.c 1 file changed, 5 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/21/44621/1 diff --git a/ich_descriptors.c b/ich_descriptors.c index 120d3fe..cd8e13a 100644 --- a/ich_descriptors.c +++ b/ich_descriptors.c @@ -932,7 +932,7 @@ return CHIPSET_8_SERIES_LYNX_POINT; msg_pwarn("Peculiar firmware descriptor, assuming Wildcat Point compatibility.\n"); return CHIPSET_9_SERIES_WILDCAT_POINT; - } else if (content->ICCRIBA < 0x34) { + } else if (content->ICCRIBA <= 0x34) { if (content->NM == 6) return CHIPSET_C620_SERIES_LEWISBURG; else @@ -1243,8 +1243,11 @@ struct ich_descriptors desc; enum ich_chipset cs = CHIPSET_ICH_UNKNOWN; - if (read_ich_descriptors_from_dump(dump, len, &cs, &desc)) + int ret = read_ich_descriptors_from_dump(dump, len, &cs, &desc); + if (ret) { + msg_cerr("__FUNC__, __LINE__ Failed with value %d.\n", ret); return 1; + } memset(layout, 0x00, sizeof(*layout)); -- To view, visit https://review.coreboot.org/c/flashrom/+/44621 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I363aaccfb90e0a127c0f0bb0072e9e85c210b669 Gerrit-Change-Number: 44621 Gerrit-PatchSet: 1 Gerrit-Owner: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-MessageType: newchange

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Change in flashrom[master]: support 4-byte address format for VARIOUS_SIZE dummy flash device
by Namyoon Woo (Code Review) 07 Sep '20

07 Sep '20

Namyoon Woo has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/44881 ) Change subject: support 4-byte address format for VARIOUS_SIZE dummy flash device ...................................................................... support 4-byte address format for VARIOUS_SIZE dummy flash device This patch adds a support of 4-byte address format for VARIOUS_SIZE dummy flash device, so that it can emulate an flash size larger than 16 MBytes. TEST=ran the command line below: $ flashrom -p dummy:image=${TMP_FILE},size=33554432, \ emulate=VARIABLE_SIZE -w ${IMG_32MB} -V -f $ flashrom -p dummy:image=${TMP_FILE},size=16777216, \ emulate=VARIABLE_SIZE -w ${IMG_16MB} -V -f $ flashrom -p dummy:image=${TMP_FILE},size=8388608, \ emulate=VARIABLE_SIZE -w ${IMG_8MB} -V -f Signed-off-by: Namyoon Woo <namyoon(a)google.com> Change-Id: Ia59eecfcbe798d50f8dacea98c3c508edf8ec77e --- M dummyflasher.c M flashchips.c 2 files changed, 25 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/81/44881/1 diff --git a/dummyflasher.c b/dummyflasher.c index 4024f2a..b5a0f1b 100644 --- a/dummyflasher.c +++ b/dummyflasher.c @@ -719,6 +719,13 @@ if (readcnt > 0) memcpy(readarr, flashchip_contents + offs, readcnt); break; + case JEDEC_READ_4BA: + offs = writearr[1] << 24 | writearr[2] << 16 | writearr[3] << 8 | writearr[4]; + /* Truncate to emu_chip_size. */ + offs %= emu_chip_size; + if (readcnt > 0) + memcpy(readarr, flashchip_contents + offs, readcnt); + break; case JEDEC_BYTE_PROGRAM: offs = writearr[1] << 16 | writearr[2] << 8 | writearr[3]; /* Truncate to emu_chip_size. */ @@ -733,6 +740,20 @@ } memcpy(flashchip_contents + offs, writearr + 4, writecnt - 4); break; + case JEDEC_BYTE_PROGRAM_4BA: + offs = writearr[1] << 24 | writearr[2] << 16 | writearr[3] << 8 | writearr[4]; + /* Truncate to emu_chip_size. */ + offs %= emu_chip_size; + if (writecnt < 6) { + msg_perr("BYTE PROGRAM size too short!\n"); + return 1; + } + if (writecnt - 5 > emu_max_byteprogram_size) { + msg_perr("Max BYTE PROGRAM size exceeded!\n"); + return 1; + } + memcpy(flashchip_contents + offs, writearr + 5, writecnt - 5); + break; case JEDEC_AAI_WORD_PROGRAM: if (!emu_max_aai_size) break; @@ -978,8 +999,8 @@ if (eraser->block_erase == NULL) break; - eraser->eraseblocks[0].count = emu_chip_size / - eraser->eraseblocks[0].size; + eraser->eraseblocks[0].count = 1; + eraser->eraseblocks[0].size = emu_chip_size; msg_cdbg("%s: eraser.size=%d, .count=%d\n", __func__, eraser->eraseblocks[0].size, eraser->eraseblocks[0].count); diff --git a/flashchips.c b/flashchips.c index e99073b..34b7702 100644 --- a/flashchips.c +++ b/flashchips.c @@ -18765,13 +18765,14 @@ .model_id = VARIABLE_SIZE_DEVICE_ID, .total_size = 64, /* This size is set temporarily */ .page_size = 256, + .feature_bits = FEATURE_4BA, .tested = TEST_OK_PREW, .probe = probe_variable_size, .block_erasers = { { .eraseblocks = { {64 * 1024, 1} }, - .block_erase = spi_block_erase_d8, + .block_erase = spi_block_erase_c7, } }, .write = spi_chip_write_256, -- To view, visit https://review.coreboot.org/c/flashrom/+/44881 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Ia59eecfcbe798d50f8dacea98c3c508edf8ec77e Gerrit-Change-Number: 44881 Gerrit-PatchSet: 1 Gerrit-Owner: Namyoon Woo <namyoon(a)google.com> Gerrit-MessageType: newchange

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Change in flashrom[master]: Only write back emulated image if modified
by Namyoon Woo (Code Review) 07 Sep '20

07 Sep '20

Namyoon Woo has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/44907 ) Change subject: Only write back emulated image if modified ...................................................................... Only write back emulated image if modified When the image is not modified, there is no point in writing it back. In fact we may not have file permissions to do so. Signed-off-by: Namyoon Woo <namyoon(a)google.com> Change-Id: I3bf2d7edb28a9a1e5406b67a88a0ee6e07db83e3 --- M dummyflasher.c 1 file changed, 9 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/07/44907/1 diff --git a/dummyflasher.c b/dummyflasher.c index d1b7366..ea3907e 100644 --- a/dummyflasher.c +++ b/dummyflasher.c @@ -50,6 +50,7 @@ static enum emu_chip emu_chip = EMULATE_NONE; static char *emu_persistent_image = NULL; static unsigned int emu_chip_size = 0; +static int emu_modified; /* is the image modified since reading it? */ #if EMULATE_SPI_CHIP static unsigned int emu_max_byteprogram_size = 0; static unsigned int emu_max_aai_size = 0; @@ -137,7 +138,7 @@ msg_pspew("%s\n", __func__); #if EMULATE_CHIP if (emu_chip != EMULATE_NONE) { - if (emu_persistent_image) { + if (emu_persistent_image && emu_modified) { msg_pdbg("Writing %s\n", emu_persistent_image); write_buf_to_file(flashchip_contents, emu_chip_size, emu_persistent_image); free(emu_persistent_image); @@ -727,6 +728,7 @@ return 1; } memcpy(flashchip_contents + offs, writearr + 4, writecnt - 4); + emu_modified = 1; break; case JEDEC_AAI_WORD_PROGRAM: if (!emu_max_aai_size) @@ -763,6 +765,7 @@ memcpy(flashchip_contents + aai_offs, writearr + 1, 2); aai_offs += 2; } + emu_modified = 1; break; case JEDEC_WRDI: if (emu_max_aai_size) @@ -784,6 +787,7 @@ msg_pdbg("Unaligned SECTOR ERASE 0x20: 0x%x\n", offs); offs &= ~(emu_jedec_se_size - 1); memset(flashchip_contents + offs, 0xff, emu_jedec_se_size); + emu_modified = 1; break; case JEDEC_BE_52: if (!emu_jedec_be_52_size) @@ -801,6 +805,7 @@ msg_pdbg("Unaligned BLOCK ERASE 0x52: 0x%x\n", offs); offs &= ~(emu_jedec_be_52_size - 1); memset(flashchip_contents + offs, 0xff, emu_jedec_be_52_size); + emu_modified = 1; break; case JEDEC_BE_D8: if (!emu_jedec_be_d8_size) @@ -818,6 +823,7 @@ msg_pdbg("Unaligned BLOCK ERASE 0xd8: 0x%x\n", offs); offs &= ~(emu_jedec_be_d8_size - 1); memset(flashchip_contents + offs, 0xff, emu_jedec_be_d8_size); + emu_modified = 1; break; case JEDEC_CE_60: if (!emu_jedec_ce_60_size) @@ -833,6 +839,7 @@ /* JEDEC_CE_60_OUTSIZE is 1 (no address) -> no offset. */ /* emu_jedec_ce_60_size is emu_chip_size. */ memset(flashchip_contents, 0xff, emu_jedec_ce_60_size); + emu_modified = 1; break; case JEDEC_CE_C7: if (!emu_jedec_ce_c7_size) @@ -848,6 +855,7 @@ /* JEDEC_CE_C7_OUTSIZE is 1 (no address) -> no offset. */ /* emu_jedec_ce_c7_size is emu_chip_size. */ memset(flashchip_contents, 0xff, emu_jedec_ce_c7_size); + emu_modified = 1; break; case JEDEC_SFDP: if (emu_chip != EMULATE_MACRONIX_MX25L6436) -- To view, visit https://review.coreboot.org/c/flashrom/+/44907 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I3bf2d7edb28a9a1e5406b67a88a0ee6e07db83e3 Gerrit-Change-Number: 44907 Gerrit-PatchSet: 1 Gerrit-Owner: Namyoon Woo <namyoon(a)google.com> Gerrit-MessageType: newchange

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