September 2020 - flashrom-gerrit

Change in flashrom[master]: flashrom: Added Support for BoyaMicro BY25Q128AS
by Jack Olsen (Code Review) 20 Nov '20

20 Nov '20

Jack Olsen has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/44308 ) Change subject: flashrom: Added Support for BoyaMicro BY25Q128AS ...................................................................... flashrom: Added Support for BoyaMicro BY25Q128AS Tested on Buspirate Change-Id: I881ba86cfaa82e43c73360135d47c74d896cc191 --- M flashchips.c M flashchips.h 2 files changed, 42 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/08/44308/1 diff --git a/flashchips.c b/flashchips.c index 09ac9b4..5c60b2c 100644 --- a/flashchips.c +++ b/flashchips.c @@ -3442,6 +3442,44 @@ .voltage = {3000, 3600}, }, + { + .vendor = "Boya", + .name = "BY25Q128AS", + .bustype = BUS_SPI, + .manufacture_id = BOYA_ID, + .model_id = BOYA_BY25Q128AS, + .total_size = 16384, + .page_size = 256, + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_QPI, + .tested = TEST_OK_PREW, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 4096} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {32 * 1024, 512} }, + .block_erase = spi_block_erase_52, + }, { + .eraseblocks = { {64 * 1024, 256} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {16 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {16 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, + .printlock = spi_prettyprint_status_register_plain, + .unlock = spi_disable_blockprotect_at25fs040, + .write = spi_chip_write_256, + .read = spi_chip_read, + .voltage = {2700, 3600}, + }, + { .vendor = "Bright", .name = "BM29F040", diff --git a/flashchips.h b/flashchips.h index 4ae6c07..9d19ef5 100644 --- a/flashchips.h +++ b/flashchips.h @@ -207,6 +207,10 @@ #define ATMEL_AT49F080 0x23 #define ATMEL_AT49F080T 0x27 +/* Boya Microelectronics Inc.*/ +#define BOYA_ID 0x68 +#define BOYA_BY25Q128AS 0x4018 + /* Bright Microelectronics has the same manufacturer ID as Hyundai... */ #define BRIGHT_ID 0xAD /* Bright Microelectronics */ #define BRIGHT_BM29F040 0x40 -- To view, visit https://review.coreboot.org/c/flashrom/+/44308 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I881ba86cfaa82e43c73360135d47c74d896cc191 Gerrit-Change-Number: 44308 Gerrit-PatchSet: 1 Gerrit-Owner: Jack Olsen <omegasec(a)tutanota.com> Gerrit-MessageType: newchange

5 21

Change in flashrom[master]: programmer: Introduce programmer alias mechanism
by Edward O'Callaghan (Code Review) 27 Oct '20

27 Oct '20

Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/38671 ) Change subject: programmer: Introduce programmer alias mechanism ...................................................................... programmer: Introduce programmer alias mechanism Originally introduced in the downstream commit ba0827acee4da6740133345f43aae386923bbaad . This was originally authored by David Hendricks so that the various flash peripheral in ChromeOS devices can be flashed. For example, flashrom -p ec -r ec.bin flashrom -p host -r host.bin Note that this requires, `CONFIG_DEFAULT_PROGRAMMER=PROGRAMMER_INTERNAL make` to be defined as build-time. BUG=b:148755493 BRANCH=none TEST=ran ./flashrom -p host --flash-name Change-Id: I73766451cd8900a9e0fe08efc7a4d81b2a35ac8d Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> --- M cli_classic.c M it85spi.c M linux_mtd.c M linux_spi.c M programmer.c M programmer.h 6 files changed, 98 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/71/38671/1 diff --git a/cli_classic.c b/cli_classic.c index 73cc417..d58562b 100644 --- a/cli_classic.c +++ b/cli_classic.c @@ -329,13 +329,51 @@ break; } } - if (prog == PROGRAMMER_INVALID) { + + for (i = 0; aliases[i].name; i++) { + name = aliases[i].name; + namelen = strlen(aliases[i].name); + + if (strncmp(optarg, name, namelen)) + continue; + + switch (optarg[namelen]) { + case ':': + pparam = strdup(optarg + namelen + 1); + if (!strlen(pparam)) { + free(pparam); + pparam = NULL; + } + break; + case '\0': + break; + default: + /* The continue refers to the for-loop. + * It is here to be able to + * differentiate between foo and foobar. + */ + continue; + } + + alias = &aliases[i]; + msg_gdbg("Programmer alias: \"%s\", parameter: " + " \"%s\",\n", alias->name, pparam); + break; + } + + if ((prog == PROGRAMMER_INVALID) && !alias) { fprintf(stderr, "Error: Unknown programmer \"%s\". Valid choices are:\n", optarg); list_programmers_linebreak(0, 80, 0); msg_ginfo(".\n"); cli_classic_abort_usage(NULL); } + + if ((prog != PROGRAMMER_INVALID) && alias) { + fprintf(stderr, "Error: Alias cannot be used " + "with programmer name.\n"); + cli_classic_abort_usage(NULL); + } break; case 'R': /* print_version() is always called during startup. */ diff --git a/it85spi.c b/it85spi.c index 5ce9193..47e2337 100644 --- a/it85spi.c +++ b/it85spi.c @@ -289,6 +289,9 @@ { int ret; + if (!programming_ec()) + return 1; + if (!(internal_buses_supported & BUS_FWH)) { msg_pdbg("%s():%d buses not support FWH\n", __func__, __LINE__); return 1; diff --git a/linux_mtd.c b/linux_mtd.c index d2df95e..bee7cc5 100644 --- a/linux_mtd.c +++ b/linux_mtd.c @@ -363,6 +363,9 @@ int dev_num = 0; int ret = 1; + if (!programming_host()) + return 1; + param = extract_programmer_param("dev"); if (param) { char *endptr; diff --git a/linux_spi.c b/linux_spi.c index aa73c18..221a36e 100644 --- a/linux_spi.c +++ b/linux_spi.c @@ -78,6 +78,14 @@ const uint8_t mode = SPI_MODE_0; const uint8_t bits = 8; + /* + * FIXME: There might be other programmers with flash memory (such as + * an EC) connected via SPI. For now we rely on the device's driver to + * distinguish it and assume generic SPI implies host. + */ + if (!programming_host()) + return 1; + p = extract_programmer_param("spispeed"); if (p && strlen(p)) { speed_hz = (uint32_t)strtoul(p, &endp, 10) * 1000; diff --git a/programmer.c b/programmer.c index f4b4384..ffad784 100644 --- a/programmer.c +++ b/programmer.c @@ -128,6 +128,13 @@ return 0; } +struct programmer_alias aliases[] = { + { "ec", ALIAS_EC }, + { "host", ALIAS_HOST }, + { NULL }, +}; +struct programmer_alias *alias; + enum chipbustype get_buses_supported(void) { int i; diff --git a/programmer.h b/programmer.h index 3cf53b9..a7bd947 100644 --- a/programmer.h +++ b/programmer.h @@ -130,6 +130,44 @@ PROGRAMMER_INVALID /* This must always be the last entry. */ }; +enum alias_type { + ALIAS_NONE = 0, /* no alias (default) */ + ALIAS_EC, /* embedded controller */ + ALIAS_HOST, /* chipset / PCH / SoC / etc. */ +}; + +struct programmer_alias { + const char *name; + enum alias_type type; +}; + +extern struct programmer_alias *alias; +extern struct programmer_alias aliases[]; + +/** + * This function returns 'true' if current flashrom invocation is programming + * NONE. + */ +static inline int programming_none(void) { + return alias && (alias->type == ALIAS_NONE); +} + +/** + * This function returns 'true' if current flashrom invocation is programming + * the EC. + */ +static inline int programming_ec(void) { + return alias && (alias->type == ALIAS_EC); +} + +/** + * This function returns 'true' if current flashrom invocation is programming + * the HOST. + */ +static inline int programming_host(void) { + return alias && (alias->type == ALIAS_HOST); +} + enum programmer_type { PCI = 1, /* to detect uninitialized values */ USB, -- To view, visit https://review.coreboot.org/c/flashrom/+/38671 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I73766451cd8900a9e0fe08efc7a4d81b2a35ac8d Gerrit-Change-Number: 38671 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: newchange

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Change in flashrom[master]: realtek_mst_i2c_spi.c: Introduce MCU reset param
by Edward O'Callaghan (Code Review) 02 Oct '20

02 Oct '20

Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/45674 ) Change subject: realtek_mst_i2c_spi.c: Introduce MCU reset param ...................................................................... realtek_mst_i2c_spi.c: Introduce MCU reset param Modify the spi master as to not automatically reset the MCU unless explicitly stated by a param. Change-Id: Ib70bf7399e7541f30b6905cdb950a6fb7b74ae18 Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> --- M realtek_mst_i2c_spi.c 1 file changed, 15 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/74/45674/1 diff --git a/realtek_mst_i2c_spi.c b/realtek_mst_i2c_spi.c index 6158524..6ac57d5 100644 --- a/realtek_mst_i2c_spi.c +++ b/realtek_mst_i2c_spi.c @@ -49,6 +49,7 @@ struct realtek_mst_i2c_spi_data { int fd; + int reset; }; static int realtek_mst_i2c_spi_write_data(int fd, uint16_t addr, void *buf, uint16_t len) @@ -392,14 +393,15 @@ struct realtek_mst_i2c_spi_data *realtek_mst_data = (struct realtek_mst_i2c_spi_data *)data; int fd = realtek_mst_data->fd; - ret |= realtek_mst_i2c_spi_reset_mpu(fd); + if (data->reset) + ret |= realtek_mst_i2c_spi_reset_mpu(fd); i2c_close(fd); free(data); return ret; } -static int get_params(int *i2c_bus) +static int get_params(int *i2c_bus, int *reset) { char *bus_str = NULL; int ret = SPI_GENERIC_ERROR; @@ -431,6 +433,12 @@ } else { msg_perr("%s: Bus number not specified.\n", __func__); } + + reset_str = extract_programmer_param("reset-mcu"); + if (reset_str && reset_str[0] == '1') + reset = 1; + free(reset_str); + get_params_done: if (bus_str) free(bus_str); @@ -441,9 +449,9 @@ int realtek_mst_i2c_spi_init(void) { int ret = 0; - int i2c_bus = 0; + int i2c_bus = 0, reset = 0; - if (get_params(&i2c_bus)) + if (get_params(&i2c_bus, &reset)) return SPI_GENERIC_ERROR; int fd = i2c_open(i2c_bus, REGISTER_ADDRESS, 0); @@ -451,7 +459,8 @@ return fd; /* Ensure we are in a known state before entering ISP mode */ - ret |= realtek_mst_i2c_spi_reset_mpu(fd); + if (reset) + ret |= realtek_mst_i2c_spi_reset_mpu(fd); if (ret) return ret; @@ -466,6 +475,7 @@ } data->fd = fd; + data->reset = reset; ret |= register_shutdown(realtek_mst_i2c_spi_shutdown, data); spi_master_i2c_realtek_mst.data = data; -- To view, visit https://review.coreboot.org/c/flashrom/+/45674 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Ib70bf7399e7541f30b6905cdb950a6fb7b74ae18 Gerrit-Change-Number: 45674 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: newchange

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Change in flashrom[master]: add newer pci infrastructure
by Paul Menzel (Code Review) 26 Sep '20

26 Sep '20

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/29078 ) Change subject: add newer pci infrastructure ...................................................................... Patch Set 3: (1 comment) https://review.coreboot.org/c/flashrom/+/29078/3/pcidev.c File pcidev.c: https://review.coreboot.org/c/flashrom/+/29078/3/pcidev.c@360 PS3, Line 360: cleanup clean up -- To view, visit https://review.coreboot.org/c/flashrom/+/29078 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I59af37cba5cb78014e0714c654db2501151f605e Gerrit-Change-Number: 29078 Gerrit-PatchSet: 3 Gerrit-Owner: Luc Verhaegen <libv(a)skynet.be> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Luc Verhaegen <libv(a)skynet.be> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Comment-Date: Sat, 26 Sep 2020 12:34:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in flashrom[master]: ati: initial commit
by Edward O'Callaghan (Code Review) 26 Sep '20

26 Sep '20

Edward O'Callaghan has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/29085 ) Change subject: ati: initial commit ...................................................................... Patch Set 5: Code-Review+1 (2 comments) https://review.coreboot.org/c/flashrom/+/29085/5//COMMIT_MSG Commit Message: https://review.coreboot.org/c/flashrom/+/29085/5//COMMIT_MSG@7 PS5, Line 7: ati: initial commit "stub spi master to later be used for AMD GPU programming. Just fill out the essentials for now." https://review.coreboot.org/c/flashrom/+/29085/5/Makefile File Makefile: https://review.coreboot.org/c/flashrom/+/29085/5/Makefile@1107 PS5, Line 1107: : ifeq ($(CONFIG_ATI_SPI), yes) : FEATURE_CFLAGS += -D'CONFIG_ATI_SPI=1' : PROGRAMMER_OBJS += ati_spi.o : NEED_LIBPCI += CONFIG_ATI_SPI : endif also add this to the meson build system as well please. -- To view, visit https://review.coreboot.org/c/flashrom/+/29085 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Ia5f755ae7a0723372933216516625bc156b1f4bc Gerrit-Change-Number: 29085 Gerrit-PatchSet: 5 Gerrit-Owner: Luc Verhaegen <libv(a)skynet.be> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 26 Sep 2020 02:22:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in flashrom[master]: add newer pci infrastructure
by Edward O'Callaghan (Code Review) 26 Sep '20

26 Sep '20

Edward O'Callaghan has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/29078 ) Change subject: add newer pci infrastructure ...................................................................... Patch Set 3: Code-Review+1 (7 comments) https://review.coreboot.org/c/flashrom/+/29078/3/pcidev.c File pcidev.c: https://review.coreboot.org/c/flashrom/+/29078/3/pcidev.c@351 PS3, Line 351: /* : * : */ kill these off? https://review.coreboot.org/c/flashrom/+/29078/3/pcidev.c@354 PS3, Line 354: static int : flashrom_pci_device_shutdown(void *data) one line https://review.coreboot.org/c/flashrom/+/29078/3/pcidev.c@396 PS3, Line 396: /* Filter by bb:dd.f (if supplied by the user). */ : pcidev_bdf = extract_programmer_param("pci"); : if (pcidev_bdf) { : char *msg; : : if ((msg = pci_filter_parse_slot(&filter, pcidev_bdf))) { : msg_perr("Error: %s\n", msg); : return NULL; : } : : free(pcidev_bdf); : } : put this into its own function that just extracts the param and validates the string is the correct format? https://review.coreboot.org/c/flashrom/+/29078/3/pcidev.c@445 PS3, Line 445: /* Only continue if exactly one supported PCI dev has been found. */ : if (!found) { : msg_perr("Error: No supported PCI device found.\n"); : return NULL; : } else if (found > 1) { : msg_perr("Error: Multiple supported PCI devices found. Use 'flashrom -p xxxx:pci=bb:dd.f'\n" : "to explicitly select the card with the given BDF (PCI bus, device, function).\n"); : return NULL; block seems to need to be indented to match the rest of the for-loop. I think this iterator logic can be sliced into its own static function because it would be nice to unit-test it. https://review.coreboot.org/c/flashrom/+/29078/3/pcidev.c@455 PS3, Line 455: dev validate the allocation before using it. also 'pcidev_data' seems more appropriate https://review.coreboot.org/c/flashrom/+/29078/3/programmer.h File programmer.h: https://review.coreboot.org/c/flashrom/+/29078/3/programmer.h@835 PS3, Line 835: /* programmer specific */ current comment has minimal value, could do with a little bit more explanation for users of the API. https://review.coreboot.org/c/flashrom/+/29078/3/programmer.h@852 PS3, Line 852: struct flashrom_pci_device *flashrom_pci_init(const struct flashrom_pci_match *matches); Add documentation comment in the header. -- To view, visit https://review.coreboot.org/c/flashrom/+/29078 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I59af37cba5cb78014e0714c654db2501151f605e Gerrit-Change-Number: 29078 Gerrit-PatchSet: 3 Gerrit-Owner: Luc Verhaegen <libv(a)skynet.be> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Luc Verhaegen <libv(a)skynet.be> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Comment-Date: Sat, 26 Sep 2020 02:19:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in flashrom[master]: ft2232_spi.c: Pack WREN and op in one ftdi_write_data() call
by Simon Buhrow (Code Review) 24 Sep '20

24 Sep '20

Simon Buhrow has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/40477 ) Change subject: ft2232_spi.c: Pack WREN and op in one ftdi_write_data() call ...................................................................... Patch Set 16: (2 comments) Sounds good. I hope you get time soon :-) https://review.coreboot.org/c/flashrom/+/40477/14/ft2232_spi.c File ft2232_spi.c: https://review.coreboot.org/c/flashrom/+/40477/14/ft2232_spi.c@480 PS14, Line 480: /* : * 280 bytes = : * + 9 B (CMD) : * + 1 B (WREN) : * + 9 B (CMD) : * + 1 B (op) \ : * + 4 B (addr) | = writecnt : * + 256 B (page data) / : * : * With op: PageProgram or Erase; CMD: FTDI-Chip commands : */ > nit: I'd place this before the assignment to `bufsize`. […] Done https://review.coreboot.org/c/flashrom/+/40477/14/ft2232_spi.c@555 PS14, Line 555: /* Return to get second op (Program or Erase) without : * resetting buf nor i*/ > Comment style should be: […] Done -- To view, visit https://review.coreboot.org/c/flashrom/+/40477 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Ie4a07499ec5ef0af23818593f45dc427285a9e8a Gerrit-Change-Number: 40477 Gerrit-PatchSet: 16 Gerrit-Owner: Simon Buhrow Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Georgi <pgeorgi(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Thu, 24 Sep 2020 11:53:54 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in flashrom[master]: ft2232_spi.c: Pack WREN and op in one ftdi_write_data() call
by Simon Buhrow (Code Review) 24 Sep '20

24 Sep '20

Hello build bot (Jenkins), Angel Pons, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/flashrom/+/40477 to look at the new patch set (#15). Change subject: ft2232_spi.c: Pack WREN and op in one ftdi_write_data() call ...................................................................... ft2232_spi.c: Pack WREN and op in one ftdi_write_data() call Every ftdi_write_data() call is quite time consuming as the ftdi-chips seems to take always 2-3ms to respond. This leads to what the comment already says: Minimize USB transfers by packing as many commands as possible together. So I packed the WREN command together with the following operation which can be program or erase operation. This saves about 1 minute when programming a 128MBit Flash with my config! I´m using ftdi-2232H chip. That´s why I put it at this place. If anyone has a good overview about all programmers: This could be implemented in spi_write_cmd() in case that it is compatible to all programmers or this principle could be transfered to other programmers which act in a similar way. Signed-off-by: Simon Buhrow <simon.buhrow(a)posteo.de> Change-Id: Ie4a07499ec5ef0af23818593f45dc427285a9e8a --- M ft2232_spi.c 1 file changed, 28 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/77/40477/15 -- To view, visit https://review.coreboot.org/c/flashrom/+/40477 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Ie4a07499ec5ef0af23818593f45dc427285a9e8a Gerrit-Change-Number: 40477 Gerrit-PatchSet: 15 Gerrit-Owner: Simon Buhrow Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Georgi <pgeorgi(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in flashrom[master]: Add support for Comet Lake-U/400-series PCH
by Matt DeVillier (Code Review) 24 Sep '20

24 Sep '20

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/44420 ) Change subject: Add support for Comet Lake-U/400-series PCH ...................................................................... Add support for Comet Lake-U/400-series PCH Add enum CHIPSET_400_SERIES_COMET_POINT and treat it identically to CHIPSET_300_SERIES_CANNON_POINT. Add PCI ID for Comet Lake-U Premium and classify as CHIPSET_400_SERIES_COMET_POINT. Test: read/write unlocked CML-U board Change-Id: I43b4ad1eecfed16fec59863e46d4e997fbe45f1b Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M chipset_enable.c M ich_descriptors.c M ichspi.c M programmer.h M util/ich_descriptors_tool/ich_descriptors_tool.c 5 files changed, 32 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/20/44420/1 diff --git a/chipset_enable.c b/chipset_enable.c index d56a547..c01deb2 100644 --- a/chipset_enable.c +++ b/chipset_enable.c @@ -599,6 +599,7 @@ case CHIPSET_100_SERIES_SUNRISE_POINT: case CHIPSET_C620_SERIES_LEWISBURG: case CHIPSET_300_SERIES_CANNON_POINT: + case CHIPSET_400_SERIES_COMET_POINT: case CHIPSET_APOLLO_LAKE: reg_name = "BIOS_SPI_BC"; gcs = pci_read_long(dev, 0xdc); @@ -694,6 +695,7 @@ case CHIPSET_100_SERIES_SUNRISE_POINT: case CHIPSET_C620_SERIES_LEWISBURG: case CHIPSET_300_SERIES_CANNON_POINT: + case CHIPSET_400_SERIES_COMET_POINT: boot_straps = boot_straps_pch8_lp; break; case CHIPSET_APOLLO_LAKE: @@ -722,6 +724,7 @@ case CHIPSET_100_SERIES_SUNRISE_POINT: case CHIPSET_C620_SERIES_LEWISBURG: case CHIPSET_300_SERIES_CANNON_POINT: + case CHIPSET_400_SERIES_COMET_POINT: case CHIPSET_APOLLO_LAKE: bbs = (gcs >> 6) & 0x1; break; @@ -963,6 +966,11 @@ return enable_flash_pch100_or_c620(dev, name, 0x1f, 5, CHIPSET_300_SERIES_CANNON_POINT); } +static int enable_flash_pch400(struct pci_dev *const dev, const char *const name) +{ + return enable_flash_pch100_or_c620(dev, name, 0x1f, 5, CHIPSET_400_SERIES_COMET_POINT); +} + static int enable_flash_apl(struct pci_dev *const dev, const char *const name) { return enable_flash_pch100_or_c620(dev, name, 0x0d, 2, CHIPSET_APOLLO_LAKE); @@ -2004,6 +2012,7 @@ {0x8086, 0x9d56, B_S, NT, "Intel", "Kaby Lake Y Premium", enable_flash_pch100}, {0x8086, 0x9d58, B_S, NT, "Intel", "Kaby Lake U Premium", enable_flash_pch100}, {0x8086, 0x9d84, B_S, DEP, "Intel", "Cannon Lake U Premium", enable_flash_pch300}, + {0x8086, 0x0284, B_S, DEP, "Intel", "Comet Lake U Premium", enable_flash_pch400}, {0x8086, 0xa141, B_S, NT, "Intel", "Sunrise Point Desktop Sample", enable_flash_pch100}, {0x8086, 0xa142, B_S, NT, "Intel", "Sunrise Point Unknown Sample", enable_flash_pch100}, {0x8086, 0xa143, B_S, NT, "Intel", "H110", enable_flash_pch100}, diff --git a/ich_descriptors.c b/ich_descriptors.c index 120d3fe..315e086 100644 --- a/ich_descriptors.c +++ b/ich_descriptors.c @@ -42,6 +42,7 @@ return 6; case CHIPSET_C620_SERIES_LEWISBURG: case CHIPSET_300_SERIES_CANNON_POINT: + case CHIPSET_400_SERIES_COMET_POINT: return 16; case CHIPSET_100_SERIES_SUNRISE_POINT: return 10; @@ -196,6 +197,7 @@ case CHIPSET_100_SERIES_SUNRISE_POINT: case CHIPSET_C620_SERIES_LEWISBURG: case CHIPSET_300_SERIES_CANNON_POINT: + case CHIPSET_400_SERIES_COMET_POINT: case CHIPSET_APOLLO_LAKE: { uint8_t size_enc; if (idx == 0) { @@ -264,6 +266,7 @@ case CHIPSET_100_SERIES_SUNRISE_POINT: case CHIPSET_C620_SERIES_LEWISBURG: case CHIPSET_300_SERIES_CANNON_POINT: + case CHIPSET_400_SERIES_COMET_POINT: return freq_str[1][value]; case CHIPSET_APOLLO_LAKE: return freq_str[2][value]; @@ -281,6 +284,7 @@ case CHIPSET_100_SERIES_SUNRISE_POINT: case CHIPSET_C620_SERIES_LEWISBURG: case CHIPSET_300_SERIES_CANNON_POINT: + case CHIPSET_400_SERIES_COMET_POINT: case CHIPSET_APOLLO_LAKE: has_flill1 = true; break; @@ -399,7 +403,8 @@ msg_pdbg2("--- Details ---\n"); if (cs == CHIPSET_100_SERIES_SUNRISE_POINT || - cs == CHIPSET_300_SERIES_CANNON_POINT) { + cs == CHIPSET_300_SERIES_CANNON_POINT || + cs == CHIPSET_400_SERIES_COMET_POINT) { const char *const master_names[] = { "BIOS", "ME", "GbE", "unknown", "EC", }; @@ -957,6 +962,7 @@ switch (guess) { case CHIPSET_300_SERIES_CANNON_POINT: + case CHIPSET_400_SERIES_COMET_POINT: /* `freq_read` was repurposed, so can't check on it any more. */ return guess; case CHIPSET_100_SERIES_SUNRISE_POINT: @@ -1111,6 +1117,7 @@ case CHIPSET_100_SERIES_SUNRISE_POINT: case CHIPSET_C620_SERIES_LEWISBURG: case CHIPSET_300_SERIES_CANNON_POINT: + case CHIPSET_400_SERIES_COMET_POINT: case CHIPSET_APOLLO_LAKE: if (idx == 0) { size_enc = desc->component.dens_new.comp1_density; @@ -1146,6 +1153,7 @@ case CHIPSET_100_SERIES_SUNRISE_POINT: case CHIPSET_C620_SERIES_LEWISBURG: case CHIPSET_300_SERIES_CANNON_POINT: + case CHIPSET_400_SERIES_COMET_POINT: case CHIPSET_APOLLO_LAKE: mmio_le_writel(control, spibar + PCH100_REG_FDOC); return mmio_le_readl(spibar + PCH100_REG_FDOD); diff --git a/ichspi.c b/ichspi.c index 4dbe69a..4209d60 100644 --- a/ichspi.c +++ b/ichspi.c @@ -399,6 +399,7 @@ case CHIPSET_100_SERIES_SUNRISE_POINT: case CHIPSET_C620_SERIES_LEWISBURG: case CHIPSET_300_SERIES_CANNON_POINT: + case CHIPSET_400_SERIES_COMET_POINT: break; default: pprint_reg(HSFS, BERASE, reg_val, ", "); @@ -409,6 +410,7 @@ case CHIPSET_100_SERIES_SUNRISE_POINT: case CHIPSET_C620_SERIES_LEWISBURG: case CHIPSET_300_SERIES_CANNON_POINT: + case CHIPSET_400_SERIES_COMET_POINT: pprint_reg(HSFS, PRR34_LOCKDN, reg_val, ", "); pprint_reg(HSFS, WRSDIS, reg_val, ", "); break; @@ -428,6 +430,7 @@ case CHIPSET_100_SERIES_SUNRISE_POINT: case CHIPSET_C620_SERIES_LEWISBURG: case CHIPSET_300_SERIES_CANNON_POINT: + case CHIPSET_400_SERIES_COMET_POINT: _pprint_reg(HSFC, PCH100_HSFC_FCYCLE, PCH100_HSFC_FCYCLE_OFF, reg_val, ", "); pprint_reg(HSFC, WET, reg_val, ", "); break; @@ -1741,6 +1744,7 @@ case CHIPSET_100_SERIES_SUNRISE_POINT: case CHIPSET_C620_SERIES_LEWISBURG: case CHIPSET_300_SERIES_CANNON_POINT: + case CHIPSET_400_SERIES_COMET_POINT: case CHIPSET_APOLLO_LAKE: num_pr = 6; /* Includes GPR0 */ reg_pr0 = PCH100_REG_FPR0; @@ -1772,6 +1776,7 @@ num_freg = 12; /* 12 MMIO regs, but 16 regions in FD spec */ break; case CHIPSET_300_SERIES_CANNON_POINT: + case CHIPSET_400_SERIES_COMET_POINT: case CHIPSET_APOLLO_LAKE: num_freg = 16; break; @@ -1867,6 +1872,7 @@ case CHIPSET_100_SERIES_SUNRISE_POINT: case CHIPSET_C620_SERIES_LEWISBURG: case CHIPSET_300_SERIES_CANNON_POINT: + case CHIPSET_400_SERIES_COMET_POINT: case CHIPSET_APOLLO_LAKE: tmp = mmio_readl(spibar + PCH100_REG_DLOCK); msg_pdbg("0x0c: 0x%08x (DLOCK)\n", tmp); @@ -1941,6 +1947,7 @@ case CHIPSET_100_SERIES_SUNRISE_POINT: case CHIPSET_C620_SERIES_LEWISBURG: case CHIPSET_300_SERIES_CANNON_POINT: + case CHIPSET_400_SERIES_COMET_POINT: case CHIPSET_APOLLO_LAKE: case CHIPSET_BAYTRAIL: break; @@ -1973,6 +1980,7 @@ case CHIPSET_100_SERIES_SUNRISE_POINT: case CHIPSET_C620_SERIES_LEWISBURG: case CHIPSET_300_SERIES_CANNON_POINT: + case CHIPSET_400_SERIES_COMET_POINT: case CHIPSET_APOLLO_LAKE: break; default: @@ -2004,7 +2012,8 @@ if (ich_spi_mode == ich_auto && (ich_gen == CHIPSET_100_SERIES_SUNRISE_POINT || - ich_gen == CHIPSET_300_SERIES_CANNON_POINT)) { + ich_gen == CHIPSET_300_SERIES_CANNON_POINT || + ich_gen == CHIPSET_400_SERIES_COMET_POINT)) { msg_pdbg("Enabling hardware sequencing by default for 100+ series PCH.\n"); ich_spi_mode = ich_hwseq; } diff --git a/programmer.h b/programmer.h index c5cab18..780fcb0 100644 --- a/programmer.h +++ b/programmer.h @@ -660,6 +660,7 @@ CHIPSET_C620_SERIES_LEWISBURG, CHIPSET_300_SERIES_CANNON_POINT, CHIPSET_APOLLO_LAKE, + CHIPSET_400_SERIES_COMET_POINT, }; /* ichspi.c */ diff --git a/util/ich_descriptors_tool/ich_descriptors_tool.c b/util/ich_descriptors_tool/ich_descriptors_tool.c index 6f13749..32eea12 100644 --- a/util/ich_descriptors_tool/ich_descriptors_tool.c +++ b/util/ich_descriptors_tool/ich_descriptors_tool.c @@ -225,6 +225,9 @@ else if ((strcmp(csn, "300") == 0) || (strcmp(csn, "cannon") == 0)) cs = CHIPSET_300_SERIES_CANNON_POINT; + else if ((strcmp(csn, "400") == 0) || + (strcmp(csn, "comet") == 0)) + cs = CHIPSET_400_SERIES_COMET_POINT; else if (strcmp(csn, "apollo") == 0) cs = CHIPSET_APOLLO_LAKE; } -- To view, visit https://review.coreboot.org/c/flashrom/+/44420 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I43b4ad1eecfed16fec59863e46d4e997fbe45f1b Gerrit-Change-Number: 44420 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: newchange

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Change in flashrom[master]: dummyflasher.c: Upstream ChromiumOS 'freq' param feature
by Edward O'Callaghan (Code Review) 22 Sep '20

22 Sep '20

Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/45461 ) Change subject: dummyflasher.c: Upstream ChromiumOS 'freq' param feature ...................................................................... dummyflasher.c: Upstream ChromiumOS 'freq' param feature This allows the dummyflasher to emulate a bus/chip frequency by passing a delay parameter. BUG=b:140394053 BRANCH=none TEST=builds and ran with freq passed, ``` └──╼ dd if=/dev/urandom of=/tmp/bar bs=2K count=1 1+0 records in 1+0 records out 2048 bytes (2.0 kB, 2.0 KiB) copied, 0.000583308 s, 3.5 MB/s └──╼ ./flashrom -p dummy:image=/tmp/foo,bus=spi,freq=100Hz,size=2048,emulate=VARIABLE_SIZE -w /tmp/bar flashrom v1.2-105-g702c58a-dirty on Linux 5.7.10-1rodete2-amd64 (x86_64) flashrom is free software, get the source code at https://flashrom.org Using clock_gettime for delay loops (clk_id: 1, resolution: 1ns). Found Generic flash chip "Variable Size SPI chip" (2 kB, SPI) on dummy. Reading old flash chip contents... done. Erasing and writing flash chip... Erase/write done. Verifying flash... VERIFIED. ``` Change-Id: I1c2702b9e0cae860f5f03114e307707d4d3219af Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> --- M dummyflasher.c 1 file changed, 49 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/61/45461/1 diff --git a/dummyflasher.c b/dummyflasher.c index 89e8ba4..8af982d 100644 --- a/dummyflasher.c +++ b/dummyflasher.c @@ -54,6 +54,9 @@ unsigned int emu_chip_size; int emu_modified; /* is the image modified since reading it? */ uint8_t emu_status; + /* If "freq" parameter is passed in from command line, commands will delay + * for this period before returning. */ + unsigned long int delay_us; unsigned int emu_max_byteprogram_size; unsigned int emu_max_aai_size; unsigned int emu_jedec_se_size; @@ -175,6 +178,7 @@ return 1; } data->emu_chip = EMULATE_NONE; + data->delay_us = 0; spi_master_dummyflasher.data = data; msg_pspew("%s\n", __func__); @@ -289,6 +293,49 @@ } free(tmp); + /* frequency to emulate in Hz (default), KHz, or MHz */ + tmp = extract_programmer_param("freq"); + if (tmp) { + unsigned long int freq; + char *units = tmp; + char *end = tmp + strlen(tmp); + + errno = 0; + freq = strtoul(tmp, &units, 0); + if (errno) { + msg_perr("Invalid frequency \"%s\", %s\n", + tmp, strerror(errno)); + goto dummy_init_out; + } + + if ((units > tmp) && (units < end)) { + int units_valid = 0; + + if (units < end - 3) { + ; + } else if (units == end - 2) { + if (!strcasecmp(units, "hz")) + units_valid = 1; + } else if (units == end - 3) { + if (!strcasecmp(units, "khz")) { + freq *= 1000; + units_valid = 1; + } else if (!strcasecmp(units, "mhz")) { + freq *= 1000000; + units_valid = 1; + } + } + + if (!units_valid) { + msg_perr("Invalid units: %s\n", units); + return 1; + } + } + + /* Assume we only work with bytes and transfer at 1 bit/Hz */ + data->delay_us = (1000000 * 8) / freq; + } + #if EMULATE_CHIP #if EMULATE_SPI_CHIP tmp = extract_programmer_param("size"); @@ -963,6 +1010,8 @@ for (i = 0; i < readcnt; i++) msg_pspew(" 0x%02x", readarr[i]); msg_pspew("\n"); + + programmer_delay((writecnt + readcnt) * emu_data->delay_us); return 0; } -- To view, visit https://review.coreboot.org/c/flashrom/+/45461 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I1c2702b9e0cae860f5f03114e307707d4d3219af Gerrit-Change-Number: 45461 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: newchange

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