May 2020 - flashrom-gerrit - mail.coreboot.org

Change in flashrom[master]: realtek_mst_i2c_spi.c: Fix _spi_send_command cb for erasures
by Edward O'Callaghan (Code Review) May 6, 2020

May 6, 2020

Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/41079 ) Change subject: realtek_mst_i2c_spi.c: Fix _spi_send_command cb for erasures ...................................................................... realtek_mst_i2c_spi.c: Fix _spi_send_command cb for erasures Before issuing SPI opcodes into 0x61 the top three BITS of 0x60 need to be carefully crafted. Correctly craft these in the case of SPI erasures and document this registers expectations. Clean up remaining debug comments while we are here. BUG=b:152558985,b:148745673 BRANCH=none TEST=flashrom -p realtek_mst_i2c_spi:bus=8 -E && flashrom -p realtek_mst_i2c_spi:bus=8 -r foo && hexdump -C foo Change-Id: Ib11ba8f63b11a1c5ebaa68deb7971648de8c2ecd Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> --- M realtek_mst_i2c_spi.c 1 file changed, 40 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/79/41079/1 diff --git a/realtek_mst_i2c_spi.c b/realtek_mst_i2c_spi.c index 2dd4936..682d4a6 100644 --- a/realtek_mst_i2c_spi.c +++ b/realtek_mst_i2c_spi.c @@ -196,21 +196,55 @@ int ret = 0; if (writecnt > 4 || readcnt > 3 || writecnt == 0) { - //msg_perr("%s: Invalid read/write count for send command.\n", __func__); return SPI_GENERIC_ERROR; } - //printf("%s: writearr[0]=0x%x\n", __func__, writearr[0]); int fd = get_fd_from_context(flash); if (fd < 0) return SPI_GENERIC_ERROR; - /* First byte of writearr should be the command value, followed by the value to write. */ - // 0xFF60 = cmd; + /* First byte of writearr should be the spi opcode value, followed by the value to write. */ writecnt--; - uint8_t ctrl_reg_val = (writecnt << 3) | (readcnt << 1) | (2 << 5); + + /** + * Before dispatching a SPI opcode the MCU register 0x60 requires + * the following configuration byte set: + * + * BIT0 - start [0] , end [1]. + * BITS[1-4] - counts. + * BITS[5-7] - opcode type. + * + * | bit7 | bit6 | bit5 | + * +------+------+------+ + * | 0 | 1 | 0 | ~ JEDEC_RDID,REMS,READ + * | 0 | 1 | 1 | ~ JEDEC_WRSR + * | 1 | 0 | 1 | ~ JEDEC_.. erasures. + */ + uint8_t ctrl_reg_val = (writecnt << 3) | (readcnt << 1); + switch (writearr[0]) { + /* WREN isn't a supported somehow? ignore it. */ + case JEDEC_WREN: return 0; + /* WRSR requires BIT6 && BIT5 set. */ + case JEDEC_WRSR: + ctrl_reg_val |= (1 << 5); + ctrl_reg_val |= (2 << 5); + break; + /* Erasures require BIT7 && BIT5 set. */ + case JEDEC_CE_60: + case JEDEC_CE_C7: + case JEDEC_BE_52: + case JEDEC_BE_D8: + case JEDEC_BE_D7: + case JEDEC_SE: + ctrl_reg_val |= (1 << 5); + ctrl_reg_val |= (4 << 5); + break; + default: + /* Otherwise things like RDID,REMS,READ require BIT6 */ + ctrl_reg_val |= (2 << 5); + } ret |= realtek_mst_i2c_spi_write_register(fd, 0x60, ctrl_reg_val); - ret |= realtek_mst_i2c_spi_write_register(fd, 0x61, writearr[0]); + ret |= realtek_mst_i2c_spi_write_register(fd, 0x61, writearr[0]); /* opcode */ for (i = 0; i < writecnt; ++i) ret |= realtek_mst_i2c_spi_write_register(fd, 0x64 + i, writearr[i + 1]); @@ -225,9 +259,6 @@ for (i = 0; i < readcnt; ++i) ret |= realtek_mst_i2c_spi_read_register(fd, 0x67 + i, &readarr[i]); - //for (i = 0; i< readcnt; i++) - // printf("DEBUG: readarr[%d]=0x%02x\n", i, readarr[i]); - return ret; } -- To view, visit https://review.coreboot.org/c/flashrom/+/41079 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Ib11ba8f63b11a1c5ebaa68deb7971648de8c2ecd Gerrit-Change-Number: 41079 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: newchange

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Change in flashrom[master]: raiden_debug_spi: Fix memleak
by Patrick Georgi (Code Review) May 5, 2020

May 5, 2020

Patrick Georgi has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/40969 ) Change subject: raiden_debug_spi: Fix memleak ...................................................................... raiden_debug_spi: Fix memleak Change-Id: Ib9d99fefda812d20265db47be353c844f8b77129 Found-by: Coverity Scan #1420204 Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> --- M raiden_debug_spi.c 1 file changed, 3 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/69/40969/1 diff --git a/raiden_debug_spi.c b/raiden_debug_spi.c index 306d8fb..57cc659 100644 --- a/raiden_debug_spi.c +++ b/raiden_debug_spi.c @@ -467,8 +467,10 @@ int ret; int request_enable = get_target(); - if (request_enable < 0) + if (request_enable < 0) { + free(serial); return 1; + } usb_match_init(&match); -- To view, visit https://review.coreboot.org/c/flashrom/+/40969 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Ib9d99fefda812d20265db47be353c844f8b77129 Gerrit-Change-Number: 40969 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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Change in flashrom[master]: spi95: Check for success before using send_command's returned data
by Patrick Georgi (Code Review) May 5, 2020

May 5, 2020

Patrick Georgi has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/40970 ) Change subject: spi95: Check for success before using send_command's returned data ...................................................................... spi95: Check for success before using send_command's returned data If the transfer failed, the data might be invalid. Change-Id: I3ad9daa00a54e2a3954983cec91b6685f1a98880 Found-By: Coverity Scan #1405870 Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> --- M spi95.c 1 file changed, 4 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/70/40970/1 diff --git a/spi95.c b/spi95.c index ecb2c1d..976f99a 100644 --- a/spi95.c +++ b/spi95.c @@ -33,12 +33,15 @@ static const unsigned char cmd[ST_M95_RDID_OUTSIZE_MAX] = { ST_M95_RDID }; unsigned char readarr[ST_M95_RDID_INSIZE]; uint32_t id1, id2; + int ret; uint32_t rdid_outsize = ST_M95_RDID_2BA_OUTSIZE; // 16 bit address if (flash->chip->total_size * KiB > 64 * KiB) rdid_outsize = ST_M95_RDID_3BA_OUTSIZE; // 24 bit address - spi_send_command(flash, rdid_outsize, sizeof(readarr), cmd, readarr); + ret = spi_send_command(flash, rdid_outsize, sizeof(readarr), cmd, readarr); + if (ret) + return ret; id1 = readarr[0]; // manufacture id id2 = (readarr[1] << 8) | readarr[2]; // SPI family code + model id -- To view, visit https://review.coreboot.org/c/flashrom/+/40970 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I3ad9daa00a54e2a3954983cec91b6685f1a98880 Gerrit-Change-Number: 40970 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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Change in flashrom[master]: realtek_mst_i2c_spi.c: Add bootloader slot param
by Edward O'Callaghan (Code Review) May 5, 2020

May 5, 2020

Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/40772 ) Change subject: realtek_mst_i2c_spi.c: Add bootloader slot param ...................................................................... realtek_mst_i2c_spi.c: Add bootloader slot param Add spi_master parameter that allows the user to specify which firmware paritition slot to select in the bootloader upon flashing a new image. BUG=b:155051790 BRANCH=none TEST=builds Change-Id: I1fa6b30ea67e7feb0651dd4b4dc3d5c308fc83c8 Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> --- M realtek_mst_i2c_spi.c 1 file changed, 23 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/72/40772/1 diff --git a/realtek_mst_i2c_spi.c b/realtek_mst_i2c_spi.c index 6f7dd70..03c0893 100644 --- a/realtek_mst_i2c_spi.c +++ b/realtek_mst_i2c_spi.c @@ -38,6 +38,7 @@ struct realtek_mst_i2c_spi_data { int fd; + int slot; /* 0: slot A, 1: slot B, -1: undefined slot */ }; static int realtek_mst_i2c_spi_write_data(int fd, uint16_t addr, void *buf, uint16_t len) @@ -355,9 +356,9 @@ return ret; } -static int get_params(int *i2c_bus) +static int get_params(int *i2c_bus, int *slot) { - char *bus_str = NULL; + char *bus_str = NULL, *slot_str = NULL; int ret = SPI_GENERIC_ERROR; bus_str = extract_programmer_param("bus"); @@ -387,9 +388,26 @@ } else { msg_perr("%s: Bus number not specified.\n", __func__); } + + slot_str = extract_programmer_param("slot"); + if (slot_str) { + msg_pinfo("Using bootloader slot %s.\n", slot_str); + switch (slot_str[0]) { + case 'A': *slot = 0; break; + case 'B': *slot = 1; break; + default: + msg_perr("%s: Invalid slot specified.\n", __func__); + *slot = -1; + } + ret = 0; + goto get_params_done; + } + get_params_done: if (bus_str) free(bus_str); + if (slot_str) + free(slot_str); return ret; } @@ -397,9 +415,9 @@ int realtek_mst_i2c_spi_init(void) { int ret = 0; - int i2c_bus = 0; + int i2c_bus = 0, bl_slot = 0; - if (get_params(&i2c_bus)) + if (get_params(&i2c_bus, &bl_slot)) return SPI_GENERIC_ERROR; int fd = i2c_open(i2c_bus, REGISTER_ADDRESS, 0); @@ -428,6 +446,7 @@ } data->fd = fd; + data->slot = bl_slot; ret |= register_shutdown(realtek_mst_i2c_spi_shutdown, data); spi_master_i2c_realtek_mst.data = data; -- To view, visit https://review.coreboot.org/c/flashrom/+/40772 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I1fa6b30ea67e7feb0651dd4b4dc3d5c308fc83c8 Gerrit-Change-Number: 40772 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: newchange

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Change in flashrom[master]: spi25: Debug flashrom crash when Write Protect is ON
by Stefan Reinauer (Code Review) May 5, 2020

May 5, 2020

Stefan Reinauer has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/40468 ) Change subject: spi25: Debug flashrom crash when Write Protect is ON ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/flashrom/+/40468 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I81094ab5f16a85871fc9869a2e285eddbbbdec4e Gerrit-Change-Number: 40468 Gerrit-PatchSet: 4 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: SANTHOSH JANARDHANA HASSAN <sahassan(a)google.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Yuji Sasaki <sasakiy(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 05 May 2020 05:46:56 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in flashrom[master]: raiden_debug_spi.c: Clean up global state
by Edward O'Callaghan (Code Review) May 5, 2020

May 5, 2020

Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/40105 ) Change subject: raiden_debug_spi.c: Clean up global state ...................................................................... raiden_debug_spi.c: Clean up global state The Chromium flashrom fork has very poor dispatch logic whereas upstream has proper inversion of control with a generic 'data' void * member for stuff long-lived state in. Leverage the member to store the USB descriptor state in during the life-time of the spi master. BUG=b:140394053 BRANCH=none TEST=builds Change-Id: Ida9dce97fef2c6dfd68a278c879917fdd3ff7fef Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> --- M raiden_debug_spi.c 1 file changed, 48 insertions(+), 15 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/05/40105/1 diff --git a/raiden_debug_spi.c b/raiden_debug_spi.c index 173e355..913ee45 100644 --- a/raiden_debug_spi.c +++ b/raiden_debug_spi.c @@ -161,9 +161,11 @@ */ #define TRANSFER_TIMEOUT_MS (200 + 800) -struct usb_device *device = NULL; -uint8_t in_endpoint = 0; -uint8_t out_endpoint = 0; +struct raiden_debug_spi_data { + struct usb_device *dev; + uint8_t in_ep; + uint8_t out_ep; +}; typedef struct { int8_t write_count; @@ -200,6 +202,12 @@ return true; } +static const struct raiden_debug_spi_data * + get_raiden_data_from_context(const struct flashctx *flash) +{ + return (const struct raiden_debug_spi_data *)flash->mst->spi.data; +} + static int write_command(const struct flashctx *flash, unsigned int write_count, unsigned int read_count, @@ -210,6 +218,7 @@ int transferred; int ret; usb_spi_command_t command_packet; + const struct raiden_debug_spi_data * ctx_data = get_raiden_data_from_context(flash); if (write_count > PAYLOAD_SIZE) { msg_perr("Raiden: Invalid write_count of %d\n", write_count); @@ -226,8 +235,8 @@ memcpy(command_packet.data, write_buffer, write_count); - ret = LIBUSB(libusb_bulk_transfer(device->handle, - out_endpoint, + ret = LIBUSB(libusb_bulk_transfer(ctx_data->dev->handle, + ctx_data->out_ep, (void*)&command_packet, write_count + PACKET_HEADER_SIZE, &transferred, @@ -258,9 +267,10 @@ int transferred; int ret; usb_spi_response_t response_packet; + const struct raiden_debug_spi_data * ctx_data = get_raiden_data_from_context(flash); - ret = LIBUSB(libusb_bulk_transfer(device->handle, - in_endpoint, + ret = LIBUSB(libusb_bulk_transfer(ctx_data->dev->handle, + ctx_data->in_ep, (void*)&response_packet, read_count + PACKET_HEADER_SIZE, &transferred, @@ -403,16 +413,19 @@ return 0; } -static int shutdown(void * data) +static int raiden_debug_spi_shutdown(void * data) { + struct raiden_debug_spi_data * ctx_data = + (struct raiden_debug_spi_data *)data; + int ret = LIBUSB(libusb_control_transfer( - device->handle, + ctx_data->dev->handle, LIBUSB_ENDPOINT_OUT | LIBUSB_REQUEST_TYPE_VENDOR | LIBUSB_RECIPIENT_INTERFACE, RAIDEN_DEBUG_SPI_REQ_DISABLE, 0, - device->interface_descriptor->bInterfaceNumber, + ctx_data->dev->interface_descriptor->bInterfaceNumber, NULL, 0, TRANSFER_TIMEOUT_MS)); @@ -421,10 +434,9 @@ return ret; } - usb_device_free(device); - - device = NULL; + usb_device_free(ctx_data->dev); libusb_exit(NULL); + free(ctx_data); return 0; } @@ -458,11 +470,20 @@ dev = usb_device_free(dev); } +static int register_raiden_debug_spi_master(void *ptr) +{ + struct spi_master mst = spi_master_raiden_debug; + mst.data = ptr; + + return register_spi_master(&mst); +} + int raiden_debug_spi_init(void) { struct usb_match match; char *serial = extract_programmer_param("serial"); struct usb_device *current; + struct usb_device *device = NULL; int found = 0; int ret; @@ -489,6 +510,8 @@ return ret; } + uint8_t in_endpoint = 0; + uint8_t out_endpoint = 0; while (current) { device = current; @@ -576,8 +599,18 @@ (request_enable == RAIDEN_DEBUG_SPI_REQ_ENABLE_EC)) usleep(50 * 1000); - register_spi_master(&spi_master_raiden_debug); - register_shutdown(shutdown, NULL); + struct raiden_debug_spi_data *data = calloc(1, sizeof(struct raiden_debug_spi_data)); + if (!data) { + msg_perr("Unable to allocate space for extra SPI master data.\n"); + return SPI_GENERIC_ERROR; + } + + data->dev = device; + data->in_ep = in_endpoint; + data->out_ep = out_endpoint; + + register_raiden_debug_spi_master(data); + register_shutdown(raiden_debug_spi_shutdown, data); return 0; } -- To view, visit https://review.coreboot.org/c/flashrom/+/40105 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Ida9dce97fef2c6dfd68a278c879917fdd3ff7fef Gerrit-Change-Number: 40105 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: newchange

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Change in flashrom[master]: realtek_mst_i2c_spi.c: Define some register names
by Edward O'Callaghan (Code Review) May 5, 2020

May 5, 2020

Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/41022 ) Change subject: realtek_mst_i2c_spi.c: Define some register names ...................................................................... realtek_mst_i2c_spi.c: Define some register names Try to document some of the register magics with plausible names for readability. BUG=b:152558985,b:148745673 BRANCH=none TEST=builds Change-Id: I97313f6f14438e4cbfc62faa7242cf6fc271f387 Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> --- M realtek_mst_i2c_spi.c 1 file changed, 14 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/22/41022/1 diff --git a/realtek_mst_i2c_spi.c b/realtek_mst_i2c_spi.c index ba41ed2..2dd4936 100644 --- a/realtek_mst_i2c_spi.c +++ b/realtek_mst_i2c_spi.c @@ -31,6 +31,15 @@ #define PAGE_SIZE 256 #define MAX_SPI_WAIT_RETRIES 1000 +#define MCU_MODE 0x6F +#define ENTER_ISP_MODE 0x80 + +#define MCU_DATA_PORT 0x70 + +#define MAP_PAGE_BYTE2 0x64 +#define MAP_PAGE_BYTE1 0x65 +#define MAP_PAGE_BYTE0 0x66 + //opcodes #define OPCODE_READ 3 #define OPCODE_WRITE 2 @@ -104,8 +113,7 @@ static int realtek_mst_i2c_spi_enter_isp_mode(int fd) { - // 0xFF6F = 0x80; - int ret = realtek_mst_i2c_spi_write_register(fd, 0x6F, 0x80); // enter isp mode + int ret = realtek_mst_i2c_spi_write_register(fd, MCU_MODE, ENTER_ISP_MODE); // set internal osc divider register to default to speed up MCU // 0x06A0 = 0x74 @@ -226,9 +234,9 @@ static int realtek_mst_i2c_spi_map_page(int fd, uint8_t block_idx, uint8_t page_idx, uint8_t byte_idx) { int ret = 0; - ret |= realtek_mst_i2c_spi_write_register(fd, 0x64, block_idx); - ret |= realtek_mst_i2c_spi_write_register(fd, 0x65, page_idx); - ret |= realtek_mst_i2c_spi_write_register(fd, 0x66, byte_idx); + ret |= realtek_mst_i2c_spi_write_register(fd, MAP_PAGE_BYTE2, block_idx); + ret |= realtek_mst_i2c_spi_write_register(fd, MAP_PAGE_BYTE1, page_idx); + ret |= realtek_mst_i2c_spi_write_register(fd, MAP_PAGE_BYTE0, byte_idx); return ret ? SPI_GENERIC_ERROR : 0; } @@ -267,7 +275,7 @@ * Advance the read by a offset of one byte and continue. */ uint8_t dummy; - realtek_mst_i2c_spi_read_register(fd, 0x70, &dummy); + realtek_mst_i2c_spi_read_register(fd, MCU_DATA_PORT, &dummy); for (i = 0; i < len; i += PAGE_SIZE) { ret |= realtek_mst_i2c_spi_read_data(fd, REGISTER_ADDRESS, -- To view, visit https://review.coreboot.org/c/flashrom/+/41022 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I97313f6f14438e4cbfc62faa7242cf6fc271f387 Gerrit-Change-Number: 41022 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: newchange

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Change in flashrom[master]: ft2232_spi.c: Pack WREN and op in one ftdi_write_data() call to save ...
by Patrick Georgi (Code Review) May 4, 2020

May 4, 2020

Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/40477 ) Change subject: ft2232_spi.c: Pack WREN and op in one ftdi_write_data() call to save programming time ...................................................................... Patch Set 8: > Patch Set 8: > > Is that good practice to add reviewers by myself? Sure, if you think somebody is a suitable reviewer, add them (but not just "anybody"). Just respect if they remove themselves from a commit and you're all set. -- To view, visit https://review.coreboot.org/c/flashrom/+/40477 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Ie4a07499ec5ef0af23818593f45dc427285a9e8a Gerrit-Change-Number: 40477 Gerrit-PatchSet: 8 Gerrit-Owner: Simon Buhrow Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Georgi <pgeorgi(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Mon, 04 May 2020 19:16:02 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in flashrom[master]: Makefile: Remove LSPCON_I2C_SPI dependency on libusb
by Shiyu Sun (Code Review) May 4, 2020

May 4, 2020

Shiyu Sun has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/41021 ) Change subject: Makefile: Remove LSPCON_I2C_SPI dependency on libusb ...................................................................... Makefile: Remove LSPCON_I2C_SPI dependency on libusb Turns out the LSPCON don't actually need libusb support. BUG=b/155133607 BRANCH=none TEST=build and tested read/write/erase Change-Id: I266b1a5fd9a0136495320509c7306fde18e64612 Signed-off-by: Shiyu Sun <sshiyu(a)chromium.org> --- M Makefile 1 file changed, 0 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/21/41021/1 diff --git a/Makefile b/Makefile index 31e987c..803529f 100644 --- a/Makefile +++ b/Makefile @@ -955,7 +955,6 @@ ifeq ($(CONFIG_LSPCON_I2C_SPI), yes) FEATURE_CFLAGS += -D'CONFIG_LSPCON_I2C_SPI=1' PROGRAMMER_OBJS += lspcon_i2c_spi.o -NEED_LIBUSB1 += CONFIG_LSPCON_I2C_SPI endif ifeq ($(CONFIG_REALTEK_MST_I2C_SPI), yes) -- To view, visit https://review.coreboot.org/c/flashrom/+/41021 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I266b1a5fd9a0136495320509c7306fde18e64612 Gerrit-Change-Number: 41021 Gerrit-PatchSet: 1 Gerrit-Owner: Shiyu Sun <sshiyu(a)google.com> Gerrit-MessageType: newchange

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Change in flashrom[master]: ft2232_spi.c: Pack WREN and op in one ftdi_write_data() call to save ...
by Simon Buhrow (Code Review) May 4, 2020

May 4, 2020

Simon Buhrow has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/40477 ) Change subject: ft2232_spi.c: Pack WREN and op in one ftdi_write_data() call to save programming time ...................................................................... Patch Set 8: Is that good practice to add reviewers by myself? -- To view, visit https://review.coreboot.org/c/flashrom/+/40477 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Ie4a07499ec5ef0af23818593f45dc427285a9e8a Gerrit-Change-Number: 40477 Gerrit-PatchSet: 8 Gerrit-Owner: Simon Buhrow Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Georgi <pgeorgi(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Mon, 04 May 2020 07:10:31 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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