September 2019 - flashrom-gerrit

Change in flashrom[master]: flashchips: Add N25Q00A devices
by Jacob Creedon (Code Review) 14 Oct '19

14 Oct '19

Jacob Creedon has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/34521 ) Change subject: flashchips: Add N25Q00A devices ...................................................................... flashchips: Add N25Q00A devices This adds the 1Gb N25Q00A device in both the 1.8v and 3v variants. This is implemented from the datasheet and is marked as untested. Signed-off-by: Jacob Creedon <jcreedon(a)google.com> Change-Id: If36880f37746c95a97c8122a8f2fd0aecede5e8e --- M flashchips.c 1 file changed, 80 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/21/34521/1 diff --git a/flashchips.c b/flashchips.c index 021ae6c..5d292f1 100644 --- a/flashchips.c +++ b/flashchips.c @@ -10304,6 +10304,86 @@ { .vendor = "Micron/Numonyx/ST", + .name = "N25Q00A..1G", /* ..1G = 1.8V, uniform 64KB/4KB blocks/sectors */ + .bustype = BUS_SPI, + .manufacture_id = ST_ID, + .model_id = ST_N25Q00A__1G, + .total_size = 131072, + .page_size = 256, + /* supports SFDP */ + /* OTP: 64B total; read 0x4B, write 0x42 */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_4BA_WREN, + .tested = TEST_UNTESTED, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 32768} }, + .block_erase = spi_block_erase_21, + }, { + .eraseblocks = { {4 * 1024, 32768} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {64 * 1024, 2048} }, + .block_erase = spi_block_erase_dc, + }, { + .eraseblocks = { {64 * 1024, 2048} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {32768 * 1024, 4} }, + .block_erase = spi_block_erase_c4, + } + }, + .printlock = spi_prettyprint_status_register_n25q, /* TODO: config, lock, flag regs */ + .unlock = spi_disable_blockprotect_n25q, /* TODO: per 64kB sector lock registers */ + .write = spi_chip_write_256, /* Multi I/O supported */ + .read = spi_chip_read, /* Fast read (0x0B) and multi I/O supported */ + .voltage = {1700, 2000}, + }, + + { + .vendor = "Micron/Numonyx/ST", + .name = "N25Q00A..3G", /* ..3G = 3V, uniform 64KB/4KB blocks/sectors */ + .bustype = BUS_SPI, + .manufacture_id = ST_ID, + .model_id = ST_N25Q00A__3G, + .total_size = 131072, + .page_size = 256, + /* supports SFDP */ + /* OTP: 64B total; read 0x4B, write 0x42 */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_4BA_WREN, + .tested = TEST_UNTESTED, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 32768} }, + .block_erase = spi_block_erase_21, + }, { + .eraseblocks = { {4 * 1024, 32768} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {64 * 1024, 2048} }, + .block_erase = spi_block_erase_dc, + }, { + .eraseblocks = { {64 * 1024, 2048} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {32768 * 1024, 4} }, + .block_erase = spi_block_erase_c4, + } + }, + .printlock = spi_prettyprint_status_register_n25q, /* TODO: config, lock, flag regs */ + .unlock = spi_disable_blockprotect_n25q, /* TODO: per 64kB sector lock registers */ + .write = spi_chip_write_256, /* Multi I/O supported */ + .read = spi_chip_read, /* Fast read (0x0B) and multi I/O supported */ + .voltage = {2700, 3600}, + }, + + { + .vendor = "Micron/Numonyx/ST", .name = "N25Q016", .bustype = BUS_SPI, .manufacture_id = ST_ID, -- To view, visit https://review.coreboot.org/c/flashrom/+/34521 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: If36880f37746c95a97c8122a8f2fd0aecede5e8e Gerrit-Change-Number: 34521 Gerrit-PatchSet: 1 Gerrit-Owner: Jacob Creedon <jcreedon(a)google.com> Gerrit-MessageType: newchange

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Change in flashrom[master]: flashchips: Fix part names for N25Q512 and N25Q00A
by Jacob Creedon (Code Review) 14 Oct '19

14 Oct '19

Jacob Creedon has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/34520 ) Change subject: flashchips: Fix part names for N25Q512 and N25Q00A ...................................................................... flashchips: Fix part names for N25Q512 and N25Q00A For the N25Q512 and N25Q00A, the 1G and 3G are used instead of 1E and 3E to represent 1.8v and 3v respectively. Signed-off-by: Jacob Creedon <jcreedon(a)google.com> Change-Id: I289c33f7293f47b9449907350654cd6183c778d4 --- M flashchips.c M flashchips.h 2 files changed, 12 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/20/34520/1 diff --git a/flashchips.c b/flashchips.c index 3a0da8d..021ae6c 100644 --- a/flashchips.c +++ b/flashchips.c @@ -10625,10 +10625,10 @@ { .vendor = "Micron/Numonyx/ST", - .name = "N25Q512..1E", /* ..1E = 1.8V, uniform 64KB/4KB blocks/sectors */ + .name = "N25Q512..1G", /* ..1G = 1.8V, uniform 64KB/4KB blocks/sectors */ .bustype = BUS_SPI, .manufacture_id = ST_ID, - .model_id = ST_N25Q512__1E, + .model_id = ST_N25Q512__1G, .total_size = 65536, .page_size = 256, /* supports SFDP */ @@ -10665,10 +10665,10 @@ { .vendor = "Micron/Numonyx/ST", - .name = "N25Q512..3E", /* ..3E = 3V, uniform 64KB/4KB blocks/sectors */ + .name = "N25Q512..3G", /* ..3G = 3V, uniform 64KB/4KB blocks/sectors */ .bustype = BUS_SPI, .manufacture_id = ST_ID, - .model_id = ST_N25Q512__3E, + .model_id = ST_N25Q512__3G, .total_size = 65536, .page_size = 256, /* supports SFDP */ @@ -10708,7 +10708,7 @@ .name = "MT25QL01G", /* L = 3V, uniform 64KB/4KB blocks/sectors */ .bustype = BUS_SPI, .manufacture_id = ST_ID, - .model_id = ST_N25Q00A__3E, + .model_id = ST_N25Q00A__3G, .total_size = 131072, .page_size = 256, /* supports SFDP */ @@ -10754,7 +10754,7 @@ .name = "MT25QU01G", /* U = 1.8V, uniform 64KB/4KB blocks/sectors */ .bustype = BUS_SPI, .manufacture_id = ST_ID, - .model_id = ST_N25Q00A__1E, + .model_id = ST_N25Q00A__1G, .total_size = 131072, .page_size = 256, /* supports SFDP */ @@ -11070,7 +11070,7 @@ .name = "MT25QL512", /* L = 3V, uniform 64KB/4KB blocks/sectors */ .bustype = BUS_SPI, .manufacture_id = ST_ID, - .model_id = ST_N25Q512__3E, + .model_id = ST_N25Q512__3G, .total_size = 65536, .page_size = 256, /* supports SFDP */ @@ -11119,7 +11119,7 @@ .name = "MT25QU512", /* U = 1.8V, uniform 64KB/4KB blocks/sectors */ .bustype = BUS_SPI, .manufacture_id = ST_ID, - .model_id = ST_N25Q512__1E, + .model_id = ST_N25Q512__1G, .total_size = 65536, .page_size = 256, /* supports SFDP */ diff --git a/flashchips.h b/flashchips.h index e53e0df..0dcf735 100644 --- a/flashchips.h +++ b/flashchips.h @@ -866,10 +866,10 @@ #define ST_N25Q128__1E 0xBB18 /* N25Q128/MT25QU128, 1.8V, (uniform sectors expected) */ #define ST_N25Q256__3E 0xBA19 /* N25Q256/MT25QL256, 3.0V, (uniform sectors expected) */ #define ST_N25Q256__1E 0xBB19 /* N25Q256/MT25QU256, 1.8V, (uniform sectors expected) */ -#define ST_N25Q512__3E 0xBA20 /* N25Q512/MT25QL512, 3.0V, (uniform sectors expected) */ -#define ST_N25Q512__1E 0xBB20 /* N25Q512/MT25QU512, 1.8V, (uniform sectors expected) */ -#define ST_N25Q00A__3E 0xBA21 /* N25Q00A/MT25QL01G, 3.0V, (uniform sectors expected) */ -#define ST_N25Q00A__1E 0xBB21 /* N25Q00A/MT25QU01G, 1.8V, (uniform sectors expected) */ +#define ST_N25Q512__3G 0xBA20 /* N25Q512/MT25QL512, 3.0V, (uniform sectors expected) */ +#define ST_N25Q512__1G 0xBB20 /* N25Q512/MT25QU512, 1.8V, (uniform sectors expected) */ +#define ST_N25Q00A__3G 0xBA21 /* N25Q00A/MT25QL01G, 3.0V, (uniform sectors expected) */ +#define ST_N25Q00A__1G 0xBB21 /* N25Q00A/MT25QU01G, 1.8V, (uniform sectors expected) */ #define ST_MT25QL02G 0xBA22 /* MT25QL02G, 3.0V, (uniform sectors expected) */ #define ST_MT25QU02G 0xBB22 /* MT25QU02G, 1.8V, (uniform sectors expected) */ #define ST_NP5Q032 0xDA16 /* Phase-change memory (PCM), 3V */ -- To view, visit https://review.coreboot.org/c/flashrom/+/34520 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I289c33f7293f47b9449907350654cd6183c778d4 Gerrit-Change-Number: 34520 Gerrit-PatchSet: 1 Gerrit-Owner: Jacob Creedon <jcreedon(a)google.com> Gerrit-MessageType: newchange

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Change in flashrom[master]: flashchips: Add missing MT25Q capacities
by Jacob Creedon (Code Review) 14 Oct '19

14 Oct '19

Jacob Creedon has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/34492 ) Change subject: flashchips: Add missing MT25Q capacities ...................................................................... flashchips: Add missing MT25Q capacities This adds the 128Mb, 1Gb, and 2Gb capacities of the MT25Q devices. All of these are implemented via the datasheet and should work but are untested in hardware. Signed-off-by: Jacob Creedon <jcreedon(a)google.com> Change-Id: Ice6ea9426361afc25d4b731e2e3079edf234fdda --- M flashchips.c M flashchips.h 2 files changed, 274 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/92/34492/1 diff --git a/flashchips.c b/flashchips.c index 5424a04..6b553fb 100644 --- a/flashchips.c +++ b/flashchips.c @@ -10705,6 +10705,270 @@ { .vendor = "Micron", + .name = "MT25QL01G", /* L = 3V, uniform 64KB/4KB blocks/sectors */ + .bustype = BUS_SPI, + .manufacture_id = ST_ID, + .model_id = ST_N25Q00A__3E, + .total_size = 131072, + .page_size = 256, + /* supports SFDP */ + /* OTP: 64B total; read 0x4B, write 0x42 */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_4BA_WREN, + .tested = TEST_UNTESTED, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 32768} }, + .block_erase = spi_block_erase_21, + }, { + .eraseblocks = { {4 * 1024, 32768} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {32 * 1024, 4096} }, + .block_erase = spi_block_erase_5c, + }, { + .eraseblocks = { {32 * 1024, 4096} }, + .block_erase = spi_block_erase_52, + }, { + .eraseblocks = { {64 * 1024, 2048} }, + .block_erase = spi_block_erase_dc, + }, { + .eraseblocks = { {64 * 1024, 2048} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {131072 * 1024, 1} }, + .block_erase = spi_block_erase_c4, + } + }, + .printlock = spi_prettyprint_status_register_n25q, /* TODO: config, lock, flag regs */ + .unlock = spi_disable_blockprotect_n25q, /* TODO: per 64kB sector lock registers */ + .write = spi_chip_write_256, /* Multi I/O supported */ + .read = spi_chip_read, /* Fast read (0x0B) and multi I/O supported */ + .voltage = {2700, 3600}, + }, + + { + .vendor = "Micron", + .name = "MT25QU01G", /* U = 1.8V, uniform 64KB/4KB blocks/sectors */ + .bustype = BUS_SPI, + .manufacture_id = ST_ID, + .model_id = ST_N25Q00A__1E, + .total_size = 131072, + .page_size = 256, + /* supports SFDP */ + /* OTP: 64B total; read 0x4B, write 0x42 */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_4BA_WREN, + .tested = TEST_UNTESTED, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 32768} }, + .block_erase = spi_block_erase_21, + }, { + .eraseblocks = { {4 * 1024, 32768} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {32 * 1024, 4096} }, + .block_erase = spi_block_erase_5c, + }, { + .eraseblocks = { {32 * 1024, 4096} }, + .block_erase = spi_block_erase_52, + }, { + .eraseblocks = { {64 * 1024, 2048} }, + .block_erase = spi_block_erase_dc, + }, { + .eraseblocks = { {64 * 1024, 2048} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {131072 * 1024, 1} }, + .block_erase = spi_block_erase_c4, + } + }, + .printlock = spi_prettyprint_status_register_n25q, /* TODO: config, lock, flag regs */ + .unlock = spi_disable_blockprotect_n25q, /* TODO: per 64kB sector lock registers */ + .write = spi_chip_write_256, /* Multi I/O supported */ + .read = spi_chip_read, /* Fast read (0x0B) and multi I/O supported */ + .voltage = {1700, 2000}, + }, + + { + .vendor = "Micron", + .name = "MT25QL02G", /* L = 3V, uniform 64KB/4KB blocks/sectors */ + .bustype = BUS_SPI, + .manufacture_id = ST_ID, + .model_id = ST_MT25QL02G, + .total_size = 262144, + .page_size = 256, + /* supports SFDP */ + /* OTP: 64B total; read 0x4B, write 0x42 */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_4BA_WREN, + .tested = TEST_UNTESTED, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 65536} }, + .block_erase = spi_block_erase_21, + }, { + .eraseblocks = { {4 * 1024, 65536} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {32 * 1024, 8192} }, + .block_erase = spi_block_erase_5c, + }, { + .eraseblocks = { {32 * 1024, 8192} }, + .block_erase = spi_block_erase_52, + }, { + .eraseblocks = { {64 * 1024, 4096} }, + .block_erase = spi_block_erase_dc, + }, { + .eraseblocks = { {64 * 1024, 4096} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {262144 * 1024, 1} }, + .block_erase = spi_block_erase_c4, + } + }, + .printlock = spi_prettyprint_status_register_n25q, /* TODO: config, lock, flag regs */ + .unlock = spi_disable_blockprotect_n25q, /* TODO: per 64kB sector lock registers */ + .write = spi_chip_write_256, /* Multi I/O supported */ + .read = spi_chip_read, /* Fast read (0x0B) and multi I/O supported */ + .voltage = {2700, 3600}, + }, + + { + .vendor = "Micron", + .name = "ST_MT25QU02G", /* U = 1.8V, uniform 64KB/4KB blocks/sectors */ + .bustype = BUS_SPI, + .manufacture_id = ST_ID, + .model_id = ST_N25Q00A__1E, + .total_size = 262144, + .page_size = 256, + /* supports SFDP */ + /* OTP: 64B total; read 0x4B, write 0x42 */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_4BA_WREN, + .tested = TEST_UNTESTED, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 65536} }, + .block_erase = spi_block_erase_21, + }, { + .eraseblocks = { {4 * 1024, 65536} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {32 * 1024, 8192} }, + .block_erase = spi_block_erase_5c, + }, { + .eraseblocks = { {32 * 1024, 8192} }, + .block_erase = spi_block_erase_52, + }, { + .eraseblocks = { {64 * 1024, 4096} }, + .block_erase = spi_block_erase_dc, + }, { + .eraseblocks = { {64 * 1024, 4096} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {262144 * 1024, 1} }, + .block_erase = spi_block_erase_c4, + } + }, + .printlock = spi_prettyprint_status_register_n25q, /* TODO: config, lock, flag regs */ + .unlock = spi_disable_blockprotect_n25q, /* TODO: per 64kB sector lock registers */ + .write = spi_chip_write_256, /* Multi I/O supported */ + .read = spi_chip_read, /* Fast read (0x0B) and multi I/O supported */ + .voltage = {1700, 2000}, + }, + + { + .vendor = "Micron", + .name = "MT25QU128", /* U = 1.8V, uniform 64KB/4KB blocks/sectors */ + .bustype = BUS_SPI, + .manufacture_id = ST_ID, + .model_id = ST_N25Q128__1E, + .total_size = 16384, + .page_size = 256, + /* supports SFDP */ + /* OTP: 64B total; read 0x4B, write 0x42 */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_4BA_WREN, + .tested = TEST_UNTESTED, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 4096} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {32 * 1024, 512} }, + .block_erase = spi_block_erase_52, + }, { + .eraseblocks = { {64 * 1024, 256} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {16384 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + }, { + .eraseblocks = { {16384 * 1024, 1} }, + .block_erase = spi_block_erase_60, + } + }, + .printlock = spi_prettyprint_status_register_n25q, /* TODO: config, lock, flag regs */ + .unlock = spi_disable_blockprotect_n25q, /* TODO: per 64kB sector lock registers */ + .write = spi_chip_write_256, /* Multi I/O supported */ + .read = spi_chip_read, /* Fast read (0x0B) and multi I/O supported */ + .voltage = {1700, 2000}, + }, + + { + .vendor = "Micron", + .name = "MT25QL128", /* L = 3V, uniform 64KB/4KB blocks/sectors */ + .bustype = BUS_SPI, + .manufacture_id = ST_ID, + .model_id = ST_N25Q128__3E, + .total_size = 16384, + .page_size = 256, + /* supports SFDP */ + /* OTP: 64B total; read 0x4B, write 0x42 */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_4BA_WREN, + .tested = TEST_UNTESTED, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 4096} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {32 * 1024, 512} }, + .block_erase = spi_block_erase_52, + }, { + .eraseblocks = { {64 * 1024, 256} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {16384 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + }, { + .eraseblocks = { {16384 * 1024, 1} }, + .block_erase = spi_block_erase_60, + } + }, + .printlock = spi_prettyprint_status_register_n25q, /* TODO: config, lock, flag regs */ + .unlock = spi_disable_blockprotect_n25q, /* TODO: per 64kB sector lock registers */ + .write = spi_chip_write_256, /* Multi I/O supported */ + .read = spi_chip_read, /* Fast read (0x0B) and multi I/O supported */ + .voltage = {2700, 3600}, + }, + + { + .vendor = "Micron", .name = "MT25QL256", /* L = 3V, uniform 64KB/4KB blocks/sectors */ .bustype = BUS_SPI, .manufacture_id = ST_ID, diff --git a/flashchips.h b/flashchips.h index 006b95e..e53e0df 100644 --- a/flashchips.h +++ b/flashchips.h @@ -862,13 +862,16 @@ #define ST_N25Q032__1E 0xBB16 /* N25Q032, 1.8V, (uniform sectors expected) */ #define ST_N25Q064__3E 0xBA17 /* N25Q064, 3.0V, (uniform sectors expected) */ #define ST_N25Q064__1E 0xBB17 /* N25Q064, 1.8V, (uniform sectors expected) */ -#define ST_N25Q128__3E 0xBA18 /* N25Q128, 3.0V, (uniform sectors expected) */ -#define ST_N25Q128__1E 0xBB18 /* N25Q128, 1.8V, (uniform sectors expected) */ -#define ST_N25Q256__3E 0xBA19 /* N25Q256, 3.0V, (uniform sectors expected) */ -#define ST_N25Q256__1E 0xBB19 /* N25Q256, 1.8V, (uniform sectors expected) */ -#define ST_N25Q512__3E 0xBA20 /* N25Q512, 3.0V, (uniform sectors expected) */ -#define ST_N25Q512__1E 0xBB20 /* N25Q512, 1.8V, (uniform sectors expected) */ -#define ST_N25Q00A__3E 0xBA21 /* N25Q00A, 3.0V, (uniform sectors expected) */ +#define ST_N25Q128__3E 0xBA18 /* N25Q128/MT25QL128, 3.0V, (uniform sectors expected) */ +#define ST_N25Q128__1E 0xBB18 /* N25Q128/MT25QU128, 1.8V, (uniform sectors expected) */ +#define ST_N25Q256__3E 0xBA19 /* N25Q256/MT25QL256, 3.0V, (uniform sectors expected) */ +#define ST_N25Q256__1E 0xBB19 /* N25Q256/MT25QU256, 1.8V, (uniform sectors expected) */ +#define ST_N25Q512__3E 0xBA20 /* N25Q512/MT25QL512, 3.0V, (uniform sectors expected) */ +#define ST_N25Q512__1E 0xBB20 /* N25Q512/MT25QU512, 1.8V, (uniform sectors expected) */ +#define ST_N25Q00A__3E 0xBA21 /* N25Q00A/MT25QL01G, 3.0V, (uniform sectors expected) */ +#define ST_N25Q00A__1E 0xBB21 /* N25Q00A/MT25QU01G, 1.8V, (uniform sectors expected) */ +#define ST_MT25QL02G 0xBA22 /* MT25QL02G, 3.0V, (uniform sectors expected) */ +#define ST_MT25QU02G 0xBB22 /* MT25QU02G, 1.8V, (uniform sectors expected) */ #define ST_NP5Q032 0xDA16 /* Phase-change memory (PCM), 3V */ #define ST_NP5Q064 0xDA17 /* Phase-change memory (PCM), 3V */ #define ST_NP5Q128 0xDA18 /* Phase-change memory (PCM), 3V */ -- To view, visit https://review.coreboot.org/c/flashrom/+/34492 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Ice6ea9426361afc25d4b731e2e3079edf234fdda Gerrit-Change-Number: 34492 Gerrit-PatchSet: 1 Gerrit-Owner: Jacob Creedon <jcreedon(a)google.com> Gerrit-MessageType: newchange

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Change in flashrom[master]: util/git-hooks: Check for Signed-off-by line
by David Hendricks (Code Review) 14 Oct '19

14 Oct '19

David Hendricks has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/35295 ) Change subject: util/git-hooks: Check for Signed-off-by line ...................................................................... util/git-hooks: Check for Signed-off-by line Enforce the DCO. The logic comes from coreboot's commit-msg hook, and I've added a pointer to flashrom's development guidelines. Change-Id: Iea49a06c2d4824be073eff98c8aae1cbc5b145e4 Signed-off-by: David Hendricks <david.hendricks(a)gmail.com> --- M util/git-hooks/commit-msg 1 file changed, 11 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/95/35295/1 diff --git a/util/git-hooks/commit-msg b/util/git-hooks/commit-msg index 346c08f..fff0e29 100755 --- a/util/git-hooks/commit-msg +++ b/util/git-hooks/commit-msg @@ -28,6 +28,8 @@ CHANGE_ID_AFTER="Bug|Depends-On|Issue|Test|Feature|Fixes|Fixed|Staging-ID" MSG="$1" +DEV_GUIDELINES_URL="https://www.flashrom.org/Development_Guidelines" + # Check for, and add if missing, a unique Change-Id # add_ChangeId() { @@ -201,8 +203,17 @@ } } +test_sign_off() { + if ! grep -qi '^[[:space:]]*\+Signed-off-by:' "$MSG"; then + printf "\nError: No Signed-off-by line in the commit message.\n" + printf "See: ${DEV_GUIDELINES_URL}\n" + exit 1 + fi +} + main() { test_duplicate_signoffs_acks + test_sign_off add_ChangeId } -- To view, visit https://review.coreboot.org/c/flashrom/+/35295 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Iea49a06c2d4824be073eff98c8aae1cbc5b145e4 Gerrit-Change-Number: 35295 Gerrit-PatchSet: 1 Gerrit-Owner: David Hendricks <david.hendricks(a)gmail.com> Gerrit-MessageType: newchange

2 5

Change in flashrom[master]: meson: Correct license to GPL-2.0
by Nico Huber (Code Review) 06 Oct '19

06 Oct '19

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/35584 ) Change subject: meson: Correct license to GPL-2.0 ...................................................................... meson: Correct license to GPL-2.0 Parts of flashrom are 2.0+ but some are not. As Meson's purpose is to link these together, it should advertise only GPL-2.0 for the whole. Change-Id: Iab99c74f5f9d54dac56085ecc7475b14be00a310 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M meson.build 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/84/35584/1 diff --git a/meson.build b/meson.build index b475f64..4be68e2 100644 --- a/meson.build +++ b/meson.build @@ -1,6 +1,6 @@ project('flashromutils', 'c', version : run_command('util/getversion.sh', '-v').stdout().strip(), - license : 'GPL-2.0+', + license : 'GPL-2.0', meson_version : '>=0.47.0', default_options : ['warning_level=2', 'c_std=c99'], ) -- To view, visit https://review.coreboot.org/c/flashrom/+/35584 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Iab99c74f5f9d54dac56085ecc7475b14be00a310 Gerrit-Change-Number: 35584 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newchange

4 5

Change in flashrom[master]: cli_classic: Add convenient '--flash-name' cli opt
by Edward O'Callaghan (Code Review) 04 Oct '19

04 Oct '19

Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/35591 ) Change subject: cli_classic: Add convenient '--flash-name' cli opt ...................................................................... cli_classic: Add convenient '--flash-name' cli opt We have this in the ChromiumOS fork of flashrom which we rely on to obtain the current flash chip in use. This ports it for upstream consumption. Change-Id: I23d574a2f8eaf809a5c0524490db9e3a560ede56 Signed-off-by: Edward O'Callaghan <quasisec(a)chromium.org> --- M cli_classic.c 1 file changed, 19 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/91/35591/1 diff --git a/cli_classic.c b/cli_classic.c index b4112fd..4604043 100644 --- a/cli_classic.c +++ b/cli_classic.c @@ -101,6 +101,7 @@ #if CONFIG_PRINT_WIKI == 1 int list_supported_wiki = 0; #endif + int flash_name = 0; int read_it = 0, write_it = 0, erase_it = 0, verify_it = 0; int dont_verify_it = 0, dont_verify_all = 0, list_supported = 0, operation_specified = 0; struct flashrom_layout *layout = NULL; @@ -110,6 +111,7 @@ OPTION_FMAP, OPTION_FMAP_FILE, OPTION_FLASH_CONTENTS, + OPTION_FLASH_NAME, }; int ret = 0; @@ -130,6 +132,7 @@ {"fmap-file", 1, NULL, OPTION_FMAP_FILE}, {"image", 1, NULL, 'i'}, {"flash-contents", 1, NULL, OPTION_FLASH_CONTENTS}, + {"flash-name", 0, NULL, OPTION_FLASH_NAME}, {"list-supported", 0, NULL, 'L'}, {"list-supported-wiki", 0, NULL, 'z'}, {"programmer", 1, NULL, 'p'}, @@ -296,6 +299,9 @@ case OPTION_FLASH_CONTENTS: referencefile = strdup(optarg); break; + case OPTION_FLASH_NAME: + flash_name = 1; + break; case 'L': if (++operation_specified > 1) { fprintf(stderr, "More than one operation " @@ -602,11 +608,23 @@ goto out_shutdown; } - if (!(read_it | write_it | verify_it | erase_it)) { + if (!(read_it | write_it | verify_it | erase_it | flash_name)) { msg_ginfo("No operations were specified.\n"); goto out_shutdown; } + if (flash_name) { + if (fill_flash->chip->vendor && fill_flash->chip->name) { + msg_ginfo("vendor\"%s\" name=\"%s\"\n", + fill_flash->chip->vendor, + fill_flash->chip->name); + goto out_shutdown; + } else { + ret = -1; + goto out_shutdown; + } + } + if (layoutfile) { layout = get_global_layout(); } else if (ifd && (flashrom_layout_read_from_ifd(&layout, fill_flash, NULL, 0) || -- To view, visit https://review.coreboot.org/c/flashrom/+/35591 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I23d574a2f8eaf809a5c0524490db9e3a560ede56 Gerrit-Change-Number: 35591 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: newchange

8 25

Change in flashrom[master]: Add support for M95M02-A125
by Konstantin Grudnev (Code Review) 04 Oct '19

04 Oct '19

Konstantin Grudnev has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/34496 ) Change subject: Add support for M95M02-A125 ...................................................................... Add support for M95M02-A125 Automotive 2 Mbit (256KiB) serial SPI bus EEPROM PREW tested successfully with use of ch341a programmer on Linux host 5.2.0-1-MANJARO x86_64 Signed-off-by: Konstantin Grudnev <grudnevkv(a)gmail.com> Change-Id: Ic29cd9051c7eac4822d620c299834134f987f01b --- M chipdrivers.h M flashchips.c M flashchips.h M spi.h M spi25.c 5 files changed, 102 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/96/34496/1 diff --git a/chipdrivers.h b/chipdrivers.h index e380878..0b4435c 100644 --- a/chipdrivers.h +++ b/chipdrivers.h @@ -34,6 +34,7 @@ int probe_spi_res1(struct flashctx *flash); int probe_spi_res2(struct flashctx *flash); int probe_spi_res3(struct flashctx *flash); +int probe_spi_st95(struct flashctx *flash); int probe_spi_at25f(struct flashctx *flash); int spi_write_enable(struct flashctx *flash); int spi_write_disable(struct flashctx *flash); @@ -51,6 +52,7 @@ int spi_block_erase_d8(struct flashctx *flash, unsigned int addr, unsigned int blocklen); int spi_block_erase_db(struct flashctx *flash, unsigned int addr, unsigned int blocklen); int spi_block_erase_dc(struct flashctx *flash, unsigned int addr, unsigned int blocklen); +int spi_block_erase_emulation(struct flashctx *flash, unsigned int addr, unsigned int blocklen); erasefunc_t *spi_get_erasefn_from_opcode(uint8_t opcode); int spi_chip_write_1(struct flashctx *flash, const uint8_t *buf, unsigned int start, unsigned int len); int spi_nbyte_read(struct flashctx *flash, unsigned int addr, uint8_t *bytes, unsigned int len); diff --git a/flashchips.c b/flashchips.c index 166af6a..44875c6 100644 --- a/flashchips.c +++ b/flashchips.c @@ -14104,6 +14104,33 @@ }, { + .vendor = "ST", + .name = "M95M02", + .bustype = BUS_SPI, + .manufacture_id = ST_ID, + .model_id = ST_M95M02, + .total_size = 256, + .page_size = 256, + .feature_bits = FEATURE_WRSR_WREN, + .tested = TEST_OK_PREW, + .probe = probe_spi_st95, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { { 256 * 1024, 1 } }, + .block_erase = spi_block_erase_emulation, + } + }, + + .printlock = spi_prettyprint_status_register_bp1_srwd, + .unlock = spi_disable_blockprotect_bp1_srwd, + .write = spi_chip_write_256, + .read = spi_chip_read, + .voltage = {2500, 5500}, + }, + + { .vendor = "Sanyo", .name = "LE25FU106B", .bustype = BUS_SPI, diff --git a/flashchips.h b/flashchips.h index 006b95e..d1eed91 100644 --- a/flashchips.h +++ b/flashchips.h @@ -851,6 +851,12 @@ #define ST_M58WR032KT 0x8814 #define ST_M58WR064KB 0x8811 #define ST_M58WR064KT 0x8810 + +/* 00h ST Manufacturer code ST_ID*/ +/* 01h SPI Family code 0x00*/ +/* 02h Memory Density code ST_M95XXX */ +#define ST_M95M02 0x0012 /* ST M95XXX 2Mbit (256KiB) */ + #define ST_MT28GU01G___1 0x88B0 #define ST_MT28GU01G___2 0x88B1 #define ST_MT28GU256___1 0x8901 diff --git a/spi.h b/spi.h index 0073c71..9f199f3 100644 --- a/spi.h +++ b/spi.h @@ -28,6 +28,12 @@ /* INSIZE may be 0x04 for some chips*/ #define JEDEC_RDID_INSIZE 0x03 +/* Some ST M95X model */ +#define ST_M95_RDID 0x83 +#define ST_M95_RDID_OUTSIZE 0x04 /* 8b op, 24bit addr where size >64KiB */ +#define ST_M95_RDID_INSIZE 0x03 + + /* Some Atmel AT25F* models have bit 3 as don't care bit in commands */ #define AT25F_RDID 0x15 /* 0x15 or 0x1d */ #define AT25F_RDID_OUTSIZE 0x01 diff --git a/spi25.c b/spi25.c index 2a1d492..ec35585 100644 --- a/spi25.c +++ b/spi25.c @@ -21,6 +21,7 @@ #include <stddef.h> #include <string.h> #include <stdbool.h> +#include <stdlib.h> #include "flash.h" #include "flashchips.h" #include "chipdrivers.h" @@ -262,6 +263,32 @@ return 1; } +/* Only used for some stm95080 and higher chip. */ +int probe_spi_st95(struct flashctx *flash) +{ + /* ST_M95_RDID_OUTSIZE depends on size of the flash and + * not all ST_M95XXX have RDID + */ + static const unsigned char cmd[ST_M95_RDID_OUTSIZE] = {ST_M95_RDID}; + unsigned char readarr[ST_M95_RDID_INSIZE]; + uint32_t id1, id2; + + spi_send_command(flash, sizeof(cmd), sizeof(readarr), cmd, readarr); + + id1 = readarr[0]; // manufacture id + id2 = readarr[2]; // model id + + msg_ginfo("RDID[%s: id1 0x%02x, id2 0x%02x, " + "L 0x%02x, M 0x%02x, H 0x%02x]\n", + __func__, flash->chip->manufacture_id, flash->chip->model_id, + readarr[0], readarr[1], readarr[2]); + + if (id1 == flash->chip->manufacture_id && id2 == flash->chip->model_id) + return 1; + + return 0; +} + /* Only used for some Atmel chips. */ int probe_spi_at25f(struct flashctx *flash) { @@ -440,6 +467,13 @@ return result ? result : status; } +static int spi_nbyte_program(struct flashctx *flash, unsigned int addr, const uint8_t *bytes, unsigned int len) +{ + const bool native_4ba = flash->chip->feature_bits & FEATURE_4BA_WRITE && spi_master_4ba(flash); + const uint8_t op = native_4ba ? JEDEC_BYTE_PROGRAM_4BA : JEDEC_BYTE_PROGRAM; + return spi_write_cmd(flash, op, native_4ba, addr, bytes, len, 10); +} + static int spi_chip_erase_60(struct flashctx *flash) { /* This usually takes 1-85s, so wait in 1s steps. */ @@ -577,6 +611,33 @@ return spi_write_cmd(flash, 0xdc, true, addr, NULL, 0, 100 * 1000); } +/* some chips don't have erase function */ +int spi_block_erase_emulation(struct flashctx *flash, unsigned int addr, unsigned int blocklen) +{ + unsigned int i; + const unsigned int erase_len = flash->chip->page_size; + uint8_t *erased_contents = NULL; + int result = 0; + + erased_contents = (uint8_t*) malloc(erase_len * sizeof(uint8_t)); + if (!erased_contents) { + msg_cerr("Out of memory!\n"); + return 1; + } + + memset(erased_contents, ERASED_VALUE(flash), erase_len * sizeof(uint8_t)); + msg_cinfo("\n"); + for (i = addr; i < blocklen; i+=erase_len) { + if (spi_nbyte_program(flash, i, erased_contents, erase_len)) { + result = 1; + break; + } + } + + free(erased_contents); + return result; +} + erasefunc_t *spi_get_erasefn_from_opcode(uint8_t opcode) { switch(opcode){ @@ -619,13 +680,6 @@ } } -static int spi_nbyte_program(struct flashctx *flash, unsigned int addr, const uint8_t *bytes, unsigned int len) -{ - const bool native_4ba = flash->chip->feature_bits & FEATURE_4BA_WRITE && spi_master_4ba(flash); - const uint8_t op = native_4ba ? JEDEC_BYTE_PROGRAM_4BA : JEDEC_BYTE_PROGRAM; - return spi_write_cmd(flash, op, native_4ba, addr, bytes, len, 10); -} - int spi_nbyte_read(struct flashctx *flash, unsigned int address, uint8_t *bytes, unsigned int len) { -- To view, visit https://review.coreboot.org/c/flashrom/+/34496 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Ic29cd9051c7eac4822d620c299834134f987f01b Gerrit-Change-Number: 34496 Gerrit-PatchSet: 1 Gerrit-Owner: Konstantin Grudnev <grudnevkv(a)gmail.com> Gerrit-MessageType: newchange

2 13

Change in flashrom[master]: tree: Enable -Wwrite-strings
by Jacob Garber (Code Review) 04 Oct '19

04 Oct '19

Jacob Garber has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/34577 ) Change subject: tree: Enable -Wwrite-strings ...................................................................... tree: Enable -Wwrite-strings When compiling, this warning gives string literals the type const char[] to help catch accidental modification (which is undefined behaviour). There currently aren't any instances of this in flashrom, so let's enable this warning to keep it that way. This requires adding const qualifiers to the declarations of several variables that work with string literals. Change-Id: I62d9bc194938a0c9a0e4cdff7ced8ea2e14cc1bc Signed-off-by: Jacob Garber <jgarber1(a)ualberta.ca> --- M Makefile M buspirate_spi.c M cli_classic.c M dmi.c M pony_spi.c M util/ich_descriptors_tool/ich_descriptors_tool.c 6 files changed, 6 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/77/34577/1 diff --git a/Makefile b/Makefile index 545e84a..1a20933 100644 --- a/Makefile +++ b/Makefile @@ -30,7 +30,7 @@ DIFF = diff PREFIX ?= /usr/local MANDIR ?= $(PREFIX)/share/man -CFLAGS ?= -Os -Wall -Wshadow -Wmissing-prototypes +CFLAGS ?= -Os -Wall -Wshadow -Wmissing-prototypes -Wwrite-strings EXPORTDIR ?= . RANLIB ?= ranlib PKG_CONFIG ?= pkg-config diff --git a/buspirate_spi.c b/buspirate_spi.c index fb066c2..bc6776b 100644 --- a/buspirate_spi.c +++ b/buspirate_spi.c @@ -112,7 +112,7 @@ return 0; } -static int buspirate_wait_for_string(unsigned char *buf, char *key) +static int buspirate_wait_for_string(unsigned char *buf, const char *key) { unsigned int keylen = strlen(key); int ret; diff --git a/cli_classic.c b/cli_classic.c index 0591bfe..428efc1 100644 --- a/cli_classic.c +++ b/cli_classic.c @@ -77,7 +77,7 @@ exit(1); } -static int check_filename(char *filename, char *type) +static int check_filename(char *filename, const char *type) { if (!filename || (filename[0] == '\0')) { fprintf(stderr, "Error: No %s file specified.\n", type); diff --git a/dmi.c b/dmi.c index ae90f7c..6132b47 100644 --- a/dmi.c +++ b/dmi.c @@ -69,7 +69,7 @@ static const struct { uint8_t type; uint8_t is_laptop; - char *name; + const char *name; } dmi_chassis_types[] = { {0x01, 2, "Other"}, {0x02, 2, "Unknown"}, diff --git a/pony_spi.c b/pony_spi.c index 6c03308..ed9d326 100644 --- a/pony_spi.c +++ b/pony_spi.c @@ -115,7 +115,7 @@ int i, data_out; char *arg = NULL; enum pony_type type = TYPE_SI_PROG; - char *name; + const char *name; int have_device = 0; int have_prog = 0; diff --git a/util/ich_descriptors_tool/ich_descriptors_tool.c b/util/ich_descriptors_tool/ich_descriptors_tool.c index 2c7966d..768401e 100644 --- a/util/ich_descriptors_tool/ich_descriptors_tool.c +++ b/util/ich_descriptors_tool/ich_descriptors_tool.c @@ -111,7 +111,7 @@ printf("\n"); } -static void usage(char *argv[], char *error) +static void usage(char *argv[], const char *error) { if (error != NULL) { fprintf(stderr, "%s\n", error); -- To view, visit https://review.coreboot.org/c/flashrom/+/34577 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I62d9bc194938a0c9a0e4cdff7ced8ea2e14cc1bc Gerrit-Change-Number: 34577 Gerrit-PatchSet: 1 Gerrit-Owner: Jacob Garber <jgarber1(a)ualberta.ca> Gerrit-MessageType: newchange

6 8

Change in flashrom[master]: flashchips.c: Add GD25Q256D from downstream
by Alan Green (Code Review) 04 Oct '19

04 Oct '19

Alan Green has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/35480 ) Change subject: flashchips.c: Add GD25Q256D from downstream ...................................................................... flashchips.c: Add GD25Q256D from downstream Take definition of GD25Q256D from ChromiumOS repository. This chip was added in `commit 0c38355c` by dlaurie(a)google.com 2019-03-17. Signed-off-by: Alan Green <avg(a)google.com> Change-Id: I79d4ed48aa9126a8a6ce455a9564451346195b8f --- M flashchips.c M flashchips.h 2 files changed, 38 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/80/35480/1 diff --git a/flashchips.c b/flashchips.c index ac07fa8..1d9d9e7 100644 --- a/flashchips.c +++ b/flashchips.c @@ -6274,6 +6274,43 @@ { .vendor = "GigaDevice", + .name = "GD25Q256D", + .bustype = BUS_SPI, + .manufacture_id = GIGADEVICE_ID, + .model_id = GIGADEVICE_GD25Q256D, + .total_size = 32768, + .page_size = 256, + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_4BA_WREN, + .tested = TEST_OK_PREW, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 8192} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {32 * 1024, 1024} }, + .block_erase = spi_block_erase_52, + }, { + .eraseblocks = { {64 * 1024, 512} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {32 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {32 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, + .unlock = spi_disable_blockprotect, + .write = spi_chip_write_256, + .read = spi_chip_read, + .voltage = {2700, 3600}, + }, + + { + .vendor = "GigaDevice", .name = "GD25Q32(B)", .bustype = BUS_SPI, .manufacture_id = GIGADEVICE_ID, diff --git a/flashchips.h b/flashchips.h index 7b8bf04..c4b863d 100644 --- a/flashchips.h +++ b/flashchips.h @@ -372,6 +372,7 @@ #define GIGADEVICE_GD25Q32 0x4016 /* Same as GD25Q32B */ #define GIGADEVICE_GD25Q64 0x4017 /* Same as GD25Q64B */ #define GIGADEVICE_GD25Q128 0x4018 /* GD25Q128B and GD25Q128C only, can be distinguished by SFDP */ +#define GIGADEVICE_GD25Q256D 0x4019 #define GIGADEVICE_GD25VQ21B 0x4212 #define GIGADEVICE_GD25VQ41B 0x4213 /* Same as GD25VQ40C, can be distinguished by SFDP */ #define GIGADEVICE_GD25VQ80C 0x4214 -- To view, visit https://review.coreboot.org/c/flashrom/+/35480 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I79d4ed48aa9126a8a6ce455a9564451346195b8f Gerrit-Change-Number: 35480 Gerrit-PatchSet: 1 Gerrit-Owner: Alan Green <avg(a)google.com> Gerrit-MessageType: newchange

3 10

Change in flashrom[master]: Add board enable for Asus P4P800SE
by Miklós Márton (Code Review) 04 Oct '19

04 Oct '19

Miklós Márton has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/34764 ) Change subject: Add board enable for Asus P4P800SE ...................................................................... Add board enable for Asus P4P800SE See github issue #32: https://github.com/flashrom/flashrom/issues/32 Change-Id: I12b25ca3f85e5f2302681bddbe1adafa49c5fcb9 Signed-off-by: Miklós Márton <martonmiklosqdev(a)gmail.com> --- M board_enable.c M print.c 2 files changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/64/34764/1 diff --git a/board_enable.c b/board_enable.c index 74612f5..5872a9a 100644 --- a/board_enable.c +++ b/board_enable.c @@ -1708,6 +1708,7 @@ * - ASUS P4P800-E Deluxe: Intel socket478 + 865PE + ICH5R * - ASUS P4P800-VM: Intel socket478 + 865PE + ICH5R * - ASUS P4P800-X: Intel socket478 + 865PE + ICH5R + * - ASUS P4P800SE: Intel socket478 + 865PE + ICH5R * - ASUS P5GD1 Pro: Intel LGA 775 + 915P + ICH6R * - ASUS P5GD2 Premium: Intel LGA775 + 915G + ICH6R * - ASUS P5GDC Deluxe: Intel socket775 + 915P + ICH6R @@ -2362,6 +2363,7 @@ {0x8086, 0x2570, 0x1043, 0x80f2, 0x8086, 0x24d3, 0x1043, 0x80a6, "^P4P800-E$", NULL, NULL, P3, "ASUS", "P4P800-E Deluxe", 0, OK, intel_ich_gpio21_raise}, {0x8086, 0x2570, 0x1043, 0x80a5, 0x8086, 0x24d3, 0x1043, 0x80a6, "^P4P800-VM$", NULL, NULL, P3, "ASUS", "P4P800-VM", 0, OK, intel_ich_gpio21_raise}, {0x8086, 0x2570, 0x1043, 0x80f2, 0x8086, 0x24d3, 0x1043, 0x80a6, "^P4P800-X$", NULL, NULL, P3, "ASUS", "P4P800-X", 0, OK, intel_ich_gpio21_raise}, + {0x8086, 0x2570, 0x1043, 0x80f2, 0x8086, 0x24d3, 0, 0, "^P4P800SE$", NULL, NULL, P3, "ASUS", "P4P800SE", 0, OK, intel_ich_gpio21_raise}, {0x8086, 0x2570, 0x1043, 0x80b2, 0x8086, 0x24c3, 0x1043, 0x8089, "^P4PE-X/TE$",NULL, NULL, P3, "ASUS", "P4PE-X/TE", 0, NT, intel_ich_gpio21_raise}, {0x1039, 0x0651, 0x1043, 0x8081, 0x1039, 0x0962, 0, 0, NULL, NULL, NULL, P3, "ASUS", "P4SC-E", 0, OK, it8707f_write_enable_2e}, {0x8086, 0x2570, 0x1043, 0x80A5, 0x105A, 0x24D3, 0x1043, 0x80A6, NULL, NULL, NULL, P3, "ASUS", "P4SD-LA", 0, NT, intel_ich_gpio32_raise}, diff --git a/print.c b/print.c index 2901c50..67cb89a 100644 --- a/print.c +++ b/print.c @@ -676,6 +676,7 @@ B("ASUS", "P4P800-E Deluxe", OK, "https://www.asus.com/Motherboards/Intel_Socket_478/P4P800E_Deluxe/", NULL), B("ASUS", "P4P800-VM", OK, "https://www.asus.com/Motherboards/Intel_Socket_478/P4P800VM/", NULL), B("ASUS", "P4P800-X", OK, "https://www.asus.com/Motherboards/Intel_Socket_478/P4P800X/", NULL), + B("ASUS", "P4P800SE", OK, "https://www.asus.com/supportonly/P4P800 SE/", NULL), B("ASUS", "P4PE-X/TE", NT, "https://www.asus.com/999/html/events/mb/socket478/p4pe-x-te/overview.htm", NULL), B("ASUS", "P4S533-X", OK, NULL, NULL), B("ASUS", "P4S800-MX", OK, "https://www.asus.com/Motherboards/Intel_Socket_478/P4S800MX/", NULL), -- To view, visit https://review.coreboot.org/c/flashrom/+/34764 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I12b25ca3f85e5f2302681bddbe1adafa49c5fcb9 Gerrit-Change-Number: 34764 Gerrit-PatchSet: 1 Gerrit-Owner: Miklós Márton <martonmiklosqdev(a)gmail.com> Gerrit-MessageType: newchange

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