June 2019 - flashrom-gerrit - mail.coreboot.org

Change in ...flashrom[master]: [WIP] picki2_spi: update to libusb1 and drop libusb0 dependence
by Thomas Heijligen (Code Review) 10 Jul '19

10 Jul '19

Thomas Heijligen has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/32213 Change subject: [WIP] picki2_spi: update to libusb1 and drop libusb0 dependence ...................................................................... [WIP] picki2_spi: update to libusb1 and drop libusb0 dependence Change-Id: Icfc5372aa1789d35ed22d68297d5e68a74d40388 Signed-off-by: Thomas Heijligen <thomas.heijligen(a)secunet.com> --- M Makefile M meson.build M meson_options.txt M pickit2_spi.c 4 files changed, 50 insertions(+), 130 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/13/32213/1 diff --git a/Makefile b/Makefile index 1e7db3e..9d6123a 100644 --- a/Makefile +++ b/Makefile @@ -679,15 +679,12 @@ $(eval $(var)=yes))) endif -# Disable feature groups -ifeq ($(CONFIG_ENABLE_LIBUSB0_PROGRAMMERS), no) -override CONFIG_PICKIT2_SPI = no -endif ifeq ($(CONFIG_ENABLE_LIBUSB1_PROGRAMMERS), no) override CONFIG_CH341A_SPI = no override CONFIG_DEDIPROG = no override CONFIG_DIGILENT_SPI = no override CONFIG_DEVELOPERBOX_SPI = no +override CONFIG_PICKIT2_SPI = no endif ifeq ($(CONFIG_ENABLE_LIBPCI_PROGRAMMERS), no) override CONFIG_INTERNAL = no @@ -852,7 +849,7 @@ ifeq ($(CONFIG_PICKIT2_SPI), yes) FEATURE_CFLAGS += -D'CONFIG_PICKIT2_SPI=1' PROGRAMMER_OBJS += pickit2_spi.o -NEED_LIBUSB0 += CONFIG_PICKIT2_SPI +NEED_LIBUSB1 += CONFIG_PICKIT2_SPI endif ifneq ($(NEED_LIBFTDI), ) @@ -1023,11 +1020,6 @@ endif -ifneq ($(NEED_LIBUSB0), ) -CHECK_LIBUSB0 = yes -FEATURE_CFLAGS += -D'NEED_LIBUSB0=1' -USBLIBS := $(call debug_shell,[ -n "$(PKG_CONFIG_LIBDIR)" ] && export PKG_CONFIG_LIBDIR="$(PKG_CONFIG_LIBDIR)" ; $(PKG_CONFIG) --libs libusb || printf "%s" "-lusb") -endif ifneq ($(NEED_LIBUSB1), ) CHECK_LIBUSB1 = yes @@ -1179,23 +1171,6 @@ endef export PCI_GET_DEV_TEST -define LIBUSB0_TEST -#include "platform.h" -#if IS_WINDOWS -#include <lusb0_usb.h> -#else -#include <usb.h> -#endif -int main(int argc, char **argv) -{ - (void) argc; - (void) argv; - usb_init(); - return 0; -} -endef -export LIBUSB0_TEST - define LIBUSB1_TEST #include <stddef.h> #include <libusb.h> @@ -1261,28 +1236,6 @@ rm -f .test.c .test.o .test$(EXEC_SUFFIX); exit 1; }; }; } 2>>$(BUILD_DETAILS_FILE); echo $? >&3 ; } | tee -a $(BUILD_DETAILS_FILE) >&4; } 3>&1;} | { read rc ; exit ${rc}; } } 4>&1 @rm -f .test.c .test.o .test$(EXEC_SUFFIX) endif -ifeq ($(CHECK_LIBUSB0), yes) - @printf "Checking for libusb-0.1/libusb-compat headers... " | tee -a $(BUILD_DETAILS_FILE) - @echo "$$LIBUSB0_TEST" > .test.c - @printf "\nexec: %s\n" "$(CC) -c $(CPPFLAGS) $(CFLAGS) .test.c -o .test.o" >>$(BUILD_DETAILS_FILE) - @{ { { { { $(CC) -c $(CPPFLAGS) $(CFLAGS) .test.c -o .test.o >&2 && \ - echo "found." || { echo "not found."; echo; \ - echo "The following features require libusb-0.1/libusb-compat: $(NEED_LIBUSB0)."; \ - echo "Please install libusb-0.1 headers or libusb-compat headers or disable all features"; \ - echo "mentioned above by specifying make CONFIG_ENABLE_LIBUSB0_PROGRAMMERS=no"; \ - echo "See README for more information."; echo; \ - rm -f .test.c .test.o; exit 1; }; } 2>>$(BUILD_DETAILS_FILE); echo $? >&3 ; } | tee -a $(BUILD_DETAILS_FILE) >&4; } 3>&1;} | { read rc ; exit ${rc}; } } 4>&1 - @printf "Checking if libusb-0.1 is usable... " | tee -a $(BUILD_DETAILS_FILE) - @printf "\nexec: %s\n" "$(CC) $(LDFLAGS) .test.o -o .test$(EXEC_SUFFIX) $(LIBS) $(USBLIBS)" >>$(BUILD_DETAILS_FILE) - @{ { { { { $(CC) $(LDFLAGS) .test.o -o .test$(EXEC_SUFFIX) $(LIBS) $(USBLIBS) >&2 && \ - echo "yes." || { echo "no."; \ - echo "The following features require libusb-0.1/libusb-compat: $(NEED_LIBUSB0)."; \ - echo "Please install libusb-0.1 or libusb-compat or disable all features"; \ - echo "mentioned above by specifying make CONFIG_ENABLE_LIBUSB0_PROGRAMMERS=no"; \ - echo "See README for more information."; echo; \ - rm -f .test.c .test.o .test$(EXEC_SUFFIX); exit 1; }; } 2>>$(BUILD_DETAILS_FILE); echo $? >&3 ; } | tee -a $(BUILD_DETAILS_FILE) >&4; } 3>&1;} | { read rc ; exit ${rc}; } } 4>&1 - @rm -f .test.c .test.o .test$(EXEC_SUFFIX) -endif ifeq ($(CHECK_LIBUSB1), yes) @printf "Checking for libusb-1.0 headers... " | tee -a $(BUILD_DETAILS_FILE) @echo "$$LIBUSB1_TEST" > .test.c diff --git a/meson.build b/meson.build index 1923fdf..e1b6c16 100644 --- a/meson.build +++ b/meson.build @@ -67,7 +67,6 @@ deps = [] srcs = [] -need_libusb0 = false need_raw_access = false need_serial = false @@ -91,6 +90,7 @@ config_dediprog = false config_digilent_spi = false config_developerbox_spi = false + config_pickit2_spi = false endif # some programmers require libpci @@ -242,7 +242,6 @@ if config_pickit2_spi srcs += 'pickit2_spi.c' cargs += '-DCONFIG_PICKIT2_SPI=1' - need_libusb0 = true endif if config_pony_spi srcs += 'pony_spi.c' @@ -293,11 +292,6 @@ srcs += 'serial.c' endif -# raw deprecated and old USB library -if need_libusb0 - deps += dependency('libusb') -endif - prefix = get_option('prefix') sbindir = join_paths(prefix, get_option('sbindir')) libdir = join_paths(prefix, get_option('libdir')) diff --git a/meson_options.txt b/meson_options.txt index 962866c..b7633d0 100644 --- a/meson_options.txt +++ b/meson_options.txt @@ -26,7 +26,7 @@ option('config_nicnatsemi', type : 'boolean', value : false, description : 'National Semiconductor NICs') option('config_nicrealtek', type : 'boolean', value : true, description : 'Realtek NICs') option('config_ogp_spi', type : 'boolean', value : true, description : 'SPI on OGP cards') -option('config_pickit2_spi', type : 'boolean', value : false, description : 'PICkit2 SPI') +option('config_pickit2_spi', type : 'boolean', value : true, description : 'PICkit2 SPI') option('config_pony_spi', type : 'boolean', value : true, description : 'PonyProg2000 SPI') option('config_rayer_spi', type : 'boolean', value : true, description : 'RayeR SPIPGM') option('config_satamv', type : 'boolean', value : true, description : 'Marvell SATA controllers') diff --git a/pickit2_spi.c b/pickit2_spi.c index 4354025..21a63f8 100644 --- a/pickit2_spi.c +++ b/pickit2_spi.c @@ -39,12 +39,7 @@ #include <string.h> #include <limits.h> #include <errno.h> - -#if IS_WINDOWS -#include <lusb0_usb.h> -#else -#include <usb.h> -#endif +#include <libusb.h> #include "flash.h" #include "chipdrivers.h" @@ -57,7 +52,7 @@ {} }; -static usb_dev_handle *pickit2_handle; +static libusb_device_handle *pickit2_handle; /* Default USB transaction timeout in ms */ #define DFLT_TIMEOUT 10000 @@ -94,36 +89,17 @@ #define SCR_VDD_OFF 0xFE #define SCR_VDD_ON 0xFF -/* Might be useful for other USB devices as well. static for now. - * device parameter allows user to specify one device of multiple installed */ -static struct usb_device *get_device_by_vid_pid(uint16_t vid, uint16_t pid, unsigned int device) -{ - struct usb_bus *bus; - struct usb_device *dev; - - for (bus = usb_get_busses(); bus; bus = bus->next) - for (dev = bus->devices; dev; dev = dev->next) - if ((dev->descriptor.idVendor == vid) && - (dev->descriptor.idProduct == pid)) { - if (device == 0) - return dev; - device--; - } - - return NULL; -} - static int pickit2_get_firmware_version(void) { int ret; uint8_t command[CMD_LENGTH] = {CMD_GET_VERSION, CMD_END_OF_BUFFER}; - ret = usb_interrupt_write(pickit2_handle, ENDPOINT_OUT, (char *)command, CMD_LENGTH, DFLT_TIMEOUT); - ret = usb_interrupt_read(pickit2_handle, ENDPOINT_IN, (char *)command, CMD_LENGTH, DFLT_TIMEOUT); + ret = libusb_interrupt_transfer(pickit2_handle, ENDPOINT_OUT, (unsigned char *)command, CMD_LENGTH, NULL, DFLT_TIMEOUT); + ret = libusb_interrupt_transfer(pickit2_handle, ENDPOINT_IN, (unsigned char *)command, CMD_LENGTH, NULL, DFLT_TIMEOUT); msg_pdbg("PICkit2 Firmware Version: %d.%d\n", (int)command[0], (int)command[1]); - if (ret != CMD_LENGTH) { - msg_perr("Command Get Firmware Version failed (%s)!\n", usb_strerror()); + if (ret != 0) { + msg_perr("Command Get Firmware Version failed!\n"); return 1; } @@ -166,10 +142,10 @@ CMD_END_OF_BUFFER }; - int ret = usb_interrupt_write(pickit2_handle, ENDPOINT_OUT, (char *)command, CMD_LENGTH, DFLT_TIMEOUT); + int ret = libusb_interrupt_transfer(pickit2_handle, ENDPOINT_OUT, (unsigned char *)command, CMD_LENGTH, NULL, DFLT_TIMEOUT); - if (ret != CMD_LENGTH) { - msg_perr("Command Set Voltage failed (%s)!\n", usb_strerror()); + if (ret != 0) { + msg_perr("Command Set Voltage failed!\n"); return 1; } @@ -201,10 +177,10 @@ CMD_END_OF_BUFFER }; - int ret = usb_interrupt_write(pickit2_handle, ENDPOINT_OUT, (char *)command, CMD_LENGTH, DFLT_TIMEOUT); + int ret = libusb_interrupt_transfer(pickit2_handle, ENDPOINT_OUT, (unsigned char*)command, CMD_LENGTH, NULL, DFLT_TIMEOUT); - if (ret != CMD_LENGTH) { - msg_perr("Command Set SPI Speed failed (%s)!\n", usb_strerror()); + if (ret != 0) { + msg_perr("Command Set SPI Speed failed!\n"); return 1; } @@ -270,18 +246,19 @@ buf[i++] = CMD_UPLOAD_DATA; buf[i++] = CMD_END_OF_BUFFER; - int ret = usb_interrupt_write(pickit2_handle, ENDPOINT_OUT, (char *)buf, CMD_LENGTH, DFLT_TIMEOUT); + int ret = libusb_interrupt_transfer(pickit2_handle, ENDPOINT_OUT, (unsigned char *)buf, CMD_LENGTH, NULL, DFLT_TIMEOUT); - if (ret != CMD_LENGTH) { - msg_perr("Send SPI failed, expected %i, got %i %s!\n", writecnt, ret, usb_strerror()); + if (ret != 0) { + msg_perr("Send SPI failed!\n"); return 1; } if (readcnt) { - ret = usb_interrupt_read(pickit2_handle, ENDPOINT_IN, (char *)buf, CMD_LENGTH, DFLT_TIMEOUT); + int length = 0; + ret = libusb_interrupt_transfer(pickit2_handle, ENDPOINT_IN, (unsigned char *)buf, CMD_LENGTH, &length, DFLT_TIMEOUT); - if (ret != CMD_LENGTH) { - msg_perr("Receive SPI failed, expected %i, got %i %s!\n", readcnt, ret, usb_strerror()); + if (length == 0 || ret != 0) { + msg_perr("Receive SPI failed\n"); return 1; } @@ -377,27 +354,22 @@ CMD_END_OF_BUFFER }; - int ret = usb_interrupt_write(pickit2_handle, ENDPOINT_OUT, (char *)command, CMD_LENGTH, DFLT_TIMEOUT); + int ret = libusb_interrupt_transfer(pickit2_handle, ENDPOINT_OUT, (unsigned char*)command, CMD_LENGTH, NULL, DFLT_TIMEOUT); - if (ret != CMD_LENGTH) { - msg_perr("Command Shutdown failed (%s)!\n", usb_strerror()); + if (ret != 0) { + msg_perr("Command Shutdown failed (%s)!\n", libusb_strerror(ret)); ret = 1; } - if (usb_release_interface(pickit2_handle, 0) != 0) { + if (libusb_release_interface(pickit2_handle, 0) != 0) { msg_perr("Could not release USB interface!\n"); ret = 1; } - if (usb_close(pickit2_handle) != 0) { - msg_perr("Could not close USB device!\n"); - ret = 1; - } + libusb_close(pickit2_handle); return ret; } int pickit2_spi_init(void) { - unsigned int usedevice = 0; // FIXME: Allow selecting one of multiple devices - uint8_t buf[CMD_LENGTH] = { CMD_EXEC_SCRIPT, 10, /* Script length */ @@ -444,31 +416,33 @@ } /* Here comes the USB stuff */ - usb_init(); - (void)usb_find_busses(); - (void)usb_find_devices(); + if (pickit2_handle != NULL) { + // FIXME print error + return -1; + } + if (libusb_init(NULL) < 0) { + // FIXME print error + return -1; + } + + // FIXME libusb debug + const uint16_t vid = devs_pickit2_spi[0].vendor_id; const uint16_t pid = devs_pickit2_spi[0].device_id; - struct usb_device *dev = get_device_by_vid_pid(vid, pid, usedevice); - if (dev == NULL) { - msg_perr("Could not find a PICkit2 on USB!\n"); + pickit2_handle = libusb_open_device_with_vid_pid(NULL, vid, pid); + if (pickit2_handle == NULL) { + msg_perr("Could not open device PICkit2!\n"); return 1; } - msg_pdbg("Found USB device (%04x:%04x).\n", dev->descriptor.idVendor, dev->descriptor.idProduct); - pickit2_handle = usb_open(dev); - int ret = usb_set_configuration(pickit2_handle, 1); - if (ret != 0) { - msg_perr("Could not set USB device configuration: %i %s\n", ret, usb_strerror()); - if (usb_close(pickit2_handle) != 0) - msg_perr("Could not close USB device!\n"); + if (libusb_set_configuration(pickit2_handle, 1) != 0) { + msg_perr("Could not set USB device configuration.\n"); + libusb_close(pickit2_handle); return 1; } - ret = usb_claim_interface(pickit2_handle, 0); - if (ret != 0) { - msg_perr("Could not claim USB device interface %i: %i %s\n", 0, ret, usb_strerror()); - if (usb_close(pickit2_handle) != 0) - msg_perr("Could not close USB device!\n"); + if (libusb_claim_interface(pickit2_handle, 0) != 0) { + msg_perr("Could not claim USB device interface\n"); + libusb_close(pickit2_handle); return 1; } @@ -493,9 +467,8 @@ /* Perform basic setup. * Configure pin directions and logic levels, turn Vdd on, turn busy LED on and clear buffers. */ - ret = usb_interrupt_write(pickit2_handle, ENDPOINT_OUT, (char *)buf, CMD_LENGTH, DFLT_TIMEOUT); - if (ret != CMD_LENGTH) { - msg_perr("Command Setup failed (%s)!\n", usb_strerror()); + if (libusb_interrupt_transfer(pickit2_handle, ENDPOINT_OUT, (unsigned char *)buf, CMD_LENGTH, NULL, DFLT_TIMEOUT) != 0) { + msg_perr("Command Setup failed!\n"); return 1; } -- To view, visit https://review.coreboot.org/c/flashrom/+/32213 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Icfc5372aa1789d35ed22d68297d5e68a74d40388 Gerrit-Change-Number: 32213 Gerrit-PatchSet: 1 Gerrit-Owner: Thomas Heijligen <src(a)posteo.de> Gerrit-MessageType: newchange

4 13

Change in ...flashrom[master]: ichspi: Add Apollo Lake support
by Nico Huber (Code Review) 06 Jul '19

06 Jul '19

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/30995 Change subject: ichspi: Add Apollo Lake support ...................................................................... ichspi: Add Apollo Lake support It's almost identical to 100 series PCHs and later. There are some addition FREGs (12..15). To not clutter the `if` conditions further, make more use of `switch` statements. Tested on Kontron mAL10. Mark it as DEP as usually the last sector is not covered by the descriptor layout and can't be read. Change-Id: I1c464b5b3d151e6d28d5db96495fe874a0a45718 Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- M chipset_enable.c M ich_descriptors.c M ichspi.c 3 files changed, 153 insertions(+), 62 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/95/30995/1 diff --git a/chipset_enable.c b/chipset_enable.c index 547f21a..2f73ded 100644 --- a/chipset_enable.c +++ b/chipset_enable.c @@ -1965,7 +1965,7 @@ {0x8086, 0xa2c8, NT, "Intel", "B250", enable_flash_pch100}, {0x8086, 0xa2c9, NT, "Intel", "Z370", enable_flash_pch100}, {0x8086, 0xa2d2, NT, "Intel", "X299", enable_flash_pch100}, - {0x8086, 0x5ae8, BAD, "Intel", "Apollo Lake", enable_flash_apl}, + {0x8086, 0x5ae8, DEP, "Intel", "Apollo Lake", enable_flash_apl}, #endif {0}, }; diff --git a/ich_descriptors.c b/ich_descriptors.c index 56e846f..dcbcfae 100644 --- a/ich_descriptors.c +++ b/ich_descriptors.c @@ -42,6 +42,8 @@ ssize_t ich_number_of_regions(const enum ich_chipset cs, const struct ich_desc_content *const cont) { switch (cs) { + case CHIPSET_APOLLO_LAKE: + return 6; case CHIPSET_C620_SERIES_LEWISBURG: return 16; case CHIPSET_100_SERIES_SUNRISE_POINT: @@ -67,6 +69,7 @@ { switch (cs) { case CHIPSET_C620_SERIES_LEWISBURG: + case CHIPSET_APOLLO_LAKE: if (cont->NM <= MAX_NUM_MASTERS) return cont->NM; default: @@ -139,8 +142,8 @@ msg_pdbg2("FRBA (Flash Region Base Address): 0x%03x\n", getFRBA(cont)); msg_pdbg2("NC (Number of Components): %5d\n", cont->NC + 1); msg_pdbg2("FCBA (Flash Component Base Address): 0x%03x\n", getFCBA(cont)); - msg_pdbg2("ISL (ICH/PCH Strap Length): %5d\n", cont->ISL); - msg_pdbg2("FISBA/FPSBA (Flash ICH/PCH Strap Base Address): 0x%03x\n", getFISBA(cont)); + msg_pdbg2("ISL (ICH/PCH/SoC Strap Length): %5d\n", cont->ISL); + msg_pdbg2("FISBA/FPSBA (Flash ICH/PCH/SoC Strap Base Addr): 0x%03x\n", getFISBA(cont)); msg_pdbg2("NM (Number of Masters): %5zd\n", ich_number_of_masters(cs, cont)); msg_pdbg2("FMBA (Flash Master Base Address): 0x%03x\n", getFMBA(cont)); msg_pdbg2("MSL/PSL (MCH/PROC Strap Length): %5d\n", cont->MSL); @@ -193,7 +196,8 @@ case CHIPSET_9_SERIES_WILDCAT_POINT: case CHIPSET_9_SERIES_WILDCAT_POINT_LP: case CHIPSET_100_SERIES_SUNRISE_POINT: - case CHIPSET_C620_SERIES_LEWISBURG: { + case CHIPSET_C620_SERIES_LEWISBURG: + case CHIPSET_APOLLO_LAKE: { uint8_t size_enc; if (idx == 0) { size_enc = desc->component.dens_new.comp1_density; @@ -212,7 +216,7 @@ static const char *pprint_freq(enum ich_chipset cs, uint8_t value) { - static const char *const freq_str[2][8] = { { + static const char *const freq_str[3][8] = { { "20 MHz", /* 000 */ "33 MHz", /* 001 */ "reserved", /* 010 */ @@ -230,6 +234,15 @@ "reserved", /* 101 */ "17 MHz", /* 110 */ "reserved" /* 111 */ + }, { + "reserved", /* 000 */ + "50 MHz", /* 001 */ + "40 MHz", /* 010 */ + "reserved", /* 011 */ + "25 MHz", /* 100 */ + "reserved", /* 101 */ + "17 MHz", /* 110 */ + "reserved" /* 111 */ } }; switch (cs) { @@ -251,6 +264,8 @@ case CHIPSET_100_SERIES_SUNRISE_POINT: case CHIPSET_C620_SERIES_LEWISBURG: return freq_str[1][value]; + case CHIPSET_APOLLO_LAKE: + return freq_str[2][value]; case CHIPSET_ICH_UNKNOWN: default: return "unknown"; @@ -259,11 +274,23 @@ void prettyprint_ich_descriptor_component(enum ich_chipset cs, const struct ich_descriptors *desc) { + bool has_flill1; + + switch (cs) { + case CHIPSET_100_SERIES_SUNRISE_POINT: + case CHIPSET_C620_SERIES_LEWISBURG: + case CHIPSET_APOLLO_LAKE: + has_flill1 = true; + break; + default: + has_flill1 = false; + break; + } msg_pdbg2("=== Component Section ===\n"); msg_pdbg2("FLCOMP 0x%08x\n", desc->component.FLCOMP); msg_pdbg2("FLILL 0x%08x\n", desc->component.FLILL ); - if (cs == CHIPSET_100_SERIES_SUNRISE_POINT || cs == CHIPSET_C620_SERIES_LEWISBURG) + if (has_flill1) msg_pdbg2("FLILL1 0x%08x\n", desc->component.FLILL1); msg_pdbg2("\n"); @@ -296,7 +323,7 @@ msg_pdbg2("Invalid instruction 3: 0x%02x\n", desc->component.invalid_instr3); } - if (cs == CHIPSET_100_SERIES_SUNRISE_POINT || cs == CHIPSET_C620_SERIES_LEWISBURG) { + if (has_flill1) { if (desc->component.FLILL1 != 0) { has_forbidden_opcode = 1; msg_pdbg2("Invalid instruction 4: 0x%02x\n", @@ -318,7 +345,7 @@ static void pprint_freg(const struct ich_desc_region *reg, uint32_t i) { static const char *const region_names[] = { - "Descr.", "BIOS", "ME", "GbE", "Platf.", "unknown", "BIOS2", "unknown", + "Descr.", "BIOS", "ME", "GbE", "Platf.", "DevExt", "BIOS2", "unknown", "EC/BMC", "unknown", "IE", "10GbE", "unknown", "unknown", "unknown", "unknown" }; if (i >= ARRAY_SIZE(region_names)) { @@ -415,6 +442,23 @@ desc->master.mstr[i].write & (1 << j) ? 'w' : ' '); msg_pdbg2("\n"); } + } else if (cs == CHIPSET_APOLLO_LAKE) { + const char *const master_names[] = { "BIOS", "TXE", }; + if (nm > ARRAY_SIZE(master_names)) { + msg_pdbg2("%s: number of masters too high (%d).\n", __func__, desc->content.NM); + return; + } + + msg_pdbg2(" FD IFWI TXE n/a Platf DevExt\n"); + for (i = 0; i < nm; i++) { + size_t j; + msg_pdbg2("%-4s", master_names[i]); + for (j = 0; j < ich_number_of_regions(cs, &desc->content); j++) + msg_pdbg2(" %c%c ", + desc->master.mstr[i].read & (1 << j) ? 'r' : ' ', + desc->master.mstr[i].write & (1 << j) ? 'w' : ' '); + msg_pdbg2("\n"); + } } else { const struct ich_desc_master *const mstr = &desc->master; msg_pdbg2(" Descr. BIOS ME GbE Platf.\n"); @@ -857,6 +901,11 @@ return CHIPSET_ICH10; else if (content->ISL <= 16) return CHIPSET_5_SERIES_IBEX_PEAK; + else if (content->FLMAP2 == 0) { + if (content->ISL != 19) + msg_pwarn("Peculiar firmware descriptor, assuming Apollo Lake compatibility.\n"); + return CHIPSET_APOLLO_LAKE; + } msg_pwarn("Peculiar firmware descriptor, assuming Ibex Peak compatibility.\n"); return CHIPSET_5_SERIES_IBEX_PEAK; } else if (content->ICCRIBA < 0x31 && content->FMSBA < 0x30) { @@ -886,8 +935,20 @@ { const enum ich_chipset guess = guess_ich_chipset_from_content(content); - if (component->modes.freq_read == 6) { - if ((guess != CHIPSET_100_SERIES_SUNRISE_POINT) && (guess != CHIPSET_C620_SERIES_LEWISBURG)) { + switch (guess) { + case CHIPSET_100_SERIES_SUNRISE_POINT: + case CHIPSET_C620_SERIES_LEWISBURG: + case CHIPSET_APOLLO_LAKE: + if (component->modes.freq_read != 6) { + msg_pwarn("\nThe firmware descriptor looks like a Skylake/Sunrise Point descriptor.\n" + "However, the read frequency isn't set to 17MHz (the only valid value).\n" + "Please report this message, the output of `ich_descriptors_tool` for\n" + "your descriptor and the output of `lspci -nn` to flashrom(a)flashrom.org\n\n"); + return CHIPSET_9_SERIES_WILDCAT_POINT; + } + return guess; + default: + if (component->modes.freq_read == 6) { msg_pwarn("\nThe firmware descriptor has the read frequency set to 17MHz. However,\n" "it doesn't look like a Skylake/Sunrise Point compatible descriptor.\n" "Please report this message, the output of `ich_descriptors_tool` for\n" @@ -895,17 +956,7 @@ return CHIPSET_100_SERIES_SUNRISE_POINT; } return guess; - } else { - if (guess == CHIPSET_100_SERIES_SUNRISE_POINT || guess == CHIPSET_C620_SERIES_LEWISBURG) { - msg_pwarn("\nThe firmware descriptor looks like a Skylake/Sunrise Point descriptor.\n" - "However, the read frequency isn't set to 17MHz (the only valid value).\n" - "Please report this message, the output of `ich_descriptors_tool` for\n" - "your descriptor and the output of `lspci -nn` to flashrom(a)flashrom.org\n\n"); - return CHIPSET_9_SERIES_WILDCAT_POINT; - } } - - return guess; } /* len is the length of dump in bytes */ @@ -1036,6 +1087,7 @@ case CHIPSET_9_SERIES_WILDCAT_POINT_LP: case CHIPSET_100_SERIES_SUNRISE_POINT: case CHIPSET_C620_SERIES_LEWISBURG: + case CHIPSET_APOLLO_LAKE: if (idx == 0) { size_enc = desc->component.dens_new.comp1_density; } else { @@ -1066,10 +1118,13 @@ uint32_t control = 0; control |= (section << FDOC_FDSS_OFF) & FDOC_FDSS; control |= (offset << FDOC_FDSI_OFF) & FDOC_FDSI; - if (cs == CHIPSET_100_SERIES_SUNRISE_POINT || cs == CHIPSET_C620_SERIES_LEWISBURG) { + switch (cs) { + case CHIPSET_100_SERIES_SUNRISE_POINT: + case CHIPSET_C620_SERIES_LEWISBURG: + case CHIPSET_APOLLO_LAKE: mmio_le_writel(control, spibar + PCH100_REG_FDOC); return mmio_le_readl(spibar + PCH100_REG_FDOD); - } else { + default: mmio_le_writel(control, spibar + ICH9_REG_FDOC); return mmio_le_readl(spibar + ICH9_REG_FDOD); } diff --git a/ichspi.c b/ichspi.c index 9eb24a9..2c8a89f 100644 --- a/ichspi.c +++ b/ichspi.c @@ -29,6 +29,9 @@ #include "spi.h" #include "ich_descriptors.h" +/* Apollo Lake */ +#define APL_REG_FREG12 0xe0 /* 32 Bytes Flash Region 12 */ + /* Sunrise Point */ /* Added HSFS Status bits */ @@ -1564,15 +1567,17 @@ static enum ich_access_protection ich9_handle_frap(uint32_t frap, int i) { const int rwperms_unknown = ARRAY_SIZE(access_names); - static const char *const region_names[5] = { + static const char *const region_names[6] = { "Flash Descriptor", "BIOS", "Management Engine", - "Gigabit Ethernet", "Platform Data" + "Gigabit Ethernet", "Platform Data", "Device Extension", }; const char *const region_name = i < ARRAY_SIZE(region_names) ? region_names[i] : "unknown"; uint32_t base, limit; int rwperms; - int offset = ICH9_REG_FREG0 + i * 4; + const int offset = i < 12 + ? ICH9_REG_FREG0 + i * 4 + : APL_REG_FREG12 + (i - 12) * 4; uint32_t freg = mmio_readl(ich_spibar + offset); if (i < 8) { @@ -1716,8 +1721,10 @@ ich_spibar = spibar; /* Moving registers / bits */ - if (ich_generation == CHIPSET_100_SERIES_SUNRISE_POINT) { - num_freg = 10; + switch (ich_generation) { + case CHIPSET_100_SERIES_SUNRISE_POINT: + case CHIPSET_C620_SERIES_LEWISBURG: + case CHIPSET_APOLLO_LAKE: num_pr = 6; /* Includes GPR0 */ reg_pr0 = PCH100_REG_FPR0; swseq_data.reg_ssfsc = PCH100_REG_SSFSC; @@ -1727,19 +1734,8 @@ hwseq_data.addr_mask = PCH100_FADDR_FLA; hwseq_data.only_4k = true; hwseq_data.hsfc_fcycle = PCH100_HSFC_FCYCLE; - } else if (ich_generation == CHIPSET_C620_SERIES_LEWISBURG) { - num_freg = 12; /* 12 MMIO regs, but 16 regions in FD spec */ - num_pr = 6; /* Includes GPR0 */ - reg_pr0 = PCH100_REG_FPR0; - swseq_data.reg_ssfsc = PCH100_REG_SSFSC; - swseq_data.reg_preop = PCH100_REG_PREOP; - swseq_data.reg_optype = PCH100_REG_OPTYPE; - swseq_data.reg_opmenu = PCH100_REG_OPMENU; - hwseq_data.addr_mask = PCH100_FADDR_FLA; - hwseq_data.only_4k = true; - hwseq_data.hsfc_fcycle = PCH100_HSFC_FCYCLE; - } else { - num_freg = 5; + break; + default: num_pr = 5; reg_pr0 = ICH9_REG_PR0; swseq_data.reg_ssfsc = ICH9_REG_SSFS; @@ -1749,6 +1745,21 @@ hwseq_data.addr_mask = ICH9_FADDR_FLA; hwseq_data.only_4k = false; hwseq_data.hsfc_fcycle = HSFC_FCYCLE; + break; + } + switch (ich_generation) { + case CHIPSET_100_SERIES_SUNRISE_POINT: + num_freg = 10; + break; + case CHIPSET_C620_SERIES_LEWISBURG: + num_freg = 12; /* 12 MMIO regs, but 16 regions in FD spec */ + break; + case CHIPSET_APOLLO_LAKE: + num_freg = 16; + break; + default: + num_freg = 5; + break; } switch (ich_generation) { @@ -1834,10 +1845,16 @@ tmp = mmio_readl(ich_spibar + ICH9_REG_FADDR); msg_pdbg2("0x08: 0x%08x (FADDR)\n", tmp); - if (ich_gen == CHIPSET_100_SERIES_SUNRISE_POINT || ich_gen == CHIPSET_C620_SERIES_LEWISBURG) { - const uint32_t dlock = mmio_readl(ich_spibar + PCH100_REG_DLOCK); - msg_pdbg("0x0c: 0x%08x (DLOCK)\n", dlock); - prettyprint_pch100_reg_dlock(dlock); + switch (ich_gen) { + case CHIPSET_100_SERIES_SUNRISE_POINT: + case CHIPSET_C620_SERIES_LEWISBURG: + case CHIPSET_APOLLO_LAKE: + tmp = mmio_readl(ich_spibar + PCH100_REG_DLOCK); + msg_pdbg("0x0c: 0x%08x (DLOCK)\n", tmp); + prettyprint_pch100_reg_dlock(tmp); + break; + default: + break; } if (desc_valid) { @@ -1898,37 +1915,51 @@ swseq_data.reg_opmenu, mmio_readl(ich_spibar + swseq_data.reg_opmenu)); msg_pdbg("0x%zx: 0x%08x (OPMENU+4)\n", swseq_data.reg_opmenu + 4, mmio_readl(ich_spibar + swseq_data.reg_opmenu + 4)); - if (ich_generation == CHIPSET_ICH8 && desc_valid) { - tmp = mmio_readl(ich_spibar + ICH8_REG_VSCC); - msg_pdbg("0xC1: 0x%08x (VSCC)\n", tmp); - msg_pdbg("VSCC: "); - prettyprint_ich_reg_vscc(tmp, FLASHROM_MSG_DEBUG, true); - } else if (ich_generation != CHIPSET_100_SERIES_SUNRISE_POINT && - ich_generation != CHIPSET_C620_SERIES_LEWISBURG) { - if (ich_generation != CHIPSET_BAYTRAIL && desc_valid) { + + if (desc_valid) { + switch (ich_gen) { + case CHIPSET_ICH8: + case CHIPSET_100_SERIES_SUNRISE_POINT: + case CHIPSET_C620_SERIES_LEWISBURG: + case CHIPSET_APOLLO_LAKE: + case CHIPSET_BAYTRAIL: + break; + default: ichspi_bbar = mmio_readl(ich_spibar + ICH9_REG_BBAR); - msg_pdbg("0xA0: 0x%08x (BBAR)\n", - ichspi_bbar); + msg_pdbg("0x%x: 0x%08x (BBAR)\n", ICH9_REG_BBAR, ichspi_bbar); ich_set_bbar(0); + break; } - if (desc_valid) { + if (ich_gen == CHIPSET_ICH8) { + tmp = mmio_readl(ich_spibar + ICH8_REG_VSCC); + msg_pdbg("0x%x: 0x%08x (VSCC)\n", ICH8_REG_VSCC, tmp); + msg_pdbg("VSCC: "); + prettyprint_ich_reg_vscc(tmp, FLASHROM_MSG_DEBUG, true); + } else { tmp = mmio_readl(ich_spibar + ICH9_REG_LVSCC); - msg_pdbg("0xC4: 0x%08x (LVSCC)\n", tmp); + msg_pdbg("0x%x: 0x%08x (LVSCC)\n", ICH9_REG_LVSCC, tmp); msg_pdbg("LVSCC: "); prettyprint_ich_reg_vscc(tmp, FLASHROM_MSG_DEBUG, true); tmp = mmio_readl(ich_spibar + ICH9_REG_UVSCC); - msg_pdbg("0xC8: 0x%08x (UVSCC)\n", tmp); + msg_pdbg("0x%x: 0x%08x (UVSCC)\n", ICH9_REG_UVSCC, tmp); msg_pdbg("UVSCC: "); prettyprint_ich_reg_vscc(tmp, FLASHROM_MSG_DEBUG, false); - - tmp = mmio_readl(ich_spibar + ICH9_REG_FPB); - msg_pdbg("0xD0: 0x%08x (FPB)\n", tmp); } - } - if (desc_valid) { + switch (ich_gen) { + case CHIPSET_ICH8: + case CHIPSET_100_SERIES_SUNRISE_POINT: + case CHIPSET_C620_SERIES_LEWISBURG: + case CHIPSET_APOLLO_LAKE: + break; + default: + tmp = mmio_readl(ich_spibar + ICH9_REG_FPB); + msg_pdbg("0x%x: 0x%08x (FPB)\n", ICH9_REG_FPB, tmp); + break; + } + if (read_ich_descriptors_via_fdo(ich_gen, ich_spibar, &desc) == ICH_RET_OK) prettyprint_ich_descriptors(ich_gen, &desc); @@ -1955,6 +1986,11 @@ ich_spi_mode = ich_hwseq; } + if (ich_spi_mode == ich_auto && ich_gen == CHIPSET_APOLLO_LAKE) { + msg_pdbg("Enabling hardware sequencing by default for Apollo Lake.\n"); + ich_spi_mode = ich_hwseq; + } + if (ich_spi_mode == ich_hwseq) { if (!desc_valid) { msg_perr("Hardware sequencing was requested " -- To view, visit https://review.coreboot.org/c/flashrom/+/30995 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I1c464b5b3d151e6d28d5db96495fe874a0a45718 Gerrit-Change-Number: 30995 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newchange

4 19

Change in ...flashrom[master]: chipset_enable: Add Apollo Lake
by Nico Huber (Code Review) 06 Jul '19

06 Jul '19

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/30994 Change subject: chipset_enable: Add Apollo Lake ...................................................................... chipset_enable: Add Apollo Lake It works the same as 100 series PCHs and on. The SPI device is at 0:0d.2, though. Mark as BAD until `ichspi` is revised. Change-Id: I7b1ad402ba562b7b977be111f8cf61f1be50843a Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- M chipset_enable.c M programmer.h 2 files changed, 19 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/94/30994/1 diff --git a/chipset_enable.c b/chipset_enable.c index 4d624a3..547f21a 100644 --- a/chipset_enable.c +++ b/chipset_enable.c @@ -598,6 +598,7 @@ break; case CHIPSET_100_SERIES_SUNRISE_POINT: case CHIPSET_C620_SERIES_LEWISBURG: + case CHIPSET_APOLLO_LAKE: reg_name = "BIOS_SPI_BC"; gcs = pci_read_long(dev, 0xdc); bild = (gcs >> 7) & 1; @@ -621,6 +622,7 @@ static const char *const straps_names_pch567[] = { "LPC", "reserved", "PCI", "SPI" }; static const char *const straps_names_pch89_baytrail[] = { "LPC", "reserved", "reserved", "SPI" }; static const char *const straps_names_pch8_lp[] = { "SPI", "LPC" }; + static const char *const straps_names_apl[] = { "SPI", "reserved" }; static const char *const straps_names_unknown[] = { "unknown", "unknown", "unknown", "unknown" }; const char *const *straps_names; @@ -658,6 +660,9 @@ case CHIPSET_C620_SERIES_LEWISBURG: straps_names = straps_names_pch8_lp; break; + case CHIPSET_APOLLO_LAKE: + straps_names = straps_names_apl; + break; case CHIPSET_8_SERIES_WELLSBURG: // FIXME: check datasheet case CHIPSET_CENTERTON: // FIXME: Datasheet does not mention GCS at all straps_names = straps_names_unknown; @@ -680,6 +685,7 @@ break; case CHIPSET_100_SERIES_SUNRISE_POINT: case CHIPSET_C620_SERIES_LEWISBURG: + case CHIPSET_APOLLO_LAKE: bbs = (gcs >> 6) & 0x1; break; default: @@ -829,7 +835,9 @@ return 0; } -static int enable_flash_pch100_or_c620(struct pci_dev *const dev, const char *const name, const enum ich_chipset pch_generation) +static int enable_flash_pch100_or_c620( + struct pci_dev *const dev, const char *const name, + const int slot, const int func, const enum ich_chipset pch_generation) { int ret = ERROR_FATAL; @@ -850,7 +858,7 @@ pci_init(pci_acc); register_shutdown(enable_flash_pch100_shutdown, pci_acc); - struct pci_dev *const spi_dev = pci_get_dev(pci_acc, dev->domain, dev->bus, 0x1f, 5); + struct pci_dev *const spi_dev = pci_get_dev(pci_acc, dev->domain, dev->bus, slot, func); if (!spi_dev) { msg_perr("Can't allocate PCI device.\n"); return ret; @@ -888,12 +896,17 @@ static int enable_flash_pch100(struct pci_dev *const dev, const char *const name) { - return enable_flash_pch100_or_c620(dev, name, CHIPSET_100_SERIES_SUNRISE_POINT); + return enable_flash_pch100_or_c620(dev, name, 0x1f, 5, CHIPSET_100_SERIES_SUNRISE_POINT); } static int enable_flash_c620(struct pci_dev *const dev, const char *const name) { - return enable_flash_pch100_or_c620(dev, name, CHIPSET_C620_SERIES_LEWISBURG); + return enable_flash_pch100_or_c620(dev, name, 0x1f, 5, CHIPSET_C620_SERIES_LEWISBURG); +} + +static int enable_flash_apl(struct pci_dev *const dev, const char *const name) +{ + return enable_flash_pch100_or_c620(dev, name, 0x0d, 2, CHIPSET_APOLLO_LAKE); } /* Silvermont architecture: Bay Trail(-T/-I), Avoton/Rangeley. @@ -1952,6 +1965,7 @@ {0x8086, 0xa2c8, NT, "Intel", "B250", enable_flash_pch100}, {0x8086, 0xa2c9, NT, "Intel", "Z370", enable_flash_pch100}, {0x8086, 0xa2d2, NT, "Intel", "X299", enable_flash_pch100}, + {0x8086, 0x5ae8, BAD, "Intel", "Apollo Lake", enable_flash_apl}, #endif {0}, }; diff --git a/programmer.h b/programmer.h index 8bf7d29..64508c4 100644 --- a/programmer.h +++ b/programmer.h @@ -708,6 +708,7 @@ CHIPSET_9_SERIES_WILDCAT_POINT_LP, CHIPSET_100_SERIES_SUNRISE_POINT, /* also 6th/7th gen Core i/o (LP) variants */ CHIPSET_C620_SERIES_LEWISBURG, + CHIPSET_APOLLO_LAKE, }; /* ichspi.c */ -- To view, visit https://review.coreboot.org/c/flashrom/+/30994 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I7b1ad402ba562b7b977be111f8cf61f1be50843a Gerrit-Change-Number: 30994 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newchange

4 10

Change in ...flashrom[master]: flashchips.c: Replace comment with #if 0
by Alan Green (Code Review) 04 Jul '19

04 Jul '19

Alan Green has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/33836 Change subject: flashchips.c: Replace comment with #if 0 ...................................................................... flashchips.c: Replace comment with #if 0 To allow better handling by automated tools, replace /* */ commenting out a whole entry with #if 0 / #endif Signed-off-by: Alan Green <avg(a)google.com> Change-Id: Ib30b3a16f25de5def508d90ec9375563b1d4d384 --- M flashchips.c 1 file changed, 4 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/36/33836/1 diff --git a/flashchips.c b/flashchips.c index e421c4c..7f3d2a2 100644 --- a/flashchips.c +++ b/flashchips.c @@ -2511,7 +2511,8 @@ }, /*The AT26DF321 has the same ID as the AT25DF321. */ - /*{ +#if 0 + { .vendor = "Atmel", .name = "AT26DF321", .bustype = BUS_SPI, @@ -2527,7 +2528,8 @@ .unlock = spi_disable_blockprotect, .write = spi_chip_write_256, .read = spi_chip_read, - },*/ + }, +#endif { .vendor = "Atmel", -- To view, visit https://review.coreboot.org/c/flashrom/+/33836 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Ib30b3a16f25de5def508d90ec9375563b1d4d384 Gerrit-Change-Number: 33836 Gerrit-PatchSet: 1 Gerrit-Owner: Alan Green <avg(a)google.com> Gerrit-MessageType: newchange

4 18

Change in ...flashrom[master]: flashchips.c: SFDP-capable chip formatting
by Alan Green (Code Review) 03 Jul '19

03 Jul '19

Alan Green has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/33834 Change subject: flashchips.c: SFDP-capable chip formatting ...................................................................... flashchips.c: SFDP-capable chip formatting To allow automated tools to manipulate flashchips.c, make the definition of SFDP-capable chip more consistent with other definitions. This involves - reordering fields to match both other entries and the definition of struct flashchip. - reformatting comments to make them consistent with other entries. Signed-off-by: Alan Green <avg(a)google.com> Change-Id: I8708a11993822085b3e8d8c80532dfb935d39876 --- M flashchips.c 1 file changed, 10 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/34/33834/1 diff --git a/flashchips.c b/flashchips.c index 8ea7043..f9ad764 100644 --- a/flashchips.c +++ b/flashchips.c @@ -16578,7 +16578,8 @@ .read = read_memmapped, }, - {/* W29EE011, W29EE012, W29C010M, W29C011A do not support probe_jedec according to the datasheet, but it works for newer(?) steppings. */ + /* W29EE011, W29EE012, W29C010M, W29C011A do not support probe_jedec according to the datasheet, but it works for newer(?) steppings. */ + { .vendor = "Winbond", .name = "W29C010(M)/W29C011A/W29EE011/W29EE012", .bustype = BUS_PARALLEL, @@ -17428,21 +17429,20 @@ .bustype = BUS_SPI, .manufacture_id = GENERIC_MANUF_ID, .model_id = SFDP_DEVICE_ID, - /* We present our own "report this" text hence we do not - * want the default "This flash part has status UNTESTED..." - * text to be printed. */ + .total_size = 0, /* set by probing function */ + .page_size = 0, /* set by probing function */ + .feature_bits = 0, /* set by probing function */ + /* We present our own "report this" text hence we do not */ + /* want the default "This flash part has status UNTESTED..." */ + /* text to be printed. */ .tested = TEST_OK_PREW, .probe = probe_spi_sfdp, + .block_erasers = {}, /* set by probing function */ .unlock = spi_disable_blockprotect, /* is this safe? */ + .write = NULL, /* set by probing function */ .read = spi_chip_read, /* FIXME: some vendor extensions define this */ .voltage = {0}, - /* Everything below will be set by the probing function. */ - .write = NULL, - .total_size = 0, - .page_size = 0, - .feature_bits = 0, - .block_erasers = {}, }, { -- To view, visit https://review.coreboot.org/c/flashrom/+/33834 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I8708a11993822085b3e8d8c80532dfb935d39876 Gerrit-Change-Number: 33834 Gerrit-PatchSet: 1 Gerrit-Owner: Alan Green <avg(a)google.com> Gerrit-MessageType: newchange

3 8

Change in ...flashrom[master]: flashchips.c: Make comment placement consistent
by Alan Green (Code Review) 03 Jul '19

03 Jul '19

Alan Green has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/33837 Change subject: flashchips.c: Make comment placement consistent ...................................................................... flashchips.c: Make comment placement consistent For consistency, move a comment about an entry from inside the open brace to outside it. Signed-off-by: Alan Green <avg(a)google.com> Change-Id: Ie9a745b7e7dc752cfd6fc14ebeb04754179893c6 --- M flashchips.c 1 file changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/37/33837/1 diff --git a/flashchips.c b/flashchips.c index 8ea7043..f35965f 100644 --- a/flashchips.c +++ b/flashchips.c @@ -16578,7 +16578,8 @@ .read = read_memmapped, }, - {/* W29EE011, W29EE012, W29C010M, W29C011A do not support probe_jedec according to the datasheet, but it works for newer(?) steppings. */ + /* W29EE011, W29EE012, W29C010M, W29C011A do not support probe_jedec according to the datasheet, but it works for newer(?) steppings. */ + { .vendor = "Winbond", .name = "W29C010(M)/W29C011A/W29EE011/W29EE012", .bustype = BUS_PARALLEL, -- To view, visit https://review.coreboot.org/c/flashrom/+/33837 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Ie9a745b7e7dc752cfd6fc14ebeb04754179893c6 Gerrit-Change-Number: 33837 Gerrit-PatchSet: 1 Gerrit-Owner: Alan Green <avg(a)google.com> Gerrit-MessageType: newchange

3 4

Change in ...flashrom[master]: flashchips.c: Fix field order
by Alan Green (Code Review) 03 Jul '19

03 Jul '19

Alan Green has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/33833 Change subject: flashchips.c: Fix field order ...................................................................... flashchips.c: Fix field order For consistency and in order to allow automated tools to work with flashchips.c, put fields in the same order as they are defined in struct flashchip, in flash.h Signed-off-by: Alan Green <avg(a)google.com> Change-Id: I5e0d81cb71b2c50ffeb9bb70267f16e9ac7a263c --- M flashchips.c 1 file changed, 11 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/33/33833/1 diff --git a/flashchips.c b/flashchips.c index e73a4e3..8ea7043 100644 --- a/flashchips.c +++ b/flashchips.c @@ -2539,8 +2539,8 @@ .model_id = ATMEL_AT26F004, .total_size = 512, .page_size = 256, - .tested = {.probe = NT, .read = NT, .erase = NT, .write = BAD }, .feature_bits = FEATURE_WRSR_WREN, + .tested = {.probe = NT, .read = NT, .erase = NT, .write = BAD }, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, .block_erasers = @@ -2690,10 +2690,10 @@ } }, .printlock = spi_prettyprint_status_register_plain, - .gran = write_gran_1056bytes, .write = spi_write_at45db, .read = spi_read_at45db, .voltage = {2700, 3600}, + .gran = write_gran_1056bytes, }, { @@ -2943,10 +2943,10 @@ } }, .printlock = spi_prettyprint_status_register_at45db, /* Bit 0 is undefined, no lockdown */ - .gran = write_gran_528bytes, .write = spi_write_at45db, .read = spi_read_at45db_e8, /* 3 address and 4 dummy bytes */ .voltage = {2700, 3600}, + .gran = write_gran_528bytes, }, { @@ -2983,8 +2983,8 @@ .block_erase = spi_erase_at45db_chip, } }, - .unlock = spi_disable_blockprotect_at45db, /* Impossible if locked down or #WP is low */ .printlock = spi_prettyprint_status_register_at45db, + .unlock = spi_disable_blockprotect_at45db, /* Impossible if locked down or #WP is low */ /* granularity will be set by the probing function. */ .write = spi_write_at45db, .read = spi_read_at45db, /* Fast read (0x0B) supported */ @@ -3025,8 +3025,8 @@ .block_erase = spi_erase_at45db_chip, } }, - .unlock = spi_disable_blockprotect_at45db, /* Impossible if locked down or #WP is low */ .printlock = spi_prettyprint_status_register_at45db, /* has a 2nd status register */ + .unlock = spi_disable_blockprotect_at45db, /* Impossible if locked down or #WP is low */ /* granularity will be set by the probing function. */ .write = spi_write_at45db, .read = spi_read_at45db, /* Fast read (0x0B) supported */ @@ -3067,8 +3067,8 @@ .block_erase = spi_erase_at45db_chip, } }, - .unlock = spi_disable_blockprotect_at45db, /* Impossible if locked down or #WP is low */ .printlock = spi_prettyprint_status_register_at45db, + .unlock = spi_disable_blockprotect_at45db, /* Impossible if locked down or #WP is low */ /* granularity will be set by the probing function. */ .write = spi_write_at45db, .read = spi_read_at45db, /* Fast read (0x0B) supported */ @@ -3430,7 +3430,7 @@ .total_size = 64, .page_size = 0, /* unused */ .feature_bits = 0, - .tested = {.probe = OK, .read = OK, .erase = BAD, .write = BAD }, + .tested = { .probe = OK, .read = OK, .erase = BAD, .write = BAD }, .probe = probe_jedec, /* FIXME! */ .probe_timing = TIMING_ZERO, .block_erasers = @@ -3476,11 +3476,11 @@ .vendor = "ENE", .name = "KB9012 (EDI)", .bustype = BUS_SPI, - .spi_cmd_set = SPI_EDI, .total_size = 128, .page_size = 128, .feature_bits = FEATURE_ERASED_ZERO, .tested = TEST_OK_PREW, + .spi_cmd_set = SPI_EDI, .probe = edi_probe_kb9012, .probe_timing = TIMING_ZERO, .block_erasers = @@ -3490,10 +3490,10 @@ .block_erase = edi_chip_block_erase, }, }, - .gran = write_gran_128bytes, .write = edi_chip_write, .read = edi_chip_read, .voltage = {2700, 3600}, + .gran = write_gran_128bytes, }, { @@ -14930,8 +14930,8 @@ .block_erase = erase_block_82802ab, } }, - .write = write_82802ab, .unlock = unlock_regspace2_uniform_64k, + .write = write_82802ab, .read = read_memmapped, .voltage = {3000, 3600}, /* Also has 12V fast program & erase */ }, @@ -14963,8 +14963,8 @@ .block_erase = erase_block_82802ab, } }, - .write = write_82802ab, .unlock = unlock_regspace2_uniform_64k, + .write = write_82802ab, .read = read_memmapped, .voltage = {3000, 3600}, /* Also has 12V fast program & erase */ }, -- To view, visit https://review.coreboot.org/c/flashrom/+/33833 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I5e0d81cb71b2c50ffeb9bb70267f16e9ac7a263c Gerrit-Change-Number: 33833 Gerrit-PatchSet: 1 Gerrit-Owner: Alan Green <avg(a)google.com> Gerrit-MessageType: newchange

3 11

Change in ...flashrom[master]: flashchips.c: comma after very .voltage attribute
by Alan Green (Code Review) 03 Jul '19

03 Jul '19

Alan Green has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/33832 Change subject: flashchips.c: comma after very .voltage attribute ...................................................................... flashchips.c: comma after very .voltage attribute To allow automated tools to manipulate flashchips.c, ensure that every voltage attribute ends with a comma, even if it is the last member in the definition. Signed-off-by: Alan Green <avg(a)google.com> Change-Id: Ie609d11ab846361f375f7b024d6ca55f83b01682 --- M flashchips.c 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/32/33832/1 diff --git a/flashchips.c b/flashchips.c index 7f3d2a2..e73a4e3 100644 --- a/flashchips.c +++ b/flashchips.c @@ -525,7 +525,7 @@ }, .write = write_jedec_1, .read = read_memmapped, - .voltage = {3000, 3600} /* 3.0-3.6V for type -70R, others 2.7-3.6V */ + .voltage = {3000, 3600}, /* 3.0-3.6V for type -70R, others 2.7-3.6V */ }, { @@ -557,7 +557,7 @@ }, .write = write_jedec_1, .read = read_memmapped, - .voltage = {3000, 3600} /* 3.0-3.6V for type -70R, others 2.7-3.6V */ + .voltage = {3000, 3600}, /* 3.0-3.6V for type -70R, others 2.7-3.6V */ }, { -- To view, visit https://review.coreboot.org/c/flashrom/+/33832 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Ie609d11ab846361f375f7b024d6ca55f83b01682 Gerrit-Change-Number: 33832 Gerrit-PatchSet: 1 Gerrit-Owner: Alan Green <avg(a)google.com> Gerrit-MessageType: newchange

4 7

Change in ...flashrom[master]: flashchips.c: format block_erasers members
by Alan Green (Code Review) 03 Jul '19

03 Jul '19

Alan Green has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/33831 Change subject: flashchips.c: format block_erasers members ...................................................................... flashchips.c: format block_erasers members To allow automated tools to manipulate flashchips.c, ensure all .block_erasers definitions have consistent formatting: - start with the opening brace on a new line. - ensure end brace indented exactly two tabs. SFDP-capable chip is the one exception to this rule as it has an empty block instead. Signed-off-by: Alan Green <avg(a)google.com> Change-Id: Ib168bdbbef4cf097109805de15c97ecc1f7915b3 --- M flashchips.c 1 file changed, 106 insertions(+), 56 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/31/33831/1 diff --git a/flashchips.c b/flashchips.c index 1796127..7f3d2a2 100644 --- a/flashchips.c +++ b/flashchips.c @@ -1253,7 +1253,8 @@ .tested = TEST_UNTESTED, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, - .block_erasers = { + .block_erasers = + { { .eraseblocks = { { 4 * 1024, 512 } }, .block_erase = spi_block_erase_20, @@ -2510,7 +2511,8 @@ }, /*The AT26DF321 has the same ID as the AT25DF321. */ - /*{ +#if 0 + { .vendor = "Atmel", .name = "AT26DF321", .bustype = BUS_SPI, @@ -2526,7 +2528,8 @@ .unlock = spi_disable_blockprotect, .write = spi_chip_write_256, .read = spi_chip_read, - },*/ + }, +#endif { .vendor = "Atmel", @@ -4991,7 +4994,8 @@ .tested = TEST_OK_PREW, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, - .block_erasers = { + .block_erasers = + { { .eraseblocks = { {4 * 1024, 2048} }, .block_erase = spi_block_erase_20, @@ -5028,7 +5032,8 @@ .tested = TEST_UNTESTED, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, - .block_erasers = { + .block_erasers = + { { .eraseblocks = { {4 * 1024, 4096} }, .block_erase = spi_block_erase_20, @@ -5063,7 +5068,8 @@ .tested = TEST_UNTESTED, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, - .block_erasers = { + .block_erasers = + { { .eraseblocks = { {4 * 1024, 32} }, .block_erase = spi_block_erase_20, @@ -5098,7 +5104,8 @@ .tested = TEST_UNTESTED, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, - .block_erasers = { + .block_erasers = + { { .eraseblocks = { {4 * 1024, 64} }, .block_erase = spi_block_erase_20, @@ -5133,7 +5140,8 @@ .tested = TEST_OK_PREW, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, - .block_erasers = { + .block_erasers = + { { .eraseblocks = { {4 * 1024, 128} }, .block_erase = spi_block_erase_20, @@ -5168,7 +5176,8 @@ .tested = TEST_UNTESTED, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, - .block_erasers = { + .block_erasers = + { { .eraseblocks = { {4 * 1024, 256} }, .block_erase = spi_block_erase_20, @@ -5203,7 +5212,8 @@ .tested = TEST_UNTESTED, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, - .block_erasers = { + .block_erasers = + { { .eraseblocks = { {4 * 1024, 512} }, .block_erase = spi_block_erase_20, @@ -5241,7 +5251,8 @@ .tested = TEST_UNTESTED, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, - .block_erasers = { + .block_erasers = + { { .eraseblocks = { {4 * 1024, 1024} }, .block_erase = spi_block_erase_20, @@ -5279,7 +5290,8 @@ .tested = TEST_UNTESTED, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, - .block_erasers = { + .block_erasers = + { { .eraseblocks = { {4 * 1024, 2048} }, .block_erase = spi_block_erase_20, @@ -6096,7 +6108,8 @@ .tested = TEST_OK_PREW, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, - .block_erasers = { + .block_erasers = + { { .eraseblocks = { {4 * 1024, 16} }, .block_erase = spi_block_erase_20, @@ -6130,7 +6143,8 @@ .tested = TEST_UNTESTED, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, - .block_erasers = { + .block_erasers = + { { .eraseblocks = { {4 * 1024, 32} }, .block_erase = spi_block_erase_20, @@ -6480,7 +6494,8 @@ .tested = TEST_UNTESTED, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, - .block_erasers = { + .block_erasers = + { { .eraseblocks = { {4 * 1024, 256} }, .block_erase = spi_block_erase_20, @@ -9996,7 +10011,8 @@ .tested = TEST_OK_PREW, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, - .block_erasers = { + .block_erasers = + { { .eraseblocks = { { 4 * 1024, 256 } }, .block_erase = spi_block_erase_20, @@ -10125,7 +10141,8 @@ .tested = TEST_UNTESTED, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, - .block_erasers = { + .block_erasers = + { { .eraseblocks = { {256, 512} }, .block_erase = spi_block_erase_db, @@ -10152,7 +10169,8 @@ .tested = TEST_UNTESTED, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, - .block_erasers = { + .block_erasers = + { { .eraseblocks = { {256, 1024} }, .block_erase = spi_block_erase_db, @@ -10179,7 +10197,8 @@ .tested = TEST_UNTESTED, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, - .block_erasers = { + .block_erasers = + { { .eraseblocks = { {256, 2048} }, .block_erase = spi_block_erase_db, @@ -10206,7 +10225,8 @@ .tested = TEST_UNTESTED, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, - .block_erasers = { + .block_erasers = + { { .eraseblocks = { {256, 4096} }, .block_erase = spi_block_erase_db, @@ -10233,7 +10253,8 @@ .tested = TEST_UNTESTED, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, - .block_erasers = { + .block_erasers = + { { .eraseblocks = { {256, 8192} }, .block_erase = spi_block_erase_db, @@ -10436,7 +10457,8 @@ .tested = TEST_OK_PREW, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, - .block_erasers = { + .block_erasers = + { { .eraseblocks = { {4 * 1024, 4096 } }, .block_erase = spi_block_erase_20, @@ -10469,7 +10491,8 @@ .tested = TEST_OK_PREW, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, - .block_erasers = { + .block_erasers = + { { .eraseblocks = { {4 * 1024, 4096 } }, .block_erase = spi_block_erase_20, @@ -10502,7 +10525,8 @@ .tested = TEST_UNTESTED, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, - .block_erasers = { + .block_erasers = + { { .eraseblocks = { {4 * 1024, 8192} }, .block_erase = spi_block_erase_21, @@ -10541,7 +10565,8 @@ .tested = TEST_OK_PREW, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, - .block_erasers = { + .block_erasers = + { { .eraseblocks = { {4 * 1024, 16384} }, .block_erase = spi_block_erase_21, @@ -11830,7 +11855,8 @@ .tested = TEST_OK_PREW, .probe = probe_spi_res2, .probe_timing = TIMING_ZERO, - .block_erasers = { + .block_erasers = + { { .eraseblocks = { {2 * 1024, 64} }, .block_erase = spi_block_erase_d7, @@ -11861,7 +11887,8 @@ .tested = TEST_OK_PREW, .probe = probe_spi_res2, .probe_timing = TIMING_ZERO, - .block_erasers = { + .block_erasers = + { { .eraseblocks = { {4 * 1024, 128} }, .block_erase = spi_block_erase_d7, @@ -11871,8 +11898,8 @@ }, { .eraseblocks = { {512 * 1024, 1} }, .block_erase = spi_block_erase_c7, - } - }, + } + }, .printlock = spi_prettyprint_status_register_plain, .unlock = spi_disable_blockprotect, .write = spi_chip_write_256, @@ -11892,7 +11919,8 @@ .tested = TEST_UNTESTED, .probe = probe_spi_res2, .probe_timing = TIMING_ZERO, - .block_erasers = { + .block_erasers = + { /* FIXME: Is this correct? { .eraseblocks = { {2 * 1024, 64} }, @@ -11925,7 +11953,8 @@ .tested = TEST_UNTESTED, .probe = probe_spi_res2, .probe_timing = TIMING_ZERO, - .block_erasers = { + .block_erasers = + { { .eraseblocks = { {4 * 1024, 64} }, .block_erase = spi_block_erase_d7, @@ -11955,7 +11984,8 @@ .tested = TEST_UNTESTED, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, - .block_erasers = { + .block_erasers = + { { .eraseblocks = { {4 * 1024, 64} }, .block_erase = spi_block_erase_20, @@ -11992,7 +12022,8 @@ .tested = TEST_OK_PREW, .probe = probe_spi_res2, .probe_timing = TIMING_ZERO, - .block_erasers = { + .block_erasers = + { { .eraseblocks = { {4 * 1024, 128} }, .block_erase = spi_block_erase_d7, @@ -12003,7 +12034,7 @@ .eraseblocks = { {512 * 1024, 1} }, .block_erase = spi_block_erase_c7, } - }, + }, .printlock = spi_prettyprint_status_register_bp2_srwd, .unlock = spi_disable_blockprotect, /* #WP pin write-protects SRWP bit. */ .write = spi_chip_write_256, @@ -12023,7 +12054,8 @@ .tested = TEST_OK_PREW, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, - .block_erasers = { + .block_erasers = + { { .eraseblocks = { {4 * 1024, 128} }, .block_erase = spi_block_erase_20, @@ -12040,7 +12072,7 @@ .eraseblocks = { {512 * 1024, 1} }, .block_erase = spi_block_erase_c7, } - }, + }, .printlock = spi_prettyprint_status_register_bp2_srwd, .unlock = spi_disable_blockprotect_bp2_srwd, .write = spi_chip_write_256, @@ -12090,7 +12122,8 @@ .tested = TEST_UNTESTED, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, - .block_erasers = { + .block_erasers = + { { .eraseblocks = { {256, 2 * 1024} }, .block_erase = spi_block_erase_db, @@ -12121,7 +12154,8 @@ .tested = TEST_UNTESTED, .probe = probe_spi_res2, .probe_timing = TIMING_ZERO, - .block_erasers = { + .block_erasers = + { { .eraseblocks = { {4 * 1024, 128} }, .block_erase = spi_block_erase_d7, @@ -12131,8 +12165,8 @@ }, { .eraseblocks = { {512 * 1024, 1} }, .block_erase = spi_block_erase_c7, - } - }, + } + }, .printlock = spi_prettyprint_status_register_bp2_srwd, .unlock = spi_disable_blockprotect, /* #WP pin write-protects SRWP bit. */ .write = spi_chip_write_256, @@ -12152,7 +12186,8 @@ .tested = TEST_UNTESTED, .probe = probe_spi_res2, .probe_timing = TIMING_ZERO, - .block_erasers = { + .block_erasers = + { { .eraseblocks = { {4 * 1024, 256} }, .block_erase = spi_block_erase_20, @@ -12186,7 +12221,8 @@ .tested = TEST_UNTESTED, .probe = probe_spi_res2, .probe_timing = TIMING_ZERO, - .block_erasers = { + .block_erasers = + { { .eraseblocks = { {8 * 1024, 128} }, .block_erase = spi_block_erase_d7, @@ -12425,7 +12461,8 @@ .tested = TEST_OK_PR, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, - .block_erasers = { + .block_erasers = + { { .eraseblocks = { {4 * 1024, 128} }, .block_erase = spi_block_erase_20, @@ -12459,7 +12496,8 @@ .tested = TEST_OK_PREW, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, - .block_erasers = { + .block_erasers = + { { .eraseblocks = { {4 * 1024, 256} }, .block_erase = spi_block_erase_20, @@ -12494,7 +12532,8 @@ .tested = TEST_UNTESTED, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, - .block_erasers = { + .block_erasers = + { { .eraseblocks = { {4 * 1024, 512} }, .block_erase = spi_block_erase_20, @@ -12529,7 +12568,8 @@ .tested = TEST_UNTESTED, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, - .block_erasers = { + .block_erasers = + { { .eraseblocks = { {4 * 1024, 1024} }, .block_erase = spi_block_erase_20, @@ -12564,7 +12604,8 @@ .tested = TEST_OK_PREW, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, - .block_erasers = { + .block_erasers = + { { .eraseblocks = { {4 * 1024, 2048} }, .block_erase = spi_block_erase_20, @@ -12601,7 +12642,8 @@ /* FIXME: we should distinguish the configuration on probing time like we do for AT45DB chips */ .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, - .block_erasers = { + .block_erasers = + { { /* This chip supports erasing of 32 so-called "parameter sectors" with * opcode 0x20 which may be configured to be on top or bottom of the address @@ -12644,7 +12686,8 @@ .tested = TEST_UNTESTED, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, - .block_erasers = { + .block_erasers = + { { .eraseblocks = { {256 * 1024, 64} }, .block_erase = spi_block_erase_d8, @@ -12675,7 +12718,8 @@ .tested = TEST_OK_PREW, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, - .block_erasers = { + .block_erasers = + { { .eraseblocks = { {64 * 1024, 256} }, .block_erase = spi_block_erase_20, @@ -12709,7 +12753,8 @@ .tested = TEST_UNTESTED, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, - .block_erasers = { + .block_erasers = + { { .eraseblocks = { {256 * 1024, 64} }, .block_erase = spi_block_erase_d8, @@ -12739,7 +12784,8 @@ .tested = TEST_OK_PREW, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, - .block_erasers = { + .block_erasers = + { { /* This chip supports erasing of the 32 so-called "parameter sectors" with * opcode 0x20. Trying to access an address outside these 4kB blocks does @@ -12781,7 +12827,8 @@ .tested = TEST_UNTESTED, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, - .block_erasers = { + .block_erasers = + { { .eraseblocks = { {256 * 1024, 64} }, .block_erase = spi_block_erase_d8, @@ -12813,7 +12860,8 @@ .tested = TEST_OK_PREW, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, - .block_erasers = { + .block_erasers = + { { /* FIXME: This chip supports erasing of the 32 so-called "parameter sectors" with * opcode 0x20. Trying to access an address outside these 4kB blocks does have no @@ -12861,7 +12909,8 @@ .tested = TEST_UNTESTED, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, - .block_erasers = { + .block_erasers = + { { .eraseblocks = { {256 * 1024, 64} }, .block_erase = spi_block_erase_d8, @@ -12893,7 +12942,8 @@ .tested = TEST_OK_PREW, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, - .block_erasers = { + .block_erasers = + { { /* This chip supports erasing of the 32 so-called "parameter sectors" with * opcode 0x20. Trying to access an address outside these 4kB blocks does -- To view, visit https://review.coreboot.org/c/flashrom/+/33831 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Ib168bdbbef4cf097109805de15c97ecc1f7915b3 Gerrit-Change-Number: 33831 Gerrit-PatchSet: 1 Gerrit-Owner: Alan Green <avg(a)google.com> Gerrit-MessageType: newchange

3 9

Change in ...flashrom[master]: flashchips.c: end of line comment consistency
by Alan Green (Code Review) 02 Jul '19

02 Jul '19

Alan Green has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/33830 Change subject: flashchips.c: end of line comment consistency ...................................................................... flashchips.c: end of line comment consistency To allow automated tools to manipulate flashchips.c, make end of line comment formatting more consistent. Specifically this change moves the comma from end of line to immediately after the field value, before the commment. Signed-off-by: Alan Green <avg(a)google.com> Change-Id: Ic4f97454766eff640b26a6c6eca29dc56c34c444 --- M flashchips.c 1 file changed, 26 insertions(+), 26 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/30/33830/1 diff --git a/flashchips.c b/flashchips.c index 88648ad..1796127 100644 --- a/flashchips.c +++ b/flashchips.c @@ -2560,7 +2560,7 @@ } }, .printlock = spi_prettyprint_status_register_plain, /* TODO: improve */ - .write = NULL /* Incompatible Page write */, + .write = NULL, /* Incompatible Page write */ .read = spi_chip_read, .voltage = {2700, 3600}, }, @@ -2667,8 +2667,8 @@ .bustype = BUS_SPI, .manufacture_id = ATMEL_ID, .model_id = ATMEL_AT45CS1282, - .total_size = 16896 /* No power of two sizes */, - .page_size = 1056 /* No power of two sizes */, + .total_size = 16896, /* No power of two sizes */ + .page_size = 1056, /* No power of two sizes */ /* does not support EWSR nor WREN and has no writable status register bits whatsoever */ /* OTP: 128B total, 64B pre-programmed; read 0x77 (4 dummy bytes); write 0x9A (via buffer) */ .feature_bits = FEATURE_OTP, @@ -2699,8 +2699,8 @@ .bustype = BUS_SPI, .manufacture_id = ATMEL_ID, .model_id = ATMEL_AT45DB011D, - .total_size = 128 /* or 132, determined from status register */, - .page_size = 256 /* or 264, determined from status register */, + .total_size = 128, /* or 132, determined from status register */ + .page_size = 256, /* or 264, determined from status register */ /* does not support EWSR nor WREN and has no writable status register bits whatsoever */ /* OTP: 128B total, 64B pre-programmed; read 0x77; write 0x9B */ .feature_bits = FEATURE_OTP, @@ -2727,8 +2727,8 @@ .block_erase = spi_erase_at45db_chip, } }, - .unlock = spi_disable_blockprotect_at45db, /* Impossible if locked down or #WP is low */ .printlock = spi_prettyprint_status_register_at45db, + .unlock = spi_disable_blockprotect_at45db, /* Impossible if locked down or #WP is low */ /* granularity will be set by the probing function. */ .write = spi_write_at45db, .read = spi_read_at45db, /* Fast read (0x0B) supported */ @@ -2741,8 +2741,8 @@ .bustype = BUS_SPI, .manufacture_id = ATMEL_ID, .model_id = ATMEL_AT45DB021D, - .total_size = 256 /* or 264, determined from status register */, - .page_size = 256 /* or 264, determined from status register */, + .total_size = 256, /* or 264, determined from status register */ + .page_size = 256, /* or 264, determined from status register */ /* does not support EWSR nor WREN and has no writable status register bits whatsoever */ /* OTP: 128B total, 64B pre-programmed; read 0x77; write 0x9B */ .feature_bits = FEATURE_OTP, @@ -2769,8 +2769,8 @@ .block_erase = spi_erase_at45db_chip, } }, - .unlock = spi_disable_blockprotect_at45db, /* Impossible if locked down or #WP is low */ .printlock = spi_prettyprint_status_register_at45db, + .unlock = spi_disable_blockprotect_at45db, /* Impossible if locked down or #WP is low */ /* granularity will be set by the probing function. */ .write = spi_write_at45db, .read = spi_read_at45db, /* Fast read (0x0B) supported */ @@ -2783,8 +2783,8 @@ .bustype = BUS_SPI, .manufacture_id = ATMEL_ID, .model_id = ATMEL_AT45DB041D, - .total_size = 512 /* or 528, determined from status register */, - .page_size = 256 /* or 264, determined from status register */, + .total_size = 512, /* or 528, determined from status register */ + .page_size = 256, /* or 264, determined from status register */ /* does not support EWSR nor WREN and has no writable status register bits whatsoever */ /* OTP: 128B total, 64B pre-programmed; read 0x77; write 0x9B */ .feature_bits = FEATURE_OTP, @@ -2811,8 +2811,8 @@ .block_erase = spi_erase_at45db_chip, } }, - .unlock = spi_disable_blockprotect_at45db, /* Impossible if locked down or #WP is low */ .printlock = spi_prettyprint_status_register_at45db, + .unlock = spi_disable_blockprotect_at45db, /* Impossible if locked down or #WP is low */ /* granularity will be set by the probing function. */ .write = spi_write_at45db, .read = spi_read_at45db, /* Fast read (0x0B) supported */ @@ -2825,8 +2825,8 @@ .bustype = BUS_SPI, .manufacture_id = ATMEL_ID, .model_id = ATMEL_AT45DB081D, - .total_size = 1024 /* or 1056, determined from status register */, - .page_size = 256 /* or 264, determined from status register */, + .total_size = 1024, /* or 1056, determined from status register */ + .page_size = 256, /* or 264, determined from status register */ /* does not support EWSR nor WREN and has no writable status register bits whatsoever */ /* OTP: 128B total, 64B pre-programmed; read 0x77; write 0x9B */ .feature_bits = FEATURE_OTP, @@ -2853,8 +2853,8 @@ .block_erase = spi_erase_at45db_chip, } }, - .unlock = spi_disable_blockprotect_at45db, /* Impossible if locked down or #WP is low */ .printlock = spi_prettyprint_status_register_at45db, + .unlock = spi_disable_blockprotect_at45db, /* Impossible if locked down or #WP is low */ /* granularity will be set by the probing function. */ .write = spi_write_at45db, .read = spi_read_at45db, /* Fast read (0x0B) supported */ @@ -2867,8 +2867,8 @@ .bustype = BUS_SPI, .manufacture_id = ATMEL_ID, .model_id = ATMEL_AT45DB161D, - .total_size = 2048 /* or 2112, determined from status register */, - .page_size = 512 /* or 528, determined from status register */, + .total_size = 2048, /* or 2112, determined from status register */ + .page_size = 512, /* or 528, determined from status register */ /* does not support EWSR nor WREN and has no writable status register bits whatsoever */ /* OTP: 128B total, 64B pre-programmed; read 0x77; write 0x9B */ .feature_bits = FEATURE_OTP, @@ -2895,8 +2895,8 @@ .block_erase = spi_erase_at45db_chip, } }, - .unlock = spi_disable_blockprotect_at45db, /* Impossible if locked down or #WP is low */ .printlock = spi_prettyprint_status_register_at45db, + .unlock = spi_disable_blockprotect_at45db, /* Impossible if locked down or #WP is low */ /* granularity will be set by the probing function. */ .write = spi_write_at45db, .read = spi_read_at45db, /* Fast read (0x0B) supported */ @@ -2909,8 +2909,8 @@ .bustype = BUS_SPI, .manufacture_id = ATMEL_ID, .model_id = ATMEL_AT45DB321C, - .total_size = 4224 /* No power of two sizes */, - .page_size = 528 /* No power of two sizes */, + .total_size = 4224, /* No power of two sizes */ + .page_size = 528, /* No power of two sizes */ /* does not support EWSR nor WREN and has no writable status register bits whatsoever */ /* OTP: 128B total, 64B pre-programmed; read 0x77 (4 dummy bytes); write 0x9A (via buffer) */ .feature_bits = FEATURE_OTP, @@ -2952,8 +2952,8 @@ .bustype = BUS_SPI, .manufacture_id = ATMEL_ID, .model_id = ATMEL_AT45DB321D, - .total_size = 4096 /* or 4224, determined from status register */, - .page_size = 512 /* or 528, determined from status register */, + .total_size = 4096, /* or 4224, determined from status register */ + .page_size = 512, /* or 528, determined from status register */ /* does not support EWSR nor WREN and has no writable status register bits whatsoever */ /* OTP: 128B total, 64B pre-programmed; read 0x77; write 0x9B */ .feature_bits = FEATURE_OTP, @@ -2994,8 +2994,8 @@ .bustype = BUS_SPI, .manufacture_id = ATMEL_ID, .model_id = ATMEL_AT45DB321C, - .total_size = 4096 /* or 4224, determined from status register */, - .page_size = 512 /* or 528, determined from status register */, + .total_size = 4096, /* or 4224, determined from status register */ + .page_size = 512, /* or 528, determined from status register */ /* does not support EWSR nor WREN and has no writable status register bits whatsoever */ /* OTP: 128B total, 64B pre-programmed; read 0x77; write 0x9B */ .feature_bits = FEATURE_OTP, @@ -3036,8 +3036,8 @@ .bustype = BUS_SPI, .manufacture_id = ATMEL_ID, .model_id = ATMEL_AT45DB642D, - .total_size = 8192 /* or 8448, determined from status register */, - .page_size = 1024 /* or 1056, determined from status register */, + .total_size = 8192, /* or 8448, determined from status register */ + .page_size = 1024, /* or 1056, determined from status register */ /* does not support EWSR nor WREN and has no writable status register bits whatsoever */ /* OTP: 128B total, 64B pre-programmed; read 0x77; write 0x9B */ .feature_bits = FEATURE_OTP, -- To view, visit https://review.coreboot.org/c/flashrom/+/33830 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Ic4f97454766eff640b26a6c6eca29dc56c34c444 Gerrit-Change-Number: 33830 Gerrit-PatchSet: 1 Gerrit-Owner: Alan Green <avg(a)google.com> Gerrit-MessageType: newchange

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