May 2019 - flashrom-gerrit - mail.coreboot.org

Change in ...flashrom[master]: Add support for security register and SBULK command on Macronix chips
by vl_sk (Code Review) 03 Aug '19

03 Aug '19

vl_sk has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/32034 Change subject: Add support for security register and SBULK command on Macronix chips ...................................................................... Add support for security register and SBULK command on Macronix chips Signed-off-by: Vladimir Skokov <vl_sk(a)mail.ru> Change-Id: I6b3d7bd2625dec5fda7b85f421d40c49bbc528a6 --- M chipdrivers.h M flashchips.c M spi.h M spi25_statusreg.c 4 files changed, 78 insertions(+), 24 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/34/32034/1 diff --git a/chipdrivers.h b/chipdrivers.h index 134ed26..54288cd 100644 --- a/chipdrivers.h +++ b/chipdrivers.h @@ -102,7 +102,9 @@ int spi_prettyprint_status_register_sst25(struct flashctx *flash); int spi_prettyprint_status_register_sst25vf016(struct flashctx *flash); int spi_prettyprint_status_register_sst25vf040b(struct flashctx *flash); +int spi_prettyprint_security_register_mx25(struct flashctx *flash); int spi_disable_blockprotect_sst26_global_unprotect(struct flashctx *flash); +int spi_disable_blockprotect_mx25_global_unprotect(struct flashctx *flash); /* sfdp.c */ int probe_spi_sfdp(struct flashctx *flash); diff --git a/flashchips.c b/flashchips.c index d85ea74..2c662e9 100644 --- a/flashchips.c +++ b/flashchips.c @@ -8555,9 +8555,8 @@ .block_erase = spi_block_erase_c7, } }, - /* TODO: security register and SBLK/SBULK; MX25L12835F: configuration register */ - .printlock = spi_prettyprint_status_register_bp3_srwd, /* bit6 is quad enable */ - .unlock = spi_disable_blockprotect_bp3_srwd, + .printlock = spi_prettyprint_security_register_mx25, + .unlock = spi_disable_blockprotect_mx25_global_unprotect, .write = spi_chip_write_256, .read = spi_chip_read, /* Fast read (0x0B) supported */ .voltage = {2700, 3600}, @@ -8604,9 +8603,8 @@ .block_erase = spi_block_erase_c7, } }, - /* TODO: security register and SBLK/SBULK; MX25L12835F: configuration register */ - .printlock = spi_prettyprint_status_register_bp3_srwd, /* bit6 is quad enable */ - .unlock = spi_disable_blockprotect_bp3_srwd, + .printlock = spi_prettyprint_security_register_mx25, + .unlock = spi_disable_blockprotect_mx25_global_unprotect, .write = spi_chip_write_256, .read = spi_chip_read, /* Fast read (0x0B) supported */ .voltage = {2700, 3600}, @@ -8693,9 +8691,8 @@ .block_erase = spi_block_erase_c7, } }, - /* TODO: security register */ - .printlock = spi_prettyprint_status_register_bp3_srwd, /* bit6 is quad enable */ - .unlock = spi_disable_blockprotect_bp3_srwd, + .printlock = spi_prettyprint_security_register_mx25, + .unlock = spi_disable_blockprotect_mx25_global_unprotect, .write = spi_chip_write_256, .read = spi_chip_read, /* Fast read (0x0B) and multi I/O supported */ .voltage = {1650, 2000}, @@ -8734,9 +8731,8 @@ .block_erase = spi_block_erase_c7, } }, - /* TODO: security register */ - .printlock = spi_prettyprint_status_register_bp3_srwd, /* bit6 is quad enable */ - .unlock = spi_disable_blockprotect_bp3_srwd, + .printlock = spi_prettyprint_security_register_mx25, + .unlock = spi_disable_blockprotect_mx25_global_unprotect, .write = spi_chip_write_256, .read = spi_chip_read, /* Fast read (0x0B) and multi I/O supported */ .voltage = {1650, 2000}, @@ -8776,9 +8772,8 @@ .block_erase = spi_block_erase_c7, } }, - /* TODO: security register */ - .printlock = spi_prettyprint_status_register_bp3_srwd, /* bit6 is quad enable */ - .unlock = spi_disable_blockprotect_bp3_srwd, + .printlock = spi_prettyprint_security_register_mx25, + .unlock = spi_disable_blockprotect_mx25_global_unprotect, .write = spi_chip_write_256, .read = spi_chip_read, /* Fast read (0x0B) and multi I/O supported */ .voltage = {1650, 2000}, @@ -8818,9 +8813,8 @@ .block_erase = spi_block_erase_c7, } }, - /* TODO: security register */ - .printlock = spi_prettyprint_status_register_bp3_srwd, /* bit6 is quad enable */ - .unlock = spi_disable_blockprotect_bp3_srwd, + .printlock = spi_prettyprint_security_register_mx25, + .unlock = spi_disable_blockprotect_mx25_global_unprotect, .write = spi_chip_write_256, .read = spi_chip_read, /* Fast read (0x0B) and multi I/O supported */ .voltage = {1650, 2000}, @@ -8858,9 +8852,8 @@ .block_erase = spi_block_erase_c7, } }, - /* TODO: security register */ - .printlock = spi_prettyprint_status_register_bp3_srwd, /* bit6 is quad enable */ - .unlock = spi_disable_blockprotect_bp3_srwd, + .printlock = spi_prettyprint_security_register_mx25, + .unlock = spi_disable_blockprotect_mx25_global_unprotect, .write = spi_chip_write_256, /* Multi I/O supported */ .read = spi_chip_read, /* Fast read (0x0B) and multi I/O supported */ .voltage = {1650, 2000}, @@ -8907,9 +8900,8 @@ .block_erase = spi_block_erase_c7, } }, - /* TODO: security register */ - .printlock = spi_prettyprint_status_register_bp3_srwd, /* bit6 is quad enable */ - .unlock = spi_disable_blockprotect_bp3_srwd, + .printlock = spi_prettyprint_security_register_mx25, + .unlock = spi_disable_blockprotect_mx25_global_unprotect, .write = spi_chip_write_256, /* Multi I/O supported */ .read = spi_chip_read, /* Fast read (0x0B) and multi I/O supported */ .voltage = {1650, 2000}, diff --git a/spi.h b/spi.h index 422e6a0..456d894 100644 --- a/spi.h +++ b/spi.h @@ -170,6 +170,15 @@ From ANY mode (3-bytes or 4-bytes) it works with 4-byte address */ #define JEDEC_BYTE_PROGRAM_4BA 0x12 +/* Read Security Register */ +#define JEDEC_RDSCUR 0x2B +#define JEDEC_RDSCUR_OUTSIZE 0x01 +#define JEDEC_RDSCUR_INSIZE 0x01 + +/* Do GBULK (gang block unlock) */ +#define JEDEC_GBULK 0x98 +#define JEDEC_GBULK_OUTSIZE 0x01 + /* Error codes */ #define SPI_GENERIC_ERROR -1 #define SPI_INVALID_OPCODE -2 diff --git a/spi25_statusreg.c b/spi25_statusreg.c index 4cf7023..4cdf800 100644 --- a/spi25_statusreg.c +++ b/spi25_statusreg.c @@ -237,6 +237,28 @@ return spi_disable_blockprotect_generic(flash, 0x7C, 1 << 7, 0, 0xFF); } +int spi_disable_blockprotect_mx25_global_unprotect(struct flashctx *flash) +{ + static const unsigned char cmd[JEDEC_GBULK_OUTSIZE] = { JEDEC_GBULK }; + int ret; + + ret = spi_write_enable(flash); + if (ret) { + msg_cerr("Set WREN failed!\n"); + return -1; + } + + /* Send GBULK cmd to device. */ + ret = spi_send_command(flash, sizeof(cmd), 0, cmd, NULL); + if (ret) { + msg_cerr("GBULK failed!\n"); + return -1; + } + + /* Disable standard blockprotect */ + return spi_disable_blockprotect_bp3_srwd(flash); +} + static void spi_prettyprint_status_register_hex(uint8_t status) { msg_cdbg("Chip status register is 0x%02x.\n", status); @@ -751,3 +773,32 @@ msg_cdbg("Resulting block protection : %s\n", bpt[(status & 0x1c) >> 2]); return 0; } + +/* === Macronix chips with Security Register === */ + +int spi_read_security_register(struct flashctx *flash) +{ + static const unsigned char cmd[JEDEC_RDSCUR_OUTSIZE] = { JEDEC_RDSCUR }; + unsigned char readarr[JEDEC_RDSCUR_INSIZE]; + int ret; + + ret = spi_send_command(flash, sizeof(cmd), sizeof(readarr), cmd, readarr); + if (ret) { + msg_cerr("RDSCUR failed!\n"); + return 0; + } + + return readarr[0]; +} + +int spi_prettyprint_security_register_mx25(struct flashctx *flash) +{ + int security_register = spi_read_security_register(flash); + int wpsel = !!(security_register & (1 << 7)); + + msg_cdbg("Chip security register: 0x%02X\n", security_register); + msg_cdbg("\tWPSEL is %s\n", wpsel ? "ON" : "OFF"); + + /* Print standard blockprotect info */ + return spi_prettyprint_status_register_bp3_srwd(flash); +} \ No newline at end of file -- To view, visit https://review.coreboot.org/c/flashrom/+/32034 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I6b3d7bd2625dec5fda7b85f421d40c49bbc528a6 Gerrit-Change-Number: 32034 Gerrit-PatchSet: 1 Gerrit-Owner: vl_sk Gerrit-MessageType: newchange

3 5

Change in ...flashrom[master]: [WIP] picki2_spi: update to libusb1 and drop libusb0 dependence
by Thomas Heijligen (Code Review) 10 Jul '19

10 Jul '19

Thomas Heijligen has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/32213 Change subject: [WIP] picki2_spi: update to libusb1 and drop libusb0 dependence ...................................................................... [WIP] picki2_spi: update to libusb1 and drop libusb0 dependence Change-Id: Icfc5372aa1789d35ed22d68297d5e68a74d40388 Signed-off-by: Thomas Heijligen <thomas.heijligen(a)secunet.com> --- M Makefile M meson.build M meson_options.txt M pickit2_spi.c 4 files changed, 50 insertions(+), 130 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/13/32213/1 diff --git a/Makefile b/Makefile index 1e7db3e..9d6123a 100644 --- a/Makefile +++ b/Makefile @@ -679,15 +679,12 @@ $(eval $(var)=yes))) endif -# Disable feature groups -ifeq ($(CONFIG_ENABLE_LIBUSB0_PROGRAMMERS), no) -override CONFIG_PICKIT2_SPI = no -endif ifeq ($(CONFIG_ENABLE_LIBUSB1_PROGRAMMERS), no) override CONFIG_CH341A_SPI = no override CONFIG_DEDIPROG = no override CONFIG_DIGILENT_SPI = no override CONFIG_DEVELOPERBOX_SPI = no +override CONFIG_PICKIT2_SPI = no endif ifeq ($(CONFIG_ENABLE_LIBPCI_PROGRAMMERS), no) override CONFIG_INTERNAL = no @@ -852,7 +849,7 @@ ifeq ($(CONFIG_PICKIT2_SPI), yes) FEATURE_CFLAGS += -D'CONFIG_PICKIT2_SPI=1' PROGRAMMER_OBJS += pickit2_spi.o -NEED_LIBUSB0 += CONFIG_PICKIT2_SPI +NEED_LIBUSB1 += CONFIG_PICKIT2_SPI endif ifneq ($(NEED_LIBFTDI), ) @@ -1023,11 +1020,6 @@ endif -ifneq ($(NEED_LIBUSB0), ) -CHECK_LIBUSB0 = yes -FEATURE_CFLAGS += -D'NEED_LIBUSB0=1' -USBLIBS := $(call debug_shell,[ -n "$(PKG_CONFIG_LIBDIR)" ] && export PKG_CONFIG_LIBDIR="$(PKG_CONFIG_LIBDIR)" ; $(PKG_CONFIG) --libs libusb || printf "%s" "-lusb") -endif ifneq ($(NEED_LIBUSB1), ) CHECK_LIBUSB1 = yes @@ -1179,23 +1171,6 @@ endef export PCI_GET_DEV_TEST -define LIBUSB0_TEST -#include "platform.h" -#if IS_WINDOWS -#include <lusb0_usb.h> -#else -#include <usb.h> -#endif -int main(int argc, char **argv) -{ - (void) argc; - (void) argv; - usb_init(); - return 0; -} -endef -export LIBUSB0_TEST - define LIBUSB1_TEST #include <stddef.h> #include <libusb.h> @@ -1261,28 +1236,6 @@ rm -f .test.c .test.o .test$(EXEC_SUFFIX); exit 1; }; }; } 2>>$(BUILD_DETAILS_FILE); echo $? >&3 ; } | tee -a $(BUILD_DETAILS_FILE) >&4; } 3>&1;} | { read rc ; exit ${rc}; } } 4>&1 @rm -f .test.c .test.o .test$(EXEC_SUFFIX) endif -ifeq ($(CHECK_LIBUSB0), yes) - @printf "Checking for libusb-0.1/libusb-compat headers... " | tee -a $(BUILD_DETAILS_FILE) - @echo "$$LIBUSB0_TEST" > .test.c - @printf "\nexec: %s\n" "$(CC) -c $(CPPFLAGS) $(CFLAGS) .test.c -o .test.o" >>$(BUILD_DETAILS_FILE) - @{ { { { { $(CC) -c $(CPPFLAGS) $(CFLAGS) .test.c -o .test.o >&2 && \ - echo "found." || { echo "not found."; echo; \ - echo "The following features require libusb-0.1/libusb-compat: $(NEED_LIBUSB0)."; \ - echo "Please install libusb-0.1 headers or libusb-compat headers or disable all features"; \ - echo "mentioned above by specifying make CONFIG_ENABLE_LIBUSB0_PROGRAMMERS=no"; \ - echo "See README for more information."; echo; \ - rm -f .test.c .test.o; exit 1; }; } 2>>$(BUILD_DETAILS_FILE); echo $? >&3 ; } | tee -a $(BUILD_DETAILS_FILE) >&4; } 3>&1;} | { read rc ; exit ${rc}; } } 4>&1 - @printf "Checking if libusb-0.1 is usable... " | tee -a $(BUILD_DETAILS_FILE) - @printf "\nexec: %s\n" "$(CC) $(LDFLAGS) .test.o -o .test$(EXEC_SUFFIX) $(LIBS) $(USBLIBS)" >>$(BUILD_DETAILS_FILE) - @{ { { { { $(CC) $(LDFLAGS) .test.o -o .test$(EXEC_SUFFIX) $(LIBS) $(USBLIBS) >&2 && \ - echo "yes." || { echo "no."; \ - echo "The following features require libusb-0.1/libusb-compat: $(NEED_LIBUSB0)."; \ - echo "Please install libusb-0.1 or libusb-compat or disable all features"; \ - echo "mentioned above by specifying make CONFIG_ENABLE_LIBUSB0_PROGRAMMERS=no"; \ - echo "See README for more information."; echo; \ - rm -f .test.c .test.o .test$(EXEC_SUFFIX); exit 1; }; } 2>>$(BUILD_DETAILS_FILE); echo $? >&3 ; } | tee -a $(BUILD_DETAILS_FILE) >&4; } 3>&1;} | { read rc ; exit ${rc}; } } 4>&1 - @rm -f .test.c .test.o .test$(EXEC_SUFFIX) -endif ifeq ($(CHECK_LIBUSB1), yes) @printf "Checking for libusb-1.0 headers... " | tee -a $(BUILD_DETAILS_FILE) @echo "$$LIBUSB1_TEST" > .test.c diff --git a/meson.build b/meson.build index 1923fdf..e1b6c16 100644 --- a/meson.build +++ b/meson.build @@ -67,7 +67,6 @@ deps = [] srcs = [] -need_libusb0 = false need_raw_access = false need_serial = false @@ -91,6 +90,7 @@ config_dediprog = false config_digilent_spi = false config_developerbox_spi = false + config_pickit2_spi = false endif # some programmers require libpci @@ -242,7 +242,6 @@ if config_pickit2_spi srcs += 'pickit2_spi.c' cargs += '-DCONFIG_PICKIT2_SPI=1' - need_libusb0 = true endif if config_pony_spi srcs += 'pony_spi.c' @@ -293,11 +292,6 @@ srcs += 'serial.c' endif -# raw deprecated and old USB library -if need_libusb0 - deps += dependency('libusb') -endif - prefix = get_option('prefix') sbindir = join_paths(prefix, get_option('sbindir')) libdir = join_paths(prefix, get_option('libdir')) diff --git a/meson_options.txt b/meson_options.txt index 962866c..b7633d0 100644 --- a/meson_options.txt +++ b/meson_options.txt @@ -26,7 +26,7 @@ option('config_nicnatsemi', type : 'boolean', value : false, description : 'National Semiconductor NICs') option('config_nicrealtek', type : 'boolean', value : true, description : 'Realtek NICs') option('config_ogp_spi', type : 'boolean', value : true, description : 'SPI on OGP cards') -option('config_pickit2_spi', type : 'boolean', value : false, description : 'PICkit2 SPI') +option('config_pickit2_spi', type : 'boolean', value : true, description : 'PICkit2 SPI') option('config_pony_spi', type : 'boolean', value : true, description : 'PonyProg2000 SPI') option('config_rayer_spi', type : 'boolean', value : true, description : 'RayeR SPIPGM') option('config_satamv', type : 'boolean', value : true, description : 'Marvell SATA controllers') diff --git a/pickit2_spi.c b/pickit2_spi.c index 4354025..21a63f8 100644 --- a/pickit2_spi.c +++ b/pickit2_spi.c @@ -39,12 +39,7 @@ #include <string.h> #include <limits.h> #include <errno.h> - -#if IS_WINDOWS -#include <lusb0_usb.h> -#else -#include <usb.h> -#endif +#include <libusb.h> #include "flash.h" #include "chipdrivers.h" @@ -57,7 +52,7 @@ {} }; -static usb_dev_handle *pickit2_handle; +static libusb_device_handle *pickit2_handle; /* Default USB transaction timeout in ms */ #define DFLT_TIMEOUT 10000 @@ -94,36 +89,17 @@ #define SCR_VDD_OFF 0xFE #define SCR_VDD_ON 0xFF -/* Might be useful for other USB devices as well. static for now. - * device parameter allows user to specify one device of multiple installed */ -static struct usb_device *get_device_by_vid_pid(uint16_t vid, uint16_t pid, unsigned int device) -{ - struct usb_bus *bus; - struct usb_device *dev; - - for (bus = usb_get_busses(); bus; bus = bus->next) - for (dev = bus->devices; dev; dev = dev->next) - if ((dev->descriptor.idVendor == vid) && - (dev->descriptor.idProduct == pid)) { - if (device == 0) - return dev; - device--; - } - - return NULL; -} - static int pickit2_get_firmware_version(void) { int ret; uint8_t command[CMD_LENGTH] = {CMD_GET_VERSION, CMD_END_OF_BUFFER}; - ret = usb_interrupt_write(pickit2_handle, ENDPOINT_OUT, (char *)command, CMD_LENGTH, DFLT_TIMEOUT); - ret = usb_interrupt_read(pickit2_handle, ENDPOINT_IN, (char *)command, CMD_LENGTH, DFLT_TIMEOUT); + ret = libusb_interrupt_transfer(pickit2_handle, ENDPOINT_OUT, (unsigned char *)command, CMD_LENGTH, NULL, DFLT_TIMEOUT); + ret = libusb_interrupt_transfer(pickit2_handle, ENDPOINT_IN, (unsigned char *)command, CMD_LENGTH, NULL, DFLT_TIMEOUT); msg_pdbg("PICkit2 Firmware Version: %d.%d\n", (int)command[0], (int)command[1]); - if (ret != CMD_LENGTH) { - msg_perr("Command Get Firmware Version failed (%s)!\n", usb_strerror()); + if (ret != 0) { + msg_perr("Command Get Firmware Version failed!\n"); return 1; } @@ -166,10 +142,10 @@ CMD_END_OF_BUFFER }; - int ret = usb_interrupt_write(pickit2_handle, ENDPOINT_OUT, (char *)command, CMD_LENGTH, DFLT_TIMEOUT); + int ret = libusb_interrupt_transfer(pickit2_handle, ENDPOINT_OUT, (unsigned char *)command, CMD_LENGTH, NULL, DFLT_TIMEOUT); - if (ret != CMD_LENGTH) { - msg_perr("Command Set Voltage failed (%s)!\n", usb_strerror()); + if (ret != 0) { + msg_perr("Command Set Voltage failed!\n"); return 1; } @@ -201,10 +177,10 @@ CMD_END_OF_BUFFER }; - int ret = usb_interrupt_write(pickit2_handle, ENDPOINT_OUT, (char *)command, CMD_LENGTH, DFLT_TIMEOUT); + int ret = libusb_interrupt_transfer(pickit2_handle, ENDPOINT_OUT, (unsigned char*)command, CMD_LENGTH, NULL, DFLT_TIMEOUT); - if (ret != CMD_LENGTH) { - msg_perr("Command Set SPI Speed failed (%s)!\n", usb_strerror()); + if (ret != 0) { + msg_perr("Command Set SPI Speed failed!\n"); return 1; } @@ -270,18 +246,19 @@ buf[i++] = CMD_UPLOAD_DATA; buf[i++] = CMD_END_OF_BUFFER; - int ret = usb_interrupt_write(pickit2_handle, ENDPOINT_OUT, (char *)buf, CMD_LENGTH, DFLT_TIMEOUT); + int ret = libusb_interrupt_transfer(pickit2_handle, ENDPOINT_OUT, (unsigned char *)buf, CMD_LENGTH, NULL, DFLT_TIMEOUT); - if (ret != CMD_LENGTH) { - msg_perr("Send SPI failed, expected %i, got %i %s!\n", writecnt, ret, usb_strerror()); + if (ret != 0) { + msg_perr("Send SPI failed!\n"); return 1; } if (readcnt) { - ret = usb_interrupt_read(pickit2_handle, ENDPOINT_IN, (char *)buf, CMD_LENGTH, DFLT_TIMEOUT); + int length = 0; + ret = libusb_interrupt_transfer(pickit2_handle, ENDPOINT_IN, (unsigned char *)buf, CMD_LENGTH, &length, DFLT_TIMEOUT); - if (ret != CMD_LENGTH) { - msg_perr("Receive SPI failed, expected %i, got %i %s!\n", readcnt, ret, usb_strerror()); + if (length == 0 || ret != 0) { + msg_perr("Receive SPI failed\n"); return 1; } @@ -377,27 +354,22 @@ CMD_END_OF_BUFFER }; - int ret = usb_interrupt_write(pickit2_handle, ENDPOINT_OUT, (char *)command, CMD_LENGTH, DFLT_TIMEOUT); + int ret = libusb_interrupt_transfer(pickit2_handle, ENDPOINT_OUT, (unsigned char*)command, CMD_LENGTH, NULL, DFLT_TIMEOUT); - if (ret != CMD_LENGTH) { - msg_perr("Command Shutdown failed (%s)!\n", usb_strerror()); + if (ret != 0) { + msg_perr("Command Shutdown failed (%s)!\n", libusb_strerror(ret)); ret = 1; } - if (usb_release_interface(pickit2_handle, 0) != 0) { + if (libusb_release_interface(pickit2_handle, 0) != 0) { msg_perr("Could not release USB interface!\n"); ret = 1; } - if (usb_close(pickit2_handle) != 0) { - msg_perr("Could not close USB device!\n"); - ret = 1; - } + libusb_close(pickit2_handle); return ret; } int pickit2_spi_init(void) { - unsigned int usedevice = 0; // FIXME: Allow selecting one of multiple devices - uint8_t buf[CMD_LENGTH] = { CMD_EXEC_SCRIPT, 10, /* Script length */ @@ -444,31 +416,33 @@ } /* Here comes the USB stuff */ - usb_init(); - (void)usb_find_busses(); - (void)usb_find_devices(); + if (pickit2_handle != NULL) { + // FIXME print error + return -1; + } + if (libusb_init(NULL) < 0) { + // FIXME print error + return -1; + } + + // FIXME libusb debug + const uint16_t vid = devs_pickit2_spi[0].vendor_id; const uint16_t pid = devs_pickit2_spi[0].device_id; - struct usb_device *dev = get_device_by_vid_pid(vid, pid, usedevice); - if (dev == NULL) { - msg_perr("Could not find a PICkit2 on USB!\n"); + pickit2_handle = libusb_open_device_with_vid_pid(NULL, vid, pid); + if (pickit2_handle == NULL) { + msg_perr("Could not open device PICkit2!\n"); return 1; } - msg_pdbg("Found USB device (%04x:%04x).\n", dev->descriptor.idVendor, dev->descriptor.idProduct); - pickit2_handle = usb_open(dev); - int ret = usb_set_configuration(pickit2_handle, 1); - if (ret != 0) { - msg_perr("Could not set USB device configuration: %i %s\n", ret, usb_strerror()); - if (usb_close(pickit2_handle) != 0) - msg_perr("Could not close USB device!\n"); + if (libusb_set_configuration(pickit2_handle, 1) != 0) { + msg_perr("Could not set USB device configuration.\n"); + libusb_close(pickit2_handle); return 1; } - ret = usb_claim_interface(pickit2_handle, 0); - if (ret != 0) { - msg_perr("Could not claim USB device interface %i: %i %s\n", 0, ret, usb_strerror()); - if (usb_close(pickit2_handle) != 0) - msg_perr("Could not close USB device!\n"); + if (libusb_claim_interface(pickit2_handle, 0) != 0) { + msg_perr("Could not claim USB device interface\n"); + libusb_close(pickit2_handle); return 1; } @@ -493,9 +467,8 @@ /* Perform basic setup. * Configure pin directions and logic levels, turn Vdd on, turn busy LED on and clear buffers. */ - ret = usb_interrupt_write(pickit2_handle, ENDPOINT_OUT, (char *)buf, CMD_LENGTH, DFLT_TIMEOUT); - if (ret != CMD_LENGTH) { - msg_perr("Command Setup failed (%s)!\n", usb_strerror()); + if (libusb_interrupt_transfer(pickit2_handle, ENDPOINT_OUT, (unsigned char *)buf, CMD_LENGTH, NULL, DFLT_TIMEOUT) != 0) { + msg_perr("Command Setup failed!\n"); return 1; } -- To view, visit https://review.coreboot.org/c/flashrom/+/32213 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Icfc5372aa1789d35ed22d68297d5e68a74d40388 Gerrit-Change-Number: 32213 Gerrit-PatchSet: 1 Gerrit-Owner: Thomas Heijligen <src(a)posteo.de> Gerrit-MessageType: newchange

4 13

Change in ...flashrom[master]: ichspi: Add Apollo Lake support
by Nico Huber (Code Review) 06 Jul '19

06 Jul '19

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/30995 Change subject: ichspi: Add Apollo Lake support ...................................................................... ichspi: Add Apollo Lake support It's almost identical to 100 series PCHs and later. There are some addition FREGs (12..15). To not clutter the `if` conditions further, make more use of `switch` statements. Tested on Kontron mAL10. Mark it as DEP as usually the last sector is not covered by the descriptor layout and can't be read. Change-Id: I1c464b5b3d151e6d28d5db96495fe874a0a45718 Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- M chipset_enable.c M ich_descriptors.c M ichspi.c 3 files changed, 153 insertions(+), 62 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/95/30995/1 diff --git a/chipset_enable.c b/chipset_enable.c index 547f21a..2f73ded 100644 --- a/chipset_enable.c +++ b/chipset_enable.c @@ -1965,7 +1965,7 @@ {0x8086, 0xa2c8, NT, "Intel", "B250", enable_flash_pch100}, {0x8086, 0xa2c9, NT, "Intel", "Z370", enable_flash_pch100}, {0x8086, 0xa2d2, NT, "Intel", "X299", enable_flash_pch100}, - {0x8086, 0x5ae8, BAD, "Intel", "Apollo Lake", enable_flash_apl}, + {0x8086, 0x5ae8, DEP, "Intel", "Apollo Lake", enable_flash_apl}, #endif {0}, }; diff --git a/ich_descriptors.c b/ich_descriptors.c index 56e846f..dcbcfae 100644 --- a/ich_descriptors.c +++ b/ich_descriptors.c @@ -42,6 +42,8 @@ ssize_t ich_number_of_regions(const enum ich_chipset cs, const struct ich_desc_content *const cont) { switch (cs) { + case CHIPSET_APOLLO_LAKE: + return 6; case CHIPSET_C620_SERIES_LEWISBURG: return 16; case CHIPSET_100_SERIES_SUNRISE_POINT: @@ -67,6 +69,7 @@ { switch (cs) { case CHIPSET_C620_SERIES_LEWISBURG: + case CHIPSET_APOLLO_LAKE: if (cont->NM <= MAX_NUM_MASTERS) return cont->NM; default: @@ -139,8 +142,8 @@ msg_pdbg2("FRBA (Flash Region Base Address): 0x%03x\n", getFRBA(cont)); msg_pdbg2("NC (Number of Components): %5d\n", cont->NC + 1); msg_pdbg2("FCBA (Flash Component Base Address): 0x%03x\n", getFCBA(cont)); - msg_pdbg2("ISL (ICH/PCH Strap Length): %5d\n", cont->ISL); - msg_pdbg2("FISBA/FPSBA (Flash ICH/PCH Strap Base Address): 0x%03x\n", getFISBA(cont)); + msg_pdbg2("ISL (ICH/PCH/SoC Strap Length): %5d\n", cont->ISL); + msg_pdbg2("FISBA/FPSBA (Flash ICH/PCH/SoC Strap Base Addr): 0x%03x\n", getFISBA(cont)); msg_pdbg2("NM (Number of Masters): %5zd\n", ich_number_of_masters(cs, cont)); msg_pdbg2("FMBA (Flash Master Base Address): 0x%03x\n", getFMBA(cont)); msg_pdbg2("MSL/PSL (MCH/PROC Strap Length): %5d\n", cont->MSL); @@ -193,7 +196,8 @@ case CHIPSET_9_SERIES_WILDCAT_POINT: case CHIPSET_9_SERIES_WILDCAT_POINT_LP: case CHIPSET_100_SERIES_SUNRISE_POINT: - case CHIPSET_C620_SERIES_LEWISBURG: { + case CHIPSET_C620_SERIES_LEWISBURG: + case CHIPSET_APOLLO_LAKE: { uint8_t size_enc; if (idx == 0) { size_enc = desc->component.dens_new.comp1_density; @@ -212,7 +216,7 @@ static const char *pprint_freq(enum ich_chipset cs, uint8_t value) { - static const char *const freq_str[2][8] = { { + static const char *const freq_str[3][8] = { { "20 MHz", /* 000 */ "33 MHz", /* 001 */ "reserved", /* 010 */ @@ -230,6 +234,15 @@ "reserved", /* 101 */ "17 MHz", /* 110 */ "reserved" /* 111 */ + }, { + "reserved", /* 000 */ + "50 MHz", /* 001 */ + "40 MHz", /* 010 */ + "reserved", /* 011 */ + "25 MHz", /* 100 */ + "reserved", /* 101 */ + "17 MHz", /* 110 */ + "reserved" /* 111 */ } }; switch (cs) { @@ -251,6 +264,8 @@ case CHIPSET_100_SERIES_SUNRISE_POINT: case CHIPSET_C620_SERIES_LEWISBURG: return freq_str[1][value]; + case CHIPSET_APOLLO_LAKE: + return freq_str[2][value]; case CHIPSET_ICH_UNKNOWN: default: return "unknown"; @@ -259,11 +274,23 @@ void prettyprint_ich_descriptor_component(enum ich_chipset cs, const struct ich_descriptors *desc) { + bool has_flill1; + + switch (cs) { + case CHIPSET_100_SERIES_SUNRISE_POINT: + case CHIPSET_C620_SERIES_LEWISBURG: + case CHIPSET_APOLLO_LAKE: + has_flill1 = true; + break; + default: + has_flill1 = false; + break; + } msg_pdbg2("=== Component Section ===\n"); msg_pdbg2("FLCOMP 0x%08x\n", desc->component.FLCOMP); msg_pdbg2("FLILL 0x%08x\n", desc->component.FLILL ); - if (cs == CHIPSET_100_SERIES_SUNRISE_POINT || cs == CHIPSET_C620_SERIES_LEWISBURG) + if (has_flill1) msg_pdbg2("FLILL1 0x%08x\n", desc->component.FLILL1); msg_pdbg2("\n"); @@ -296,7 +323,7 @@ msg_pdbg2("Invalid instruction 3: 0x%02x\n", desc->component.invalid_instr3); } - if (cs == CHIPSET_100_SERIES_SUNRISE_POINT || cs == CHIPSET_C620_SERIES_LEWISBURG) { + if (has_flill1) { if (desc->component.FLILL1 != 0) { has_forbidden_opcode = 1; msg_pdbg2("Invalid instruction 4: 0x%02x\n", @@ -318,7 +345,7 @@ static void pprint_freg(const struct ich_desc_region *reg, uint32_t i) { static const char *const region_names[] = { - "Descr.", "BIOS", "ME", "GbE", "Platf.", "unknown", "BIOS2", "unknown", + "Descr.", "BIOS", "ME", "GbE", "Platf.", "DevExt", "BIOS2", "unknown", "EC/BMC", "unknown", "IE", "10GbE", "unknown", "unknown", "unknown", "unknown" }; if (i >= ARRAY_SIZE(region_names)) { @@ -415,6 +442,23 @@ desc->master.mstr[i].write & (1 << j) ? 'w' : ' '); msg_pdbg2("\n"); } + } else if (cs == CHIPSET_APOLLO_LAKE) { + const char *const master_names[] = { "BIOS", "TXE", }; + if (nm > ARRAY_SIZE(master_names)) { + msg_pdbg2("%s: number of masters too high (%d).\n", __func__, desc->content.NM); + return; + } + + msg_pdbg2(" FD IFWI TXE n/a Platf DevExt\n"); + for (i = 0; i < nm; i++) { + size_t j; + msg_pdbg2("%-4s", master_names[i]); + for (j = 0; j < ich_number_of_regions(cs, &desc->content); j++) + msg_pdbg2(" %c%c ", + desc->master.mstr[i].read & (1 << j) ? 'r' : ' ', + desc->master.mstr[i].write & (1 << j) ? 'w' : ' '); + msg_pdbg2("\n"); + } } else { const struct ich_desc_master *const mstr = &desc->master; msg_pdbg2(" Descr. BIOS ME GbE Platf.\n"); @@ -857,6 +901,11 @@ return CHIPSET_ICH10; else if (content->ISL <= 16) return CHIPSET_5_SERIES_IBEX_PEAK; + else if (content->FLMAP2 == 0) { + if (content->ISL != 19) + msg_pwarn("Peculiar firmware descriptor, assuming Apollo Lake compatibility.\n"); + return CHIPSET_APOLLO_LAKE; + } msg_pwarn("Peculiar firmware descriptor, assuming Ibex Peak compatibility.\n"); return CHIPSET_5_SERIES_IBEX_PEAK; } else if (content->ICCRIBA < 0x31 && content->FMSBA < 0x30) { @@ -886,8 +935,20 @@ { const enum ich_chipset guess = guess_ich_chipset_from_content(content); - if (component->modes.freq_read == 6) { - if ((guess != CHIPSET_100_SERIES_SUNRISE_POINT) && (guess != CHIPSET_C620_SERIES_LEWISBURG)) { + switch (guess) { + case CHIPSET_100_SERIES_SUNRISE_POINT: + case CHIPSET_C620_SERIES_LEWISBURG: + case CHIPSET_APOLLO_LAKE: + if (component->modes.freq_read != 6) { + msg_pwarn("\nThe firmware descriptor looks like a Skylake/Sunrise Point descriptor.\n" + "However, the read frequency isn't set to 17MHz (the only valid value).\n" + "Please report this message, the output of `ich_descriptors_tool` for\n" + "your descriptor and the output of `lspci -nn` to flashrom(a)flashrom.org\n\n"); + return CHIPSET_9_SERIES_WILDCAT_POINT; + } + return guess; + default: + if (component->modes.freq_read == 6) { msg_pwarn("\nThe firmware descriptor has the read frequency set to 17MHz. However,\n" "it doesn't look like a Skylake/Sunrise Point compatible descriptor.\n" "Please report this message, the output of `ich_descriptors_tool` for\n" @@ -895,17 +956,7 @@ return CHIPSET_100_SERIES_SUNRISE_POINT; } return guess; - } else { - if (guess == CHIPSET_100_SERIES_SUNRISE_POINT || guess == CHIPSET_C620_SERIES_LEWISBURG) { - msg_pwarn("\nThe firmware descriptor looks like a Skylake/Sunrise Point descriptor.\n" - "However, the read frequency isn't set to 17MHz (the only valid value).\n" - "Please report this message, the output of `ich_descriptors_tool` for\n" - "your descriptor and the output of `lspci -nn` to flashrom(a)flashrom.org\n\n"); - return CHIPSET_9_SERIES_WILDCAT_POINT; - } } - - return guess; } /* len is the length of dump in bytes */ @@ -1036,6 +1087,7 @@ case CHIPSET_9_SERIES_WILDCAT_POINT_LP: case CHIPSET_100_SERIES_SUNRISE_POINT: case CHIPSET_C620_SERIES_LEWISBURG: + case CHIPSET_APOLLO_LAKE: if (idx == 0) { size_enc = desc->component.dens_new.comp1_density; } else { @@ -1066,10 +1118,13 @@ uint32_t control = 0; control |= (section << FDOC_FDSS_OFF) & FDOC_FDSS; control |= (offset << FDOC_FDSI_OFF) & FDOC_FDSI; - if (cs == CHIPSET_100_SERIES_SUNRISE_POINT || cs == CHIPSET_C620_SERIES_LEWISBURG) { + switch (cs) { + case CHIPSET_100_SERIES_SUNRISE_POINT: + case CHIPSET_C620_SERIES_LEWISBURG: + case CHIPSET_APOLLO_LAKE: mmio_le_writel(control, spibar + PCH100_REG_FDOC); return mmio_le_readl(spibar + PCH100_REG_FDOD); - } else { + default: mmio_le_writel(control, spibar + ICH9_REG_FDOC); return mmio_le_readl(spibar + ICH9_REG_FDOD); } diff --git a/ichspi.c b/ichspi.c index 9eb24a9..2c8a89f 100644 --- a/ichspi.c +++ b/ichspi.c @@ -29,6 +29,9 @@ #include "spi.h" #include "ich_descriptors.h" +/* Apollo Lake */ +#define APL_REG_FREG12 0xe0 /* 32 Bytes Flash Region 12 */ + /* Sunrise Point */ /* Added HSFS Status bits */ @@ -1564,15 +1567,17 @@ static enum ich_access_protection ich9_handle_frap(uint32_t frap, int i) { const int rwperms_unknown = ARRAY_SIZE(access_names); - static const char *const region_names[5] = { + static const char *const region_names[6] = { "Flash Descriptor", "BIOS", "Management Engine", - "Gigabit Ethernet", "Platform Data" + "Gigabit Ethernet", "Platform Data", "Device Extension", }; const char *const region_name = i < ARRAY_SIZE(region_names) ? region_names[i] : "unknown"; uint32_t base, limit; int rwperms; - int offset = ICH9_REG_FREG0 + i * 4; + const int offset = i < 12 + ? ICH9_REG_FREG0 + i * 4 + : APL_REG_FREG12 + (i - 12) * 4; uint32_t freg = mmio_readl(ich_spibar + offset); if (i < 8) { @@ -1716,8 +1721,10 @@ ich_spibar = spibar; /* Moving registers / bits */ - if (ich_generation == CHIPSET_100_SERIES_SUNRISE_POINT) { - num_freg = 10; + switch (ich_generation) { + case CHIPSET_100_SERIES_SUNRISE_POINT: + case CHIPSET_C620_SERIES_LEWISBURG: + case CHIPSET_APOLLO_LAKE: num_pr = 6; /* Includes GPR0 */ reg_pr0 = PCH100_REG_FPR0; swseq_data.reg_ssfsc = PCH100_REG_SSFSC; @@ -1727,19 +1734,8 @@ hwseq_data.addr_mask = PCH100_FADDR_FLA; hwseq_data.only_4k = true; hwseq_data.hsfc_fcycle = PCH100_HSFC_FCYCLE; - } else if (ich_generation == CHIPSET_C620_SERIES_LEWISBURG) { - num_freg = 12; /* 12 MMIO regs, but 16 regions in FD spec */ - num_pr = 6; /* Includes GPR0 */ - reg_pr0 = PCH100_REG_FPR0; - swseq_data.reg_ssfsc = PCH100_REG_SSFSC; - swseq_data.reg_preop = PCH100_REG_PREOP; - swseq_data.reg_optype = PCH100_REG_OPTYPE; - swseq_data.reg_opmenu = PCH100_REG_OPMENU; - hwseq_data.addr_mask = PCH100_FADDR_FLA; - hwseq_data.only_4k = true; - hwseq_data.hsfc_fcycle = PCH100_HSFC_FCYCLE; - } else { - num_freg = 5; + break; + default: num_pr = 5; reg_pr0 = ICH9_REG_PR0; swseq_data.reg_ssfsc = ICH9_REG_SSFS; @@ -1749,6 +1745,21 @@ hwseq_data.addr_mask = ICH9_FADDR_FLA; hwseq_data.only_4k = false; hwseq_data.hsfc_fcycle = HSFC_FCYCLE; + break; + } + switch (ich_generation) { + case CHIPSET_100_SERIES_SUNRISE_POINT: + num_freg = 10; + break; + case CHIPSET_C620_SERIES_LEWISBURG: + num_freg = 12; /* 12 MMIO regs, but 16 regions in FD spec */ + break; + case CHIPSET_APOLLO_LAKE: + num_freg = 16; + break; + default: + num_freg = 5; + break; } switch (ich_generation) { @@ -1834,10 +1845,16 @@ tmp = mmio_readl(ich_spibar + ICH9_REG_FADDR); msg_pdbg2("0x08: 0x%08x (FADDR)\n", tmp); - if (ich_gen == CHIPSET_100_SERIES_SUNRISE_POINT || ich_gen == CHIPSET_C620_SERIES_LEWISBURG) { - const uint32_t dlock = mmio_readl(ich_spibar + PCH100_REG_DLOCK); - msg_pdbg("0x0c: 0x%08x (DLOCK)\n", dlock); - prettyprint_pch100_reg_dlock(dlock); + switch (ich_gen) { + case CHIPSET_100_SERIES_SUNRISE_POINT: + case CHIPSET_C620_SERIES_LEWISBURG: + case CHIPSET_APOLLO_LAKE: + tmp = mmio_readl(ich_spibar + PCH100_REG_DLOCK); + msg_pdbg("0x0c: 0x%08x (DLOCK)\n", tmp); + prettyprint_pch100_reg_dlock(tmp); + break; + default: + break; } if (desc_valid) { @@ -1898,37 +1915,51 @@ swseq_data.reg_opmenu, mmio_readl(ich_spibar + swseq_data.reg_opmenu)); msg_pdbg("0x%zx: 0x%08x (OPMENU+4)\n", swseq_data.reg_opmenu + 4, mmio_readl(ich_spibar + swseq_data.reg_opmenu + 4)); - if (ich_generation == CHIPSET_ICH8 && desc_valid) { - tmp = mmio_readl(ich_spibar + ICH8_REG_VSCC); - msg_pdbg("0xC1: 0x%08x (VSCC)\n", tmp); - msg_pdbg("VSCC: "); - prettyprint_ich_reg_vscc(tmp, FLASHROM_MSG_DEBUG, true); - } else if (ich_generation != CHIPSET_100_SERIES_SUNRISE_POINT && - ich_generation != CHIPSET_C620_SERIES_LEWISBURG) { - if (ich_generation != CHIPSET_BAYTRAIL && desc_valid) { + + if (desc_valid) { + switch (ich_gen) { + case CHIPSET_ICH8: + case CHIPSET_100_SERIES_SUNRISE_POINT: + case CHIPSET_C620_SERIES_LEWISBURG: + case CHIPSET_APOLLO_LAKE: + case CHIPSET_BAYTRAIL: + break; + default: ichspi_bbar = mmio_readl(ich_spibar + ICH9_REG_BBAR); - msg_pdbg("0xA0: 0x%08x (BBAR)\n", - ichspi_bbar); + msg_pdbg("0x%x: 0x%08x (BBAR)\n", ICH9_REG_BBAR, ichspi_bbar); ich_set_bbar(0); + break; } - if (desc_valid) { + if (ich_gen == CHIPSET_ICH8) { + tmp = mmio_readl(ich_spibar + ICH8_REG_VSCC); + msg_pdbg("0x%x: 0x%08x (VSCC)\n", ICH8_REG_VSCC, tmp); + msg_pdbg("VSCC: "); + prettyprint_ich_reg_vscc(tmp, FLASHROM_MSG_DEBUG, true); + } else { tmp = mmio_readl(ich_spibar + ICH9_REG_LVSCC); - msg_pdbg("0xC4: 0x%08x (LVSCC)\n", tmp); + msg_pdbg("0x%x: 0x%08x (LVSCC)\n", ICH9_REG_LVSCC, tmp); msg_pdbg("LVSCC: "); prettyprint_ich_reg_vscc(tmp, FLASHROM_MSG_DEBUG, true); tmp = mmio_readl(ich_spibar + ICH9_REG_UVSCC); - msg_pdbg("0xC8: 0x%08x (UVSCC)\n", tmp); + msg_pdbg("0x%x: 0x%08x (UVSCC)\n", ICH9_REG_UVSCC, tmp); msg_pdbg("UVSCC: "); prettyprint_ich_reg_vscc(tmp, FLASHROM_MSG_DEBUG, false); - - tmp = mmio_readl(ich_spibar + ICH9_REG_FPB); - msg_pdbg("0xD0: 0x%08x (FPB)\n", tmp); } - } - if (desc_valid) { + switch (ich_gen) { + case CHIPSET_ICH8: + case CHIPSET_100_SERIES_SUNRISE_POINT: + case CHIPSET_C620_SERIES_LEWISBURG: + case CHIPSET_APOLLO_LAKE: + break; + default: + tmp = mmio_readl(ich_spibar + ICH9_REG_FPB); + msg_pdbg("0x%x: 0x%08x (FPB)\n", ICH9_REG_FPB, tmp); + break; + } + if (read_ich_descriptors_via_fdo(ich_gen, ich_spibar, &desc) == ICH_RET_OK) prettyprint_ich_descriptors(ich_gen, &desc); @@ -1955,6 +1986,11 @@ ich_spi_mode = ich_hwseq; } + if (ich_spi_mode == ich_auto && ich_gen == CHIPSET_APOLLO_LAKE) { + msg_pdbg("Enabling hardware sequencing by default for Apollo Lake.\n"); + ich_spi_mode = ich_hwseq; + } + if (ich_spi_mode == ich_hwseq) { if (!desc_valid) { msg_perr("Hardware sequencing was requested " -- To view, visit https://review.coreboot.org/c/flashrom/+/30995 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I1c464b5b3d151e6d28d5db96495fe874a0a45718 Gerrit-Change-Number: 30995 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newchange

4 19

Change in ...flashrom[master]: chipset_enable: Add Apollo Lake
by Nico Huber (Code Review) 06 Jul '19

06 Jul '19

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/30994 Change subject: chipset_enable: Add Apollo Lake ...................................................................... chipset_enable: Add Apollo Lake It works the same as 100 series PCHs and on. The SPI device is at 0:0d.2, though. Mark as BAD until `ichspi` is revised. Change-Id: I7b1ad402ba562b7b977be111f8cf61f1be50843a Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- M chipset_enable.c M programmer.h 2 files changed, 19 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/94/30994/1 diff --git a/chipset_enable.c b/chipset_enable.c index 4d624a3..547f21a 100644 --- a/chipset_enable.c +++ b/chipset_enable.c @@ -598,6 +598,7 @@ break; case CHIPSET_100_SERIES_SUNRISE_POINT: case CHIPSET_C620_SERIES_LEWISBURG: + case CHIPSET_APOLLO_LAKE: reg_name = "BIOS_SPI_BC"; gcs = pci_read_long(dev, 0xdc); bild = (gcs >> 7) & 1; @@ -621,6 +622,7 @@ static const char *const straps_names_pch567[] = { "LPC", "reserved", "PCI", "SPI" }; static const char *const straps_names_pch89_baytrail[] = { "LPC", "reserved", "reserved", "SPI" }; static const char *const straps_names_pch8_lp[] = { "SPI", "LPC" }; + static const char *const straps_names_apl[] = { "SPI", "reserved" }; static const char *const straps_names_unknown[] = { "unknown", "unknown", "unknown", "unknown" }; const char *const *straps_names; @@ -658,6 +660,9 @@ case CHIPSET_C620_SERIES_LEWISBURG: straps_names = straps_names_pch8_lp; break; + case CHIPSET_APOLLO_LAKE: + straps_names = straps_names_apl; + break; case CHIPSET_8_SERIES_WELLSBURG: // FIXME: check datasheet case CHIPSET_CENTERTON: // FIXME: Datasheet does not mention GCS at all straps_names = straps_names_unknown; @@ -680,6 +685,7 @@ break; case CHIPSET_100_SERIES_SUNRISE_POINT: case CHIPSET_C620_SERIES_LEWISBURG: + case CHIPSET_APOLLO_LAKE: bbs = (gcs >> 6) & 0x1; break; default: @@ -829,7 +835,9 @@ return 0; } -static int enable_flash_pch100_or_c620(struct pci_dev *const dev, const char *const name, const enum ich_chipset pch_generation) +static int enable_flash_pch100_or_c620( + struct pci_dev *const dev, const char *const name, + const int slot, const int func, const enum ich_chipset pch_generation) { int ret = ERROR_FATAL; @@ -850,7 +858,7 @@ pci_init(pci_acc); register_shutdown(enable_flash_pch100_shutdown, pci_acc); - struct pci_dev *const spi_dev = pci_get_dev(pci_acc, dev->domain, dev->bus, 0x1f, 5); + struct pci_dev *const spi_dev = pci_get_dev(pci_acc, dev->domain, dev->bus, slot, func); if (!spi_dev) { msg_perr("Can't allocate PCI device.\n"); return ret; @@ -888,12 +896,17 @@ static int enable_flash_pch100(struct pci_dev *const dev, const char *const name) { - return enable_flash_pch100_or_c620(dev, name, CHIPSET_100_SERIES_SUNRISE_POINT); + return enable_flash_pch100_or_c620(dev, name, 0x1f, 5, CHIPSET_100_SERIES_SUNRISE_POINT); } static int enable_flash_c620(struct pci_dev *const dev, const char *const name) { - return enable_flash_pch100_or_c620(dev, name, CHIPSET_C620_SERIES_LEWISBURG); + return enable_flash_pch100_or_c620(dev, name, 0x1f, 5, CHIPSET_C620_SERIES_LEWISBURG); +} + +static int enable_flash_apl(struct pci_dev *const dev, const char *const name) +{ + return enable_flash_pch100_or_c620(dev, name, 0x0d, 2, CHIPSET_APOLLO_LAKE); } /* Silvermont architecture: Bay Trail(-T/-I), Avoton/Rangeley. @@ -1952,6 +1965,7 @@ {0x8086, 0xa2c8, NT, "Intel", "B250", enable_flash_pch100}, {0x8086, 0xa2c9, NT, "Intel", "Z370", enable_flash_pch100}, {0x8086, 0xa2d2, NT, "Intel", "X299", enable_flash_pch100}, + {0x8086, 0x5ae8, BAD, "Intel", "Apollo Lake", enable_flash_apl}, #endif {0}, }; diff --git a/programmer.h b/programmer.h index 8bf7d29..64508c4 100644 --- a/programmer.h +++ b/programmer.h @@ -708,6 +708,7 @@ CHIPSET_9_SERIES_WILDCAT_POINT_LP, CHIPSET_100_SERIES_SUNRISE_POINT, /* also 6th/7th gen Core i/o (LP) variants */ CHIPSET_C620_SERIES_LEWISBURG, + CHIPSET_APOLLO_LAKE, }; /* ichspi.c */ -- To view, visit https://review.coreboot.org/c/flashrom/+/30994 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I7b1ad402ba562b7b977be111f8cf61f1be50843a Gerrit-Change-Number: 30994 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newchange

4 10

Change in ...flashrom[master]: dediprog: Break apart large (>=32MiB) transfers
by David Hendricks (Code Review) 20 Jun '19

20 Jun '19

David Hendricks has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/30520 Change subject: dediprog: Break apart large (>=32MiB) transfers ...................................................................... dediprog: Break apart large (>=32MiB) transfers The 2-byte length defined in the command spec appears to be 1-based, that is to say that we can transfer 65536 - 1 data packets of 512 bytes in one bulk read request, just shy of 32MiB. Attempting to read >=32MiB at once will result in bulk read failure (with "SPI bulk read failed!" messages). This patch breaks the transfer at 32MiB - 512 bytes to avoid that. Tested using an SF600 (FW v7.2.21), IS25LP256D, W25Q256JV, and MX25L25735. Change-Id: Ia42253137719607c1525581049239cc9e88880a3 Signed-off-by: David Hendricks <david.hendricks(a)gmail.com> --- M dediprog.c 1 file changed, 23 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/20/30520/1 diff --git a/dediprog.c b/dediprog.c index 7738459..2a190d2 100644 --- a/dediprog.c +++ b/dediprog.c @@ -557,6 +557,7 @@ const unsigned int chunksize = 0x200; unsigned int residue = start % chunksize ? min(len, chunksize - start % chunksize) : 0; unsigned int bulklen; + uint32_t max_xfer = 0x2000000 - chunksize; dediprog_set_leds(LED_BUSY); @@ -570,18 +571,31 @@ /* Round down. */ bulklen = (len - residue) / chunksize * chunksize; - ret = dediprog_spi_bulk_read(flash, buf + residue, start + residue, bulklen); - if (ret) - goto err; - len -= residue + bulklen; - if (len != 0) { - msg_pdbg("Slow read for partial block from 0x%x, length 0x%x\n", - start, len); - ret = spi_read_chunked(flash, buf + residue + bulklen, - start + residue + bulklen, len, 16); + /* Break apart large transfers (32MB - chunksize) to avoid "SPI bulk + * read failed!" errors */ + while (bulklen > 0) { + unsigned int xfer_size = min(bulklen, max_xfer); + ret = dediprog_spi_bulk_read(flash, buf + residue, start + residue, xfer_size); if (ret) goto err; + + len -= residue + xfer_size; + if (len == chunksize) { + ret = dediprog_spi_bulk_read(flash, + buf + residue + xfer_size, + start + residue + xfer_size, chunksize); + len -= chunksize; + bulklen -= chunksize; + } else if (len != 0) { + msg_pdbg("Slow read for partial block from 0x%x, length 0x%x\n", + start, len); + ret = spi_read_chunked(flash, buf + residue + xfer_size, + start + residue + xfer_size, len, 16); + if (ret) + goto err; + } + bulklen -= xfer_size; } dediprog_set_leds(LED_PASS); -- To view, visit https://review.coreboot.org/c/flashrom/+/30520 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Ia42253137719607c1525581049239cc9e88880a3 Gerrit-Change-Number: 30520 Gerrit-PatchSet: 1 Gerrit-Owner: David Hendricks <david.hendricks(a)gmail.com> Gerrit-MessageType: newchange

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Change in ...flashrom[master]: layout.c: Don't use global variables for included regions
by Arthur Heymans (Code Review) 17 Jun '19

17 Jun '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/31247 Change subject: layout.c: Don't use global variables for included regions ...................................................................... layout.c: Don't use global variables for included regions This removes the use of global variables for included region arguments and also uses a linked list to store the arguments. Change-Id: I6534cc58b8dcc6256c2730c809286d8083669a6c Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M cli_classic.c M flash.h M layout.c M layout.h 4 files changed, 55 insertions(+), 52 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/47/31247/1 diff --git a/cli_classic.c b/cli_classic.c index ced08c6..5ef8077 100644 --- a/cli_classic.c +++ b/cli_classic.c @@ -151,6 +151,7 @@ #endif /* !STANDALONE */ char *tempstr = NULL; char *pparam = NULL; + struct layout_include_args *include_args = NULL; flashrom_set_log_callback((flashrom_log_callback *)&flashrom_print_cb); @@ -290,7 +291,7 @@ break; case 'i': tempstr = strdup(optarg); - if (register_include_arg(tempstr)) { + if (register_include_arg(&include_args, tempstr)) { free(tempstr); cli_classic_abort_usage(); } @@ -452,7 +453,7 @@ goto out; } - if (!ifd && !fmap && process_include_args(get_global_layout())) { + if (!ifd && !fmap && process_include_args(include_args, get_global_layout())) { ret = 1; goto out; } @@ -608,7 +609,7 @@ if (layoutfile) { layout = get_global_layout(); } else if (ifd && (flashrom_layout_read_from_ifd(&layout, fill_flash, NULL, 0) || - process_include_args(layout))) { + process_include_args(include_args, layout))) { ret = 1; goto out_shutdown; } else if (fmap && fmapfile) { @@ -633,14 +634,14 @@ } if (flashrom_layout_read_fmap_from_buffer(&layout, fill_flash, fmapfile_buffer, fmapfile_size) || - process_include_args(layout)) { + process_include_args(include_args, layout)) { ret = 1; free(fmapfile_buffer); goto out_shutdown; } free(fmapfile_buffer); } else if (fmap && (flashrom_layout_read_fmap_from_rom(&layout, fill_flash, 0, - fill_flash->chip->total_size * 1024) || process_include_args(layout))) { + fill_flash->chip->total_size * 1024) || process_include_args(include_args, layout))) { ret = 1; goto out_shutdown; } @@ -675,7 +676,7 @@ for (i = 0; i < chipcount; i++) free(flashes[i].chip); - layout_cleanup(); + layout_cleanup(&include_args); free(filename); free(fmapfile); free(referencefile); diff --git a/flash.h b/flash.h index 911214c..5bbfa0a 100644 --- a/flash.h +++ b/flash.h @@ -391,10 +391,10 @@ #define msg_cspew(...) print(FLASHROM_MSG_SPEW, __VA_ARGS__) /* chip debug spew */ /* layout.c */ -int register_include_arg(char *name); +int register_include_arg(struct layout_include_args **args, char *name); int read_romlayout(const char *name); int normalize_romentries(const struct flashctx *flash); -void layout_cleanup(void); +void layout_cleanup(struct layout_include_args **args); /* spi.c */ struct spi_command { diff --git a/layout.c b/layout.c index 384a513..583c733 100644 --- a/layout.c +++ b/layout.c @@ -26,11 +26,6 @@ struct romentry entries[MAX_ROMLAYOUT]; static struct flashrom_layout layout = { entries, 0 }; -/* include_args holds the arguments specified at the command line with -i. They must be processed at some point - * so that desired regions are marked as "included" in the layout. */ -static char *include_args[MAX_ROMLAYOUT]; -static int num_include_args = 0; /* the number of valid include_args. */ - struct flashrom_layout *get_global_layout(void) { return &layout; @@ -101,37 +96,30 @@ } #endif -/* returns the index of the entry (or a negative value if it is not found) */ -static int find_include_arg(const char *const name) -{ - unsigned int i; - for (i = 0; i < num_include_args; i++) { - if (!strcmp(include_args[i], name)) - return i; - } - return -1; -} - /* register an include argument (-i) for later processing */ -int register_include_arg(char *name) +int register_include_arg(struct layout_include_args **args, char *name) { - if (num_include_args >= MAX_ROMLAYOUT) { - msg_gerr("Too many regions included (%i).\n", num_include_args); - return 1; - } - + struct layout_include_args *tmp; if (name == NULL) { msg_gerr("<NULL> is a bad region name.\n"); return 1; } - if (find_include_arg(name) != -1) { - msg_gerr("Duplicate region name: \"%s\".\n", name); - return 1; + tmp = *args; + while(tmp) { + if (!strcmp(tmp->name, name)) { + msg_gerr("Duplicate region name: \"%s\".\n", name); + return 1; + } + tmp = tmp->next; } - include_args[num_include_args] = name; - num_include_args++; + tmp = malloc(sizeof(struct layout_include_args)); + + tmp->name = name; + tmp->next = *args; + *args = tmp; + return 0; } @@ -153,45 +141,54 @@ /* process -i arguments * returns 0 to indicate success, >0 to indicate failure */ -int process_include_args(struct flashrom_layout *const l) +int process_include_args(const struct layout_include_args * const args, struct flashrom_layout *const l) { - int i; + int found = 0; + const struct layout_include_args *tmp; - if (num_include_args == 0) + if (args == NULL) return 0; /* User has specified an area, but no layout file is loaded. */ if (l->num_entries == 0) { msg_gerr("Region requested (with -i \"%s\"), " "but no layout data is available.\n", - include_args[0]); + args->name); return 1; } - for (i = 0; i < num_include_args; i++) { - if (find_romentry(l, include_args[i]) < 0) { + tmp = args; + while (tmp) { + if (find_romentry(l, tmp->name) < 0) { msg_gerr("Invalid region specified: \"%s\".\n", - include_args[i]); + tmp->name); return 1; } + tmp = tmp->next; + found++; } - msg_ginfo("Using region%s: \"%s\"", num_include_args > 1 ? "s" : "", - include_args[0]); - for (i = 1; i < num_include_args; i++) - msg_ginfo(", \"%s\"", include_args[i]); + msg_ginfo("Using region%s:", found > 1 ? "s" : ""); + tmp = args; + while (tmp) { + msg_ginfo(" \"%s\"%s", tmp->name, found > 1 ? "," : ""); + found--; + tmp = tmp->next; + } msg_ginfo(".\n"); return 0; } -void layout_cleanup(void) +void layout_cleanup(struct layout_include_args **args) { int i; - for (i = 0; i < num_include_args; i++) { - free(include_args[i]); - include_args[i] = NULL; + struct layout_include_args *tmp; + + while (*args) { + tmp = (*args)->next; + free(*args); + *args = tmp; } - num_include_args = 0; for (i = 0; i < layout.num_entries; i++) { layout.entries[i].included = 0; diff --git a/layout.h b/layout.h index eb54a4f..63607a3 100644 --- a/layout.h +++ b/layout.h @@ -53,10 +53,15 @@ struct romentry entry; }; +struct layout_include_args { + char *name; + struct layout_include_args *next; +}; + struct flashrom_layout *get_global_layout(void); struct flashrom_flashctx; const struct flashrom_layout *get_layout(const struct flashrom_flashctx *const flashctx); -int process_include_args(struct flashrom_layout *); +int process_include_args(const struct layout_include_args * const args, struct flashrom_layout *const l); #endif /* !__LAYOUT_H__ */ -- To view, visit https://review.coreboot.org/c/flashrom/+/31247 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I6534cc58b8dcc6256c2730c809286d8083669a6c Gerrit-Change-Number: 31247 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in ...flashrom[master]: layout.c: Use the the libflashrom function for included arguments
by Arthur Heymans (Code Review) 06 Jun '19

06 Jun '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/31244 Change subject: layout.c: Use the the libflashrom function for included arguments ...................................................................... layout.c: Use the the libflashrom function for included arguments Use the libflashrom function to determine whether included regions are present in the layout file. Change-Id: I5e9375baad763612e179262973413a7161acba8b Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M layout.c 1 file changed, 6 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/44/31244/1 diff --git a/layout.c b/layout.c index e10bb73..384a513 100644 --- a/layout.c +++ b/layout.c @@ -135,24 +135,19 @@ return 0; } -/* returns the index of the entry (or a negative value if it is not found) */ +/* returns -1 if an entry is not found, 0 if found. */ static int find_romentry(struct flashrom_layout *const l, char *name) { - int i; - if (l->num_entries == 0) return -1; msg_gspew("Looking for region \"%s\"... ", name); - for (i = 0; i < l->num_entries; i++) { - if (!strcmp(l->entries[i].name, name)) { - l->entries[i].included = 1; - msg_gspew("found.\n"); - return i; - } + if (flashrom_layout_include_region(l, name)) { + msg_gspew("not found.\n"); + return -1; } - msg_gspew("not found.\n"); - return -1; + msg_gspew("found.\n"); + return 0; } /* process -i arguments -- To view, visit https://review.coreboot.org/c/flashrom/+/31244 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I5e9375baad763612e179262973413a7161acba8b Gerrit-Change-Number: 31244 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

3 6

Change in ...flashrom[master]: dediprog: Implement 4BA EAR mode for protocol v1
by Nico Huber (Code Review) 04 Jun '19

04 Jun '19

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/32016 Change subject: dediprog: Implement 4BA EAR mode for protocol v1 ...................................................................... dediprog: Implement 4BA EAR mode for protocol v1 With an SF100 and protocol version 1, using the extended address register of the flash chip seems safe. Make use of that and remove the broken 4BA modes flag. Tested with SF100 V:5.1.9 and W25Q256FV. Change-Id: If926cf3cbbebf88231116c4d65bafc19d23646f6 Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- M chipdrivers.h M dediprog.c M spi25.c 3 files changed, 26 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/16/32016/1 diff --git a/chipdrivers.h b/chipdrivers.h index 134ed26..e380878 100644 --- a/chipdrivers.h +++ b/chipdrivers.h @@ -58,6 +58,7 @@ int spi_write_chunked(struct flashctx *flash, const uint8_t *buf, unsigned int start, unsigned int len, unsigned int chunksize); int spi_enter_4ba(struct flashctx *flash); int spi_exit_4ba(struct flashctx *flash); +int spi_set_extended_address(struct flashctx *, uint8_t addr_high); /* spi25_statusreg.c */ diff --git a/dediprog.c b/dediprog.c index 03675e5..d48c541 100644 --- a/dediprog.c +++ b/dediprog.c @@ -360,7 +360,7 @@ return 0; } -static void prepare_rw_cmd( +static int prepare_rw_cmd( struct flashctx *const flash, uint8_t *data_packet, unsigned int count, uint8_t dedi_spi_cmd, unsigned int *value, unsigned int *idx, unsigned int start, int is_read) { /* First 5 bytes are common in both generations. */ @@ -400,9 +400,23 @@ } } } else { - *value = start % 0x10000; - *idx = start / 0x10000; + if (flash->chip->feature_bits & FEATURE_4BA_EXT_ADDR) { + if (spi_set_extended_address(flash, start >> 24)) + return 1; + } else if (start >> 24) { + msg_cerr("Can't handle 4-byte address with dediprog.\n"); + return 1; + } + /* + * We don't know how the dediprog firmware handles 4-byte + * addresses. So let's not tell it what we are doing and + * only send the lower 3 bytes. + */ + *value = start & 0xffff; + *idx = (start >> 16) & 0xff; } + + return 0; } /* Bulk read interface, will read multiple 512 byte chunks aligned to 512 bytes. @@ -448,7 +462,8 @@ uint8_t data_packet[command_packet_size]; unsigned int value, idx; - prepare_rw_cmd(flash, data_packet, count, READ_MODE_STD, &value, &idx, start, 1); + if (prepare_rw_cmd(flash, data_packet, count, READ_MODE_STD, &value, &idx, start, 1)) + return 1; int ret = dediprog_write(CMD_READ, value, idx, data_packet, sizeof(data_packet)); if (ret != sizeof(data_packet)) { @@ -604,7 +619,8 @@ uint8_t data_packet[command_packet_size]; unsigned int value, idx; - prepare_rw_cmd(flash, data_packet, count, dedi_spi_cmd, &value, &idx, start, 0); + if (prepare_rw_cmd(flash, data_packet, count, dedi_spi_cmd, &value, &idx, start, 0)) + return 1; int ret = dediprog_write(CMD_WRITE, value, idx, data_packet, sizeof(data_packet)); if (ret != sizeof(data_packet)) { msg_perr("Command Write SPI Bulk failed, %s!\n", libusb_error_name(ret)); @@ -1134,6 +1150,9 @@ if (dediprog_standalone_mode()) return 1; + if (dediprog_devicetype == DEV_SF100 && protocol() == PROTOCOL_V1) + spi_master_dediprog.features &= ~SPI_MASTER_NO_4BA_MODES; + if (dediprog_devicetype == DEV_SF600 && protocol() == PROTOCOL_V2) spi_master_dediprog.features |= SPI_MASTER_4BA; diff --git a/spi25.c b/spi25.c index 8b6c462..fd87dc9 100644 --- a/spi25.c +++ b/spi25.c @@ -363,7 +363,7 @@ return result; } -static int spi_set_extended_address(struct flashctx *const flash, const uint8_t addr_high) +int spi_set_extended_address(struct flashctx *const flash, const uint8_t addr_high) { if (flash->address_high_byte != addr_high && spi_write_extended_address_register(flash, addr_high)) -- To view, visit https://review.coreboot.org/c/flashrom/+/32016 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: If926cf3cbbebf88231116c4d65bafc19d23646f6 Gerrit-Change-Number: 32016 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newchange

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Change in ...flashrom[master]: dummyflasher: Add emulation for Winbond W25Q128FV
by Nico Huber (Code Review) 03 Jun '19

03 Jun '19

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/31011 Change subject: dummyflasher: Add emulation for Winbond W25Q128FV ...................................................................... dummyflasher: Add emulation for Winbond W25Q128FV Just needed a 16MiB chip. Change-Id: Ic01d45c1f709808404ad53bb31f8b998c6977a9d Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M dummyflasher.c 1 file changed, 31 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/11/31011/1 diff --git a/dummyflasher.c b/dummyflasher.c index 2929686..22b28c4 100644 --- a/dummyflasher.c +++ b/dummyflasher.c @@ -43,6 +43,7 @@ EMULATE_SST_SST25VF040_REMS, EMULATE_SST_SST25VF032B, EMULATE_MACRONIX_MX25L6436, + EMULATE_WINBOND_W25Q128FV, }; static enum emu_chip emu_chip = EMULATE_NONE; static char *emu_persistent_image = NULL; @@ -331,6 +332,18 @@ msg_pdbg("Emulating Macronix MX25L6436 SPI flash chip (RDID, " "SFDP)\n"); } + if (!strcmp(tmp, "W25Q128FV")) { + emu_chip = EMULATE_WINBOND_W25Q128FV; + emu_chip_size = 16 * 1024 * 1024; + emu_max_byteprogram_size = 256; + emu_max_aai_size = 0; + emu_jedec_se_size = 4 * 1024; + emu_jedec_be_52_size = 32 * 1024; + emu_jedec_be_d8_size = 64 * 1024; + emu_jedec_ce_60_size = emu_chip_size; + emu_jedec_ce_c7_size = emu_chip_size; + msg_pdbg("Emulating Winbond W25Q128FV SPI flash chip (RDID)\n"); + } #endif if (emu_chip == EMULATE_NONE) { msg_perr("Invalid chip specified for emulation: %s\n", tmp); @@ -474,6 +487,7 @@ const unsigned char sst25vf040_rems_response[2] = {0xbf, 0x44}; const unsigned char sst25vf032b_rems_response[2] = {0xbf, 0x4a}; const unsigned char mx25l6436_rems_response[2] = {0xc2, 0x16}; + const unsigned char w25q128fv_rems_response[2] = {0xef, 0x17}; if (writecnt == 0) { msg_perr("No command sent to the chip!\n"); @@ -532,6 +546,10 @@ if (readcnt > 0) memset(readarr, 0x16, readcnt); break; + case EMULATE_WINBOND_W25Q128FV: + if (readcnt > 0) + memset(readarr, 0x17, readcnt); + break; default: /* ignore */ break; } @@ -555,6 +573,10 @@ for (i = 0; i < readcnt; i++) readarr[i] = mx25l6436_rems_response[(offs + i) % 2]; break; + case EMULATE_WINBOND_W25Q128FV: + for (i = 0; i < readcnt; i++) + readarr[i] = w25q128fv_rems_response[(offs + i) % 2]; + break; default: /* ignore */ break; } @@ -577,6 +599,14 @@ if (readcnt > 2) readarr[2] = 0x17; break; + case EMULATE_WINBOND_W25Q128FV: + if (readcnt > 0) + readarr[0] = 0xef; + if (readcnt > 1) + readarr[1] = 0x40; + if (readcnt > 2) + readarr[2] = 0x18; + break; default: /* ignore */ break; } @@ -806,6 +836,7 @@ case EMULATE_SST_SST25VF040_REMS: case EMULATE_SST_SST25VF032B: case EMULATE_MACRONIX_MX25L6436: + case EMULATE_WINBOND_W25Q128FV: if (emulate_spi_chip_response(writecnt, readcnt, writearr, readarr)) { msg_pdbg("Invalid command sent to flash chip!\n"); -- To view, visit https://review.coreboot.org/c/flashrom/+/31011 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Ic01d45c1f709808404ad53bb31f8b998c6977a9d Gerrit-Change-Number: 31011 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newchange

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Change in ...flashrom[master]: [WIP]spi25.c: Implement fast read
by Arthur Heymans (Code Review) 28 May '19

28 May '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/33034 Change subject: [WIP]spi25.c: Implement fast read ...................................................................... [WIP]spi25.c: Implement fast read Use the fast read OP by default and fall back to regular read if that failed. Change-Id: I96393e1beea0164daa8e366a1d09a573f2c6d16f Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M ichspi.c M spi.h M spi25.c 3 files changed, 23 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/34/33034/1 diff --git a/ichspi.c b/ichspi.c index 0f1470d..54cb1f9 100644 --- a/ichspi.c +++ b/ichspi.c @@ -1117,14 +1117,14 @@ opcode = &(curopcodes->opcode[opcode_index]); /* The following valid writecnt/readcnt combinations exist: - * writecnt = 4, readcnt >= 0 + * writecnt = 4 or 5, readcnt >= 0 (The dummy bit on fast reads gets discarded) * writecnt = 1, readcnt >= 0 * writecnt >= 4, readcnt = 0 * writecnt >= 1, readcnt = 0 * writecnt >= 1 is guaranteed for all commands. */ if ((opcode->spi_type == SPI_OPCODE_TYPE_READ_WITH_ADDRESS) && - (writecnt != 4)) { + ((writecnt != 4) && (writecnt != 5))) { msg_perr("%s: Internal command size error for opcode " "0x%02x, got writecnt=%i, want =4\n", __func__, cmd, writecnt); diff --git a/spi.h b/spi.h index 0073c71..65dc033 100644 --- a/spi.h +++ b/spi.h @@ -149,6 +149,7 @@ /* Read the memory */ #define JEDEC_READ 0x03 #define JEDEC_READ_OUTSIZE 0x04 +#define JEDEC_FAST_READ 0x0b /* JEDEC_READ_INSIZE : any length */ /* Read the memory (with delay after sending address) */ @@ -168,6 +169,7 @@ /* Read the memory with 4-byte address From ANY mode (3-bytes or 4-bytes) it works with 4-byte address */ #define JEDEC_READ_4BA 0x13 +#define JEDEC_FAST_READ_4BA 0x0c /* Read the memory with 4-byte address (and delay after sending address) From ANY mode (3-bytes or 4-bytes) it works with 4-byte address */ diff --git a/spi25.c b/spi25.c index 8b6c462..36d2436 100644 --- a/spi25.c +++ b/spi25.c @@ -645,12 +645,30 @@ unsigned int len) { const bool native_4ba = flash->chip->feature_bits & FEATURE_4BA_READ && spi_master_4ba(flash); - uint8_t cmd[1 + JEDEC_MAX_ADDR_LEN] = { native_4ba ? JEDEC_READ_4BA : JEDEC_READ, }; + bool fast_read = true; + uint8_t cmd[2 + JEDEC_MAX_ADDR_LEN]; + + if (native_4ba) + fast_read = flash->chip->feature_bits & FEATURE_4BA_FAST_READ; + + if (fast_read) + cmd[0] = native_4ba ? JEDEC_FAST_READ_4BA : JEDEC_FAST_READ; + else + cmd[0] = native_4ba ? JEDEC_READ_4BA : JEDEC_READ; const int addr_len = spi_prepare_address(flash, cmd, native_4ba, address); if (addr_len < 0) return 1; + if (fast_read) { + cmd[addr_len + 1] = 0; + int ret = spi_send_command(flash, 2 + addr_len, len, cmd, bytes); + if (!ret) + return ret; + msg_cinfo("%s: Fast Read did not succeed, falling back to regular read", __func__); + cmd[0] = native_4ba ? JEDEC_READ_4BA : JEDEC_READ; + } + /* Send Read */ return spi_send_command(flash, 1 + addr_len, len, cmd, bytes); } -- To view, visit https://review.coreboot.org/c/flashrom/+/33034 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I96393e1beea0164daa8e366a1d09a573f2c6d16f Gerrit-Change-Number: 33034 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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