May 2018 - flashrom-gerrit - mail.coreboot.org

Change in flashrom[master]: [WIP] Hack out a lot of stuff
by build bot (Jenkins) (Code Review) 29 May '18

29 May '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/26657 ) Change subject: [WIP] Hack out a lot of stuff ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/flashrom-customrules/1309/ : SUCCESS https://qa.coreboot.org/job/flashrom_gerrit/1086/ : SUCCESS -- To view, visit https://review.coreboot.org/26657 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Iae8ac4c9006d2f5a488a100e8d878f9069ad7e54 Gerrit-Change-Number: 26657 Gerrit-PatchSet: 1 Gerrit-Owner: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 29 May 2018 02:32:05 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

1 0

Change in flashrom[master]: [WIP] Hack out a lot of stuff
by David Hendricks (Code Review) 29 May '18

29 May '18

David Hendricks has posted comments on this change. ( https://review.coreboot.org/26657 ) Change subject: [WIP] Hack out a lot of stuff ...................................................................... Patch Set 1: Code-Review-2 Move along, nothing to see here... -- To view, visit https://review.coreboot.org/26657 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Iae8ac4c9006d2f5a488a100e8d878f9069ad7e54 Gerrit-Change-Number: 26657 Gerrit-PatchSet: 1 Gerrit-Owner: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Comment-Date: Tue, 29 May 2018 02:32:03 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

1 0

Change in flashrom[master]: [WIP] Hack out a lot of stuff
by David Hendricks (Code Review) 29 May '18

29 May '18

David Hendricks has uploaded this change for review. ( https://review.coreboot.org/26657 Change subject: [WIP] Hack out a lot of stuff ...................................................................... [WIP] Hack out a lot of stuff This is for experimentation and should not be used. Change-Id: Iae8ac4c9006d2f5a488a100e8d878f9069ad7e54 Signed-off-by: David Hendricks <dhendricks(a)fb.com> --- M Makefile M board_enable.c M chipset_enable.c M flashchips.c M internal.c M print.c 6 files changed, 47 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/57/26657/1 diff --git a/Makefile b/Makefile index 943d88d..cd27a5a 100644 --- a/Makefile +++ b/Makefile @@ -517,10 +517,14 @@ ############################################################################### # Flash chip drivers and bus support infrastructure. -CHIP_OBJS = jedec.o stm50.o w39.o w29ee011.o \ - sst28sf040.o 82802ab.o \ - sst49lfxxxc.o sst_fwhub.o edi.o flashchips.o spi.o spi25.o spi25_statusreg.o \ - opaque.o sfdp.o en29lv640b.o at45db.o +#CHIP_OBJS = jedec.o stm50.o w39.o w29ee011.o \ +# sst28sf040.o 82802ab.o \ +# sst49lfxxxc.o sst_fwhub.o edi.o flashchips.o spi.o spi25.o spi25_statusreg.o \ +# opaque.o sfdp.o en29lv640b.o at45db.o +# opaque.o sfdp.o en29lv640b.o at45db.o +CHIP_OBJS = jedec.o \ + flashchips.o spi.o spi25.o spi25_statusreg.o \ + opaque.o sfdp.o ############################################################################### # Library code. @@ -737,7 +741,7 @@ FEATURE_CFLAGS += -D'CONFIG_INTERNAL=1' PROGRAMMER_OBJS += processor_enable.o chipset_enable.o board_enable.o cbtable.o internal.o ifeq ($(ARCH), x86) -PROGRAMMER_OBJS += it87spi.o it85spi.o sb600spi.o amd_imc.o wbsio_spi.o mcp6x_spi.o +#PROGRAMMER_OBJS += it87spi.o it85spi.o sb600spi.o amd_imc.o wbsio_spi.o mcp6x_spi.o PROGRAMMER_OBJS += ichspi.o dmi.o ifeq ($(CONFIG_INTERNAL_DMI), yes) FEATURE_CFLAGS += -D'CONFIG_INTERNAL_DMI=1' diff --git a/board_enable.c b/board_enable.c index a09a075..7e3ffe8 100644 --- a/board_enable.c +++ b/board_enable.c @@ -28,6 +28,7 @@ #include "hwaccess.h" #if defined(__i386__) || defined(__x86_64__) +#if 0 /* * Helper functions for many Winbond Super I/Os of the W836xx range. */ @@ -2256,6 +2257,7 @@ } #endif +#endif /* * Below is the list of boards which need a special "board enable" code in @@ -2302,6 +2304,7 @@ /* first pci-id set [4], second pci-id set [4], dmi identifier, coreboot id [2], phase, vendor name, board name max_rom_... OK? flash enable */ #if defined(__i386__) || defined(__x86_64__) +#if 0 {0x10DE, 0x0547, 0x147B, 0x1C2F, 0x10DE, 0x0548, 0x147B, 0x1C2F, NULL, NULL, NULL, P3, "abit", "AN-M2", 0, NT, nvidia_mcp_gpio2_raise}, {0x1106, 0x0282, 0x147B, 0x1415, 0x1106, 0x3227, 0x147B, 0x1415, "^AV8 ", NULL, NULL, P3, "abit", "AV8", 0, OK, board_abit_av8}, {0x8086, 0x7190, 0, 0, 0x8086, 0x7110, 0, 0, NULL /* "^I440BX-W977$" */, "abit", "bf6", P3, "abit", "BF6", 0, OK, intel_piix4_gpo26_lower}, @@ -2475,6 +2478,7 @@ {0x1106, 0x3177, 0x1106, 0xAA01, 0x1106, 0x3123, 0x1106, 0xAA01, NULL, NULL, NULL, P3, "VIA", "EPIA M/MII/...", 0, OK, via_vt823x_gpio15_raise}, {0x1106, 0x0259, 0x1106, 0x3227, 0x1106, 0x3065, 0x1106, 0x3149, NULL, NULL, NULL, P3, "VIA", "EPIA-N/NL", 0, OK, via_vt823x_gpio9_raise}, #endif +#endif { 0, 0, 0, 0, 0, 0, 0, 0, NULL, NULL, NULL, P3, NULL, NULL, 0, NT, NULL}, /* end marker */ }; diff --git a/chipset_enable.c b/chipset_enable.c index 15b760b..6c78cc0 100644 --- a/chipset_enable.c +++ b/chipset_enable.c @@ -39,6 +39,7 @@ #if defined(__i386__) || defined(__x86_64__) +#if 0 static int enable_flash_ali_m1533(struct pci_dev *dev, const char *name) { uint8_t tmp; @@ -211,6 +212,7 @@ { return enable_flash_sis5x0(dev, name, 0x80, 0x40); } +#endif /* Datasheet: * - Name: 82371AB PCI-TO-ISA / IDE XCELERATOR (PIIX4) @@ -946,6 +948,7 @@ return 0; } +#if 0 static int via_no_byte_merge(struct pci_dev *dev, const char *name) { uint8_t val; @@ -1598,10 +1601,12 @@ } #endif +#endif /* Please keep this list numerically sorted by vendor/device ID. */ const struct penable chipset_enables[] = { #if defined(__i386__) || defined(__x86_64__) +#if 0 {0x1002, 0x4377, OK, "ATI", "SB400", enable_flash_sb400}, {0x1002, 0x438d, OK, "AMD", "SB600", enable_flash_sb600}, {0x1002, 0x439d, OK, "AMD", "SB7x0/SB8x0/SB9x0", enable_flash_sb600}, @@ -1714,6 +1719,7 @@ {0x1166, 0x0200, OK, "Broadcom", "OSB4", enable_flash_osb4}, {0x1166, 0x0205, OK, "Broadcom", "HT-1000", enable_flash_ht1000}, {0x17f3, 0x6030, OK, "RDC", "R8610/R3210", enable_flash_rdc_r8610}, +#endif {0x8086, 0x0c60, NT, "Intel", "S12x0", enable_flash_s12x0}, {0x8086, 0x0f1c, OK, "Intel", "Bay Trail", enable_flash_silvermont}, {0x8086, 0x0f1d, NT, "Intel", "Bay Trail", enable_flash_silvermont}, diff --git a/flashchips.c b/flashchips.c index 8eda608..c33b5b9 100644 --- a/flashchips.c +++ b/flashchips.c @@ -53,6 +53,7 @@ * .voltage = Voltage range in millivolt */ +#if 0 { .vendor = "AMD", .name = "Am29F010", @@ -7419,6 +7420,7 @@ .read = spi_chip_read, /* Fast read (0x0B) supported */ .voltage = {3000, 3600}, }, +#endif { .vendor = "Macronix", @@ -7436,6 +7438,7 @@ .voltage = {3000, 3600}, }, +#if 0 { .vendor = "Macronix", .name = "MX25L512(E)/MX25V512(C)", @@ -8144,6 +8147,7 @@ .read = spi_chip_read, /* Fast read (0x0B) and multi I/O supported */ .voltage = {2700, 3600}, }, +#endif { .vendor = "Macronix", @@ -8221,6 +8225,7 @@ .voltage = {2700, 3600}, }, +#if 0 { .vendor = "Macronix", .name = "MX25L25635F", @@ -8443,6 +8448,7 @@ .read = spi_chip_read, /* Fast read (0x0B) and multi I/O supported */ .voltage = {1650, 2000}, }, +#endif { .vendor = "Macronix", @@ -8484,6 +8490,7 @@ .voltage = {1650, 2000}, }, +#if 0 { .vendor = "Macronix", .name = "MX25L6495F", @@ -9323,6 +9330,7 @@ .read = spi_chip_read, .voltage = {2700, 3600}, }, +#endif { .vendor = "Micron/Numonyx/ST", @@ -9353,6 +9361,7 @@ .voltage = {2700, 3600}, }, +#if 0 { .vendor = "Micron/Numonyx/ST", .name = "M25PE10", @@ -9951,6 +9960,7 @@ .read = spi_chip_read, /* Fast read (0x0B) and multi I/O supported */ .voltage = {2700, 3600}, }, +#endif { .vendor = "Micron/Numonyx/ST", @@ -10018,6 +10028,7 @@ .voltage = {2700, 3600}, }, +#if 0 { .vendor = "Micron", .name = "N25Q256..3E/MT25QL256", /* ..3E/L = 3V, uniform 64KB/4KB blocks/sectors */ @@ -12014,6 +12025,7 @@ .read = spi_chip_read, /* Fast read (0x0B) and multi I/O supported */ .voltage = {2700, 3600}, }, +#endif { .vendor = "Spansion", @@ -12309,6 +12321,7 @@ .voltage = {2700, 3600}, }, +#if 0 { .vendor = "SST", .name = "SST25LF020A", @@ -15014,6 +15027,7 @@ .voltage = {2700, 3600}, }, +#endif { .vendor = "Winbond", .name = "W25Q128.V", @@ -15053,6 +15067,7 @@ .read = spi_chip_read, .voltage = {2700, 3600}, }, +#if 0 { .vendor = "Winbond", @@ -15410,6 +15425,7 @@ .read = spi_chip_read, .voltage = {1700, 1950}, /* Fast read (0x0B) and multi I/O supported */ }, +#endif { .vendor = "Winbond", @@ -15451,6 +15467,7 @@ .voltage = {1650, 1950}, }, +#if 0 { .vendor = "Winbond", .name = "W25X10", @@ -16669,6 +16686,7 @@ .read = spi_chip_read, .voltage = {2700, 3600}, }, +#endif { .vendor = "Unknown", diff --git a/internal.c b/internal.c index 1d6cff6..080a0b4 100644 --- a/internal.c +++ b/internal.c @@ -94,6 +94,7 @@ int force_boardmismatch = 0; #if IS_X86 +#if 0 void probe_superio(void) { probe_superio_winbond(); @@ -105,6 +106,7 @@ //probe_superio_smsc(); probe_superio_ite(); } +#endif int superio_count = 0; #define SUPERIO_MAX_COUNT 3 @@ -263,7 +265,9 @@ board_handle_before_superio(); /* Probe for the Super I/O chip and fill global struct superio. */ +#if 0 probe_superio(); +#endif #else /* FIXME: Enable cbtable searching on all non-x86 platforms supported * by coreboot. @@ -319,7 +323,9 @@ #if IS_X86 /* Probe unconditionally for ITE Super I/O chips. This enables LPC->SPI translation on IT87* and * parallel writes on IT8705F. Also, this handles the manual chip select for Gigabyte's DualBIOS. */ +#if 0 init_superio_ite(); +#endif if (board_flash_enable(board_vendor, board_model, cb_vendor, cb_model)) { msg_perr("Aborting to be safe.\n"); diff --git a/print.c b/print.c index 114181e..799c7da 100644 --- a/print.c +++ b/print.c @@ -515,6 +515,7 @@ /* Please keep this list alphabetically ordered by vendor/board. */ const struct board_info boards_known[] = { #if defined(__i386__) || defined(__x86_64__) +#if 0 B("A-Trend", "ATC-6220", OK, "http://www.motherboard.cz/mb/atrend/atc6220.htm", NULL), B("abit", "A-S78H", OK, NULL, NULL), B("abit", "AN-M2", OK, NULL, NULL), @@ -1136,6 +1137,7 @@ B("ZOTAC", "ZBOX AD02 (PLUS)", OK, NULL, NULL), B("ZOTAC", "ZBOX HD-ID11", OK, NULL, NULL), #endif +#endif {0}, }; @@ -1143,6 +1145,7 @@ /* Please keep this list alphabetically ordered by vendor/board. */ const struct board_info laptops_known[] = { #if defined(__i386__) || defined(__x86_64__) +#if 0 B("Acer", "Aspire 1520", OK, "http://support.acer.com/us/en/acerpanam/notebook/0000/Acer/Aspire1520/Aspir…", NULL), B("Acer", "Aspire One", BAD, NULL, "http://www.coreboot.org/pipermail/coreboot/2009-May/048041.html"), B("ASUS", "A8Jm", OK, NULL, NULL), @@ -1170,7 +1173,7 @@ //B("MSI", "GT60-2OD", OK, "http://www.msi.com/product/nb/GT60_2OD.html", NULL), requires layout patches B("Teclast", "X98 Air 3G", OK, NULL, NULL), #endif - +#endif {0}, }; #endif -- To view, visit https://review.coreboot.org/26657 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Iae8ac4c9006d2f5a488a100e8d878f9069ad7e54 Gerrit-Change-Number: 26657 Gerrit-PatchSet: 1 Gerrit-Owner: David Hendricks <david.hendricks(a)gmail.com>

1 0

Change in flashrom[master]: chipset_enable: Add PCI IDs for discrete Kaby Lake PCHs
by David Hendricks (Code Review) 29 May '18

29 May '18

David Hendricks has posted comments on this change. ( https://review.coreboot.org/26232 ) Change subject: chipset_enable: Add PCI IDs for discrete Kaby Lake PCHs ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/#/c/26232/1//COMMIT_MSG Commit Message: https://review.coreboot.org/#/c/26232/1//COMMIT_MSG@21 PS1, Line 21: Revision 003 It seems you were looking at the same version of spec as me. If you want to leave out the Z370 stuff for now, that's fine too. -- To view, visit https://review.coreboot.org/26232 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ida545d69ec998a5d3ae4dc88e76adbb13952bceb Gerrit-Change-Number: 26232 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 28 May 2018 23:37:51 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

1 0

Change in flashrom[master]: chipset_enable: Add PCI IDs for discrete Kaby Lake PCHs
by David Hendricks (Code Review) 29 May '18

29 May '18

David Hendricks has posted comments on this change. ( https://review.coreboot.org/26232 ) Change subject: chipset_enable: Add PCI IDs for discrete Kaby Lake PCHs ...................................................................... Patch Set 1: Code-Review+2 (1 comment) Looks good, though you may wanna add the Z370 PCI ID while you're at it. https://review.coreboot.org/#/c/26232/1/chipset_enable.c File chipset_enable.c: https://review.coreboot.org/#/c/26232/1/chipset_enable.c@1952 PS1, Line 1952: {0x8086, 0xa2c8, NT, "Intel", "B250", enable_flash_pch100}, Revision 003 of the spec also mentions 0xa2c9 for the Z370. -- To view, visit https://review.coreboot.org/26232 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ida545d69ec998a5d3ae4dc88e76adbb13952bceb Gerrit-Change-Number: 26232 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 28 May 2018 23:35:56 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: Yes

1 0

Change in flashrom[master]: flashchips: AT25SL128A tested PREW
by David Hendricks (Code Review) 29 May '18

29 May '18

David Hendricks has posted comments on this change. ( https://review.coreboot.org/26582 ) Change subject: flashchips: AT25SL128A tested PREW ...................................................................... Patch Set 1: Code-Review-1 Please squash this into the previous patch. -- To view, visit https://review.coreboot.org/26582 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: If32900f742a3b3fb9951eac052cea7631748635e Gerrit-Change-Number: 26582 Gerrit-PatchSet: 1 Gerrit-Owner: Hal Martin <hal.martin+coreboot(a)gmail.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 28 May 2018 23:17:43 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

1 0

Change in flashrom[master]: flashchips: Add ATMEL AT25SL128A
by David Hendricks (Code Review) 29 May '18

29 May '18

David Hendricks has posted comments on this change. ( https://review.coreboot.org/26576 ) Change subject: flashchips: Add ATMEL AT25SL128A ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/#/c/26576/1/flashchips.c File flashchips.c: https://review.coreboot.org/#/c/26576/1/flashchips.c@2261 PS1, Line 2261: TEST_UNTESTED Update this too since you have tested it. -- To view, visit https://review.coreboot.org/26576 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I60c433ffe9e34663c2cfc608b8b76943cd92a8ba Gerrit-Change-Number: 26576 Gerrit-PatchSet: 1 Gerrit-Owner: Hal Martin <hal.martin+coreboot(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Comment-Date: Mon, 28 May 2018 23:17:29 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

1 0

Change in flashrom[master]: flashchips: Add ATMEL AT25SL128A
by David Hendricks (Code Review) 29 May '18

29 May '18

David Hendricks has posted comments on this change. ( https://review.coreboot.org/26576 ) Change subject: flashchips: Add ATMEL AT25SL128A ...................................................................... Patch Set 1: (1 comment) One small nit, otherwise looks good. Thanks! https://review.coreboot.org/#/c/26576/1/flashchips.c File flashchips.c: https://review.coreboot.org/#/c/26576/1/flashchips.c@2287 PS1, Line 2287: 1650, 1950 Voltage tolerance is 1.7-2.0 according to the datasheet, so this should be {1700, 2000}. -- To view, visit https://review.coreboot.org/26576 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I60c433ffe9e34663c2cfc608b8b76943cd92a8ba Gerrit-Change-Number: 26576 Gerrit-PatchSet: 1 Gerrit-Owner: Hal Martin <hal.martin+coreboot(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Comment-Date: Mon, 28 May 2018 23:16:38 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

1 0

Change in flashrom[master]: Remove white space before tab
by Nico Huber (Code Review) 28 May '18

28 May '18

Nico Huber has posted comments on this change. ( https://review.coreboot.org/26652 ) Change subject: Remove white space before tab ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/26652 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I90f171924790ced74a62ca344fee8607607aa480 Gerrit-Change-Number: 26652 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 28 May 2018 18:37:43 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

1 0

Change in flashrom[master]: Enable writes with active ME
by Arthur Heymans (Code Review) 28 May '18

28 May '18

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/26261 ) Change subject: Enable writes with active ME ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/26261 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I94a5e7074b845c227e43d76d04dd1a71082a1cef Gerrit-Change-Number: 26261 Gerrit-PatchSet: 4 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 28 May 2018 17:50:22 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

1 0

2024

2023

2022

2021

2020

2019

2018

2017

flashrom-gerrit May 2018