May 2018 - flashrom-gerrit - mail.coreboot.org

Change in flashrom[master]: chipset_enable: Add PCI IDs for discrete Kaby Lake PCHs
by David Hendricks (Code Review) 31 May '18

31 May '18

David Hendricks has posted comments on this change. ( https://review.coreboot.org/26232 ) Change subject: chipset_enable: Add PCI IDs for discrete Kaby Lake PCHs ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/26232 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ida545d69ec998a5d3ae4dc88e76adbb13952bceb Gerrit-Change-Number: 26232 Gerrit-PatchSet: 3 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 31 May 2018 20:22:01 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in flashrom[master]: Enable writes with active ME
by build bot (Jenkins) (Code Review) 29 May '18

29 May '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/26261 ) Change subject: Enable writes with active ME ...................................................................... Patch Set 6: Build Successful https://qa.coreboot.org/job/flashrom-customrules/1313/ : SUCCESS -- To view, visit https://review.coreboot.org/26261 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I94a5e7074b845c227e43d76d04dd1a71082a1cef Gerrit-Change-Number: 26261 Gerrit-PatchSet: 6 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 29 May 2018 14:57:05 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in flashrom[master]: Enable writes with active ME
by Nico Huber (Code Review) 29 May '18

29 May '18

Nico Huber has submitted this change and it was merged. ( https://review.coreboot.org/26261 ) Change subject: Enable writes with active ME ...................................................................... Enable writes with active ME Replace the `ich_spi_force` logic with more helpful warnings. These can be hidden later, in case the necessary switches are detected. Also, demote some warnings about settings that are the default nowadays (e.g. SPI configuration lock, inaccessible ME region). Change-Id: I94a5e7074b845c227e43d76d04dd1a71082a1cef Signed-off-by: Nico Huber <nico.huber(a)secunet.com> Reviewed-on: https://review.coreboot.org/26261 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M flashrom.8.tmpl M ichspi.c 2 files changed, 39 insertions(+), 54 deletions(-) Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved diff --git a/flashrom.8.tmpl b/flashrom.8.tmpl index e732bcf..a3528f1 100644 --- a/flashrom.8.tmpl +++ b/flashrom.8.tmpl @@ -490,14 +490,7 @@ the ME firmware and so on respectively. The flash descriptor can also specify up to 5 so called "Protected Regions", which are freely chosen address ranges independent from the aforementioned "Flash Regions". All of them can be write -and/or read protected individually. If flashrom detects such a lock it will -disable write support unless the user forces it with the -.sp -.B " flashrom \-p internal:ich_spi_force=yes" -.sp -syntax. If this leads to erase or write accesses to the flash it would most -probably bring it into an inconsistent and unbootable state and we will not -provide any support in such a case. +and/or read protected individually. .sp If you have an Intel chipset with an ICH2 or later southbridge and if you want to set specific IDSEL values for a non-default flash chip or an embedded diff --git a/ichspi.c b/ichspi.c index 1989a87..9eb24a9 100644 --- a/ichspi.c +++ b/ichspi.c @@ -221,6 +221,13 @@ #define ICH7_REG_OPTYPE 0x56 /* 16 Bits */ #define ICH7_REG_OPMENU 0x58 /* 64 Bits */ +enum ich_access_protection { + NO_PROT = 0, + READ_PROT = 1, + WRITE_PROT = 2, + LOCKED = 3, +}; + /* ICH SPI configuration lock-down. May be set during chipset enabling. */ static int ichspi_lock = 0; @@ -1547,12 +1554,15 @@ #define ICH_BRWA(x) ((x >> 8) & 0xff) #define ICH_BRRA(x) ((x >> 0) & 0xff) -/* returns 0 if region is unused or r/w */ -static int ich9_handle_frap(uint32_t frap, int i) +static const enum ich_access_protection access_perms_to_protection[] = { + LOCKED, WRITE_PROT, READ_PROT, NO_PROT +}; +static const char *const access_names[] = { + "locked", "read-only", "write-only", "read-write" +}; + +static enum ich_access_protection ich9_handle_frap(uint32_t frap, int i) { - static const char *const access_names[4] = { - "locked", "read-only", "write-only", "read-write" - }; const int rwperms_unknown = ARRAY_SIZE(access_names); static const char *const region_names[5] = { "Flash Descriptor", "BIOS", "Management Engine", @@ -1582,23 +1592,23 @@ /* this FREG is disabled */ msg_pdbg2("0x%02X: 0x%08x FREG%i: %s region is unused.\n", offset, freg, i, region_name); - return 0; + return NO_PROT; } msg_pdbg("0x%02X: 0x%08x ", offset, freg); if (rwperms == 0x3) { msg_pdbg("FREG%i: %s region (0x%08x-0x%08x) is %s.\n", i, region_name, base, limit, access_names[rwperms]); - return 0; + return NO_PROT; } if (rwperms == rwperms_unknown) { msg_pdbg("FREG%i: %s region (0x%08x-0x%08x) has unknown permissions.\n", i, region_name, base, limit); - return 0; + return NO_PROT; } - msg_pwarn("FREG%i: Warning: %s region (0x%08x-0x%08x) is %s.\n", i, + msg_pinfo("FREG%i: %s region (0x%08x-0x%08x) is %s.\n", i, region_name, base, limit, access_names[rwperms]); - return 1; + return access_perms_to_protection[rwperms]; } /* In contrast to FRAP and the master section of the descriptor the bits @@ -1610,12 +1620,8 @@ #define ICH_PR_PERMS(pr) (((~((pr) >> PR_RP_OFF) & 1) << 0) | \ ((~((pr) >> PR_WP_OFF) & 1) << 1)) -/* returns 0 if range is unused (i.e. r/w) */ -static int ich9_handle_pr(const size_t reg_pr0, int i) +static enum ich_access_protection ich9_handle_pr(const size_t reg_pr0, int i) { - static const char *const access_names[3] = { - "locked", "read-only", "write-only" - }; uint8_t off = reg_pr0 + (i * 4); uint32_t pr = mmio_readl(ich_spibar + off); unsigned int rwperms = ICH_PR_PERMS(pr); @@ -1627,13 +1633,13 @@ if (rwperms == 0x3) { msg_pdbg2("0x%02X: 0x%08x (%sPR%u is unused)\n", off, pr, prefix, i); - return 0; + return NO_PROT; } msg_pdbg("0x%02X: 0x%08x ", off, pr); msg_pwarn("%sPR%u: Warning: 0x%08x-0x%08x is %s.\n", prefix, i, ICH_FREG_BASE(pr), ICH_FREG_LIMIT(pr), access_names[rwperms]); - return 1; + return access_perms_to_protection[rwperms]; } /* Set/Clear the read and write protection enable bits of PR register @i @@ -1696,7 +1702,6 @@ uint16_t tmp2; uint32_t tmp; char *arg; - int ich_spi_force = 0; int ich_spi_rw_restricted = 0; int desc_valid = 0; struct ich_descriptors desc = {{ 0 }}; @@ -1805,27 +1810,11 @@ } free(arg); - arg = extract_programmer_param("ich_spi_force"); - if (arg && !strcmp(arg, "yes")) { - ich_spi_force = 1; - msg_pspew("ich_spi_force enabled.\n"); - } else if (arg && !strlen(arg)) { - msg_perr("Missing argument for ich_spi_force.\n"); - free(arg); - return ERROR_FATAL; - } else if (arg) { - msg_perr("Unknown argument for ich_spi_force: \"%s\" " - "(not \"yes\").\n", arg); - free(arg); - return ERROR_FATAL; - } - free(arg); - tmp2 = mmio_readw(ich_spibar + ICH9_REG_HSFS); msg_pdbg("0x04: 0x%04x (HSFS)\n", tmp2); prettyprint_ich9_reg_hsfs(tmp2); if (tmp2 & HSFS_FLOCKDN) { - msg_pwarn("Warning: SPI Configuration Lockdown activated.\n"); + msg_pinfo("SPI Configuration is locked down.\n"); ichspi_lock = 1; } if (tmp2 & HSFS_FDV) @@ -1863,7 +1852,7 @@ for (i = 0; i < num_freg; i++) ich_spi_rw_restricted |= ich9_handle_frap(tmp, i); if (ich_spi_rw_restricted) - msg_pwarn("Not all flash regions are freely accessible by flashrom. This is " + msg_pinfo("Not all flash regions are freely accessible by flashrom. This is " "most likely\ndue to an active ME. Please see " "https://flashrom.org/ME for details.\n"); } @@ -1876,16 +1865,19 @@ ich_spi_rw_restricted |= ich9_handle_pr(reg_pr0, i); } - if (ich_spi_rw_restricted) { - if (!ich_spi_force) - programmer_may_write = 0; - msg_pinfo("Writes have been disabled for safety reasons. You can enforce write\n" - "support with the ich_spi_force programmer option, but you will most likely\n" - "harm your hardware! If you force flashrom you will get no support if\n" - "something breaks. On a few mainboards it is possible to enable write\n" - "access by setting a jumper (see its documentation or the board itself).\n"); - if (ich_spi_force) - msg_pinfo("Continuing with write support because the user forced us to!\n"); + switch (ich_spi_rw_restricted) { + case WRITE_PROT: + msg_pwarn("At least some flash regions are write protected. For write operations,\n" + "you should use a flash layout and include only writable regions. See\n" + "manpage for more details.\n"); + break; + case READ_PROT: + case LOCKED: + msg_pwarn("At least some flash regions are read protected. You have to use a flash\n" + "layout and include only accessible regions. For write operations, you'll\n" + "additionally need the --noverify-all switch. See manpage for more details.\n" + ); + break; } tmp = mmio_readl(ich_spibar + swseq_data.reg_ssfsc); -- To view, visit https://review.coreboot.org/26261 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-MessageType: merged Gerrit-Change-Id: I94a5e7074b845c227e43d76d04dd1a71082a1cef Gerrit-Change-Number: 26261 Gerrit-PatchSet: 6 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in flashrom[master]: Enable writes with active ME
by build bot (Jenkins) (Code Review) 29 May '18

29 May '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/26261 ) Change subject: Enable writes with active ME ...................................................................... Patch Set 5: Verified+1 Build Successful https://qa.coreboot.org/job/flashrom-customrules/1312/ : SUCCESS https://qa.coreboot.org/job/flashrom_gerrit/1088/ : SUCCESS -- To view, visit https://review.coreboot.org/26261 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I94a5e7074b845c227e43d76d04dd1a71082a1cef Gerrit-Change-Number: 26261 Gerrit-PatchSet: 5 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 29 May 2018 14:56:45 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in flashrom[master]: flashchips: Add ATMEL AT25SL128A
by Nico Huber (Code Review) 29 May '18

29 May '18

Nico Huber has posted comments on this change. ( https://review.coreboot.org/26576 ) Change subject: flashchips: Add ATMEL AT25SL128A ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/#/c/26576/1/flashchips.c File flashchips.c: https://review.coreboot.org/#/c/26576/1/flashchips.c@2259 PS1, Line 2259: /* OTP: 1024B total, 256B reserved; read 0x48; write 0x42, erase 0x44, read ID 0x4B */ Datasheet says 512B (4kbit) with enter/exit functions etc... -- To view, visit https://review.coreboot.org/26576 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I60c433ffe9e34663c2cfc608b8b76943cd92a8ba Gerrit-Change-Number: 26576 Gerrit-PatchSet: 1 Gerrit-Owner: Hal Martin <hal.martin+coreboot(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: David Hendricks <david.hendricks(a)gmail.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-Comment-Date: Tue, 29 May 2018 11:25:50 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in flashrom[master]: chipset_enable: Add PCI IDs for discrete Kaby Lake PCHs
by Nico Huber (Code Review) 29 May '18

29 May '18

Nico Huber has posted comments on this change. ( https://review.coreboot.org/26232 ) Change subject: chipset_enable: Add PCI IDs for discrete Kaby Lake PCHs ...................................................................... Patch Set 3: (2 comments) https://review.coreboot.org/#/c/26232/1//COMMIT_MSG Commit Message: https://review.coreboot.org/#/c/26232/1//COMMIT_MSG@21 PS1, Line 21: Revision 003 > It seems you were looking at the same version of spec as me. […] No, you were right initially. Device IDs are listed in volume 1 and that's where I was looking at revision 002 ;) https://review.coreboot.org/#/c/26232/1/chipset_enable.c File chipset_enable.c: https://review.coreboot.org/#/c/26232/1/chipset_enable.c@1952 PS1, Line 1952: {0x8086, 0xa2c8, NT, "Intel", "B250", enable_flash_pch100}, > Revision 003 of the spec also mentions 0xa2c9 for the Z370. Done -- To view, visit https://review.coreboot.org/26232 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ida545d69ec998a5d3ae4dc88e76adbb13952bceb Gerrit-Change-Number: 26232 Gerrit-PatchSet: 3 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 29 May 2018 10:22:47 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in flashrom[master]: chipset_enable: Add PCI IDs for discrete Kaby Lake PCHs
by build bot (Jenkins) (Code Review) 29 May '18

29 May '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/26232 ) Change subject: chipset_enable: Add PCI IDs for discrete Kaby Lake PCHs ...................................................................... Patch Set 3: Verified+1 Build Successful https://qa.coreboot.org/job/flashrom-customrules/1311/ : SUCCESS -- To view, visit https://review.coreboot.org/26232 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ida545d69ec998a5d3ae4dc88e76adbb13952bceb Gerrit-Change-Number: 26232 Gerrit-PatchSet: 3 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 29 May 2018 10:22:41 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in flashrom[master]: chipset_enable: Add PCI IDs for discrete Kaby Lake PCHs
by Nico Huber (Code Review) 29 May '18

29 May '18

Hello David Hendricks, Paul Menzel, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/26232 to look at the new patch set (#3). Change subject: chipset_enable: Add PCI IDs for discrete Kaby Lake PCHs ...................................................................... chipset_enable: Add PCI IDs for discrete Kaby Lake PCHs The Kaby Lake "200 Series" PCHs [1,2] share the register layout of their Skylake "100 Series" siblings. [1] Intel® 200 Series (including X299) and Intel® Z370 Series Chipset Families Platform Controller Hub (PCH) Datasheet - Volume 1 of 2 Revision 003 Document Number 335192 [2] Intel® 200 Series (including X299) Chipset Family Platform Controller Hub (PCH) Datasheet - Volume 2 of 2 Revision 003 Document Number 335193 Change-Id: Ida545d69ec998a5d3ae4dc88e76adbb13952bceb Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M chipset_enable.c 1 file changed, 7 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/32/26232/3 -- To view, visit https://review.coreboot.org/26232 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: Ida545d69ec998a5d3ae4dc88e76adbb13952bceb Gerrit-Change-Number: 26232 Gerrit-PatchSet: 3 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in flashrom[master]: chipset_enable: Add PCI IDs for discrete Kaby Lake PCHs
by build bot (Jenkins) (Code Review) 29 May '18

29 May '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/26232 ) Change subject: chipset_enable: Add PCI IDs for discrete Kaby Lake PCHs ...................................................................... Patch Set 2: Verified+1 Build Successful https://qa.coreboot.org/job/flashrom-customrules/1310/ : SUCCESS https://qa.coreboot.org/job/flashrom_gerrit/1087/ : SUCCESS -- To view, visit https://review.coreboot.org/26232 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ida545d69ec998a5d3ae4dc88e76adbb13952bceb Gerrit-Change-Number: 26232 Gerrit-PatchSet: 2 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 29 May 2018 10:20:09 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in flashrom[master]: chipset_enable: Add PCI IDs for discrete Kaby Lake PCHs
by Nico Huber (Code Review) 29 May '18

29 May '18

Hello David Hendricks, Paul Menzel, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/26232 to look at the new patch set (#2). Change subject: chipset_enable: Add PCI IDs for discrete Kaby Lake PCHs ...................................................................... chipset_enable: Add PCI IDs for discrete Kaby Lake PCHs The Kaby Lake "200 Series" PCHs [1,2] share the register layout of their Skylake "100 Series" siblings. [1] Intel® 200 Series (including X299) Chipset Family Platform Controller Hub (PCH) Datasheet - Volume 1 of 2 Revision 003 Document Number 335192 [2] Intel® 200 Series (including X299) Chipset Family Platform Controller Hub (PCH) Datasheet - Volume 2 of 2 Revision 003 Document Number 335193 Change-Id: Ida545d69ec998a5d3ae4dc88e76adbb13952bceb Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M chipset_enable.c 1 file changed, 7 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/32/26232/2 -- To view, visit https://review.coreboot.org/26232 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: Ida545d69ec998a5d3ae4dc88e76adbb13952bceb Gerrit-Change-Number: 26232 Gerrit-PatchSet: 2 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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