September 2017 - flashrom-gerrit

Change in flashrom[stable]: ichspi: Drop `dev` parameter from init functions
by Nico Huber (Code Review) 30 Sep '17

30 Sep '17

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/21803 Change subject: ichspi: Drop `dev` parameter from init functions ...................................................................... ichspi: Drop `dev` parameter from init functions It's never used and has no clear contract (e.g. will the pointer stay valid beyond the call?). Original-Change-Id: I0d4e7cc731364e86eff214b9022b842a577f9ef4 Original-Reviewed-on: https://review.coreboot.org/19460 Original-Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Original-Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude(a)gmail.com> Original-Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Change-Id: I01978e3e45332021f8967034bbaa907ef5f48d19 Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- M chipset_enable.c M ichspi.c M programmer.h 3 files changed, 8 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/03/21803/1 diff --git a/chipset_enable.c b/chipset_enable.c index 208cd3a..83c470f 100644 --- a/chipset_enable.c +++ b/chipset_enable.c @@ -718,7 +718,7 @@ void *spibar = rcrb + spibar_offset; /* This adds BUS_SPI */ - int ret_spi = ich_init_spi(dev, spibar, ich_generation); + int ret_spi = ich_init_spi(spibar, ich_generation); if (ret_spi == ERROR_FATAL) return ret_spi; @@ -846,7 +846,7 @@ */ enable_flash_ich_bios_cntl_memmapped(ich_generation, spibar + 0xFC); - int ret_spi = ich_init_spi(dev, spibar, ich_generation); + int ret_spi = ich_init_spi(spibar, ich_generation); if (ret_spi == ERROR_FATAL) return ret_spi; @@ -949,12 +949,12 @@ return ERROR_FATAL; } - return via_init_spi(dev, spi0_mm_base); + return via_init_spi(spi0_mm_base); } static int enable_flash_vt8237s_spi(struct pci_dev *dev, const char *name) { - return via_init_spi(dev, pci_read_long(dev, 0xbc) << 8); + return via_init_spi(pci_read_long(dev, 0xbc) << 8); } static int enable_flash_cs5530(struct pci_dev *dev, const char *name) diff --git a/ichspi.c b/ichspi.c index e1395ee..218e3b1 100644 --- a/ichspi.c +++ b/ichspi.c @@ -1561,7 +1561,7 @@ .erase = ich_hwseq_block_erase, }; -int ich_init_spi(struct pci_dev *dev, void *spibar, enum ich_chipset ich_gen) +int ich_init_spi(void *spibar, enum ich_chipset ich_gen) { int i; uint16_t tmp2; @@ -1828,7 +1828,7 @@ .write_aai = default_spi_write_aai, }; -int via_init_spi(struct pci_dev *dev, uint32_t mmio_base) +int via_init_spi(uint32_t mmio_base) { int i; diff --git a/programmer.h b/programmer.h index 9beaf98..fd9da96 100644 --- a/programmer.h +++ b/programmer.h @@ -655,8 +655,8 @@ /* ichspi.c */ #if CONFIG_INTERNAL == 1 extern uint32_t ichspi_bbar; -int ich_init_spi(struct pci_dev *dev, void *spibar, enum ich_chipset ich_generation); -int via_init_spi(struct pci_dev *dev, uint32_t mmio_base); +int ich_init_spi(void *spibar, enum ich_chipset ich_generation); +int via_init_spi(uint32_t mmio_base); /* amd_imc.c */ int amd_imc_shutdown(struct pci_dev *dev); -- To view, visit https://review.coreboot.org/21803 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: stable Gerrit-MessageType: newchange Gerrit-Change-Id: I01978e3e45332021f8967034bbaa907ef5f48d19 Gerrit-Change-Number: 21803 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de>

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Change in flashrom[stable]: Handle Intel Wildcat Point *LP* like Lynx Point LP
by Nico Huber (Code Review) 30 Sep '17

30 Sep '17

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/21802 Change subject: Handle Intel Wildcat Point *LP* like Lynx Point LP ...................................................................... Handle Intel Wildcat Point *LP* like Lynx Point LP The subtle difference was ignored when adding these chipsets. The integrated Wildcat Point LP PCH is documented in [1]. I'm not sure how to account for "Broadwell H" which seems not publicly documented. Maybe it's an unreleased HM9*, in which case the non-LP path should be correct. [1] Mobile 5th Generation Intel® Core(TM) Processor Family I/O, Intel® Core(TM) M Processor Family I/O, Mobile Intel® Pentium® Processor Family I/O, and Mobile Intel® Celeron® Processor Family I/O Datasheet Revision 004 Document Number: 330837 Original-Change-Id: I6b7ca3c0bde111b04ed7c745ed76d28d3d05f01c Original-Reviewed-on: https://review.coreboot.org/18883 Original-Reviewed-by: Youness Alaoui <snifikino(a)gmail.com> Original-Reviewed-by: David Hendricks <david.hendricks(a)gmail.com> Original-Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude(a)gmail.com> Original-Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Change-Id: Ib68704b4a720cb4539d4dd65495ccf6fead64724 Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- M chipset_enable.c M ich_descriptors.c M programmer.h 3 files changed, 21 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/02/21802/1 diff --git a/chipset_enable.c b/chipset_enable.c index 1191a4c..208cd3a 100644 --- a/chipset_enable.c +++ b/chipset_enable.c @@ -643,6 +643,7 @@ straps_names = straps_names_pch89_baytrail; break; case CHIPSET_8_SERIES_LYNX_POINT_LP: + case CHIPSET_9_SERIES_WILDCAT_POINT_LP: straps_names = straps_names_pch8_lp; break; case CHIPSET_8_SERIES_WELLSBURG: // FIXME: check datasheet @@ -661,7 +662,8 @@ bbs = (gcs >> 1) & 0x1; break; case CHIPSET_8_SERIES_LYNX_POINT_LP: - /* Lynx Point LP uses a single bit for BBS */ + case CHIPSET_9_SERIES_WILDCAT_POINT_LP: + /* LP PCHs use a single bit for BBS */ bbs = (gcs >> 10) & 0x1; break; default: @@ -796,6 +798,12 @@ static int enable_flash_pch9(struct pci_dev *dev, const char *name) { return enable_flash_ich_spi(dev, CHIPSET_9_SERIES_WILDCAT_POINT, 0xdc); +} + +/* Wildcat Point LP */ +static int enable_flash_pch9_lp(struct pci_dev *dev, const char *name) +{ + return enable_flash_ich_spi(dev, CHIPSET_9_SERIES_WILDCAT_POINT_LP, 0xdc); } /* Silvermont architecture: Bay Trail(-T/-I), Avoton/Rangeley. @@ -1787,13 +1795,13 @@ {0x8086, 0x9c43, NT, "Intel", "Lynx Point LP Premium", enable_flash_pch8_lp}, {0x8086, 0x9c45, NT, "Intel", "Lynx Point LP Mainstream", enable_flash_pch8_lp}, {0x8086, 0x9c47, NT, "Intel", "Lynx Point LP Value", enable_flash_pch8_lp}, - {0x8086, 0x9cc1, NT, "Intel", "Haswell U Sample", enable_flash_pch9}, - {0x8086, 0x9cc2, NT, "Intel", "Broadwell U Sample", enable_flash_pch9}, - {0x8086, 0x9cc3, NT, "Intel", "Broadwell U Premium", enable_flash_pch9}, - {0x8086, 0x9cc5, NT, "Intel", "Broadwell U Base", enable_flash_pch9}, - {0x8086, 0x9cc6, NT, "Intel", "Broadwell Y Sample", enable_flash_pch9}, - {0x8086, 0x9cc7, NT, "Intel", "Broadwell Y Premium", enable_flash_pch9}, - {0x8086, 0x9cc9, NT, "Intel", "Broadwell Y Base", enable_flash_pch9}, + {0x8086, 0x9cc1, NT, "Intel", "Haswell U Sample", enable_flash_pch9_lp}, + {0x8086, 0x9cc2, NT, "Intel", "Broadwell U Sample", enable_flash_pch9_lp}, + {0x8086, 0x9cc3, NT, "Intel", "Broadwell U Premium", enable_flash_pch9_lp}, + {0x8086, 0x9cc5, NT, "Intel", "Broadwell U Base", enable_flash_pch9_lp}, + {0x8086, 0x9cc6, NT, "Intel", "Broadwell Y Sample", enable_flash_pch9_lp}, + {0x8086, 0x9cc7, NT, "Intel", "Broadwell Y Premium", enable_flash_pch9_lp}, + {0x8086, 0x9cc9, NT, "Intel", "Broadwell Y Base", enable_flash_pch9_lp}, {0x8086, 0x9ccb, NT, "Intel", "Broadwell H", enable_flash_pch9}, {0x8086, 0x9d41, BAD, "Intel", "Sunrise Point (Skylake LP Sample)", NULL}, {0x8086, 0x9d43, BAD, "Intel", "Sunrise Point (Skylake-U Base)", NULL}, diff --git a/ich_descriptors.c b/ich_descriptors.c index 66dbb44..a12022c 100644 --- a/ich_descriptors.c +++ b/ich_descriptors.c @@ -139,7 +139,8 @@ case CHIPSET_8_SERIES_LYNX_POINT: case CHIPSET_8_SERIES_LYNX_POINT_LP: case CHIPSET_8_SERIES_WELLSBURG: - case CHIPSET_9_SERIES_WILDCAT_POINT: { + case CHIPSET_9_SERIES_WILDCAT_POINT: + case CHIPSET_9_SERIES_WILDCAT_POINT_LP: { uint8_t size_enc; if (idx == 0) { size_enc = desc->component.dens_new.comp1_density; @@ -183,6 +184,7 @@ case CHIPSET_8_SERIES_LYNX_POINT_LP: case CHIPSET_8_SERIES_WELLSBURG: case CHIPSET_9_SERIES_WILDCAT_POINT: + case CHIPSET_9_SERIES_WILDCAT_POINT_LP: return freq_str[value]; case CHIPSET_ICH_UNKNOWN: default: @@ -821,6 +823,7 @@ case CHIPSET_8_SERIES_LYNX_POINT_LP: case CHIPSET_8_SERIES_WELLSBURG: case CHIPSET_9_SERIES_WILDCAT_POINT: + case CHIPSET_9_SERIES_WILDCAT_POINT_LP: if (idx == 0) { size_enc = desc->component.dens_new.comp1_density; } else { diff --git a/programmer.h b/programmer.h index 1a6216a..9beaf98 100644 --- a/programmer.h +++ b/programmer.h @@ -649,6 +649,7 @@ CHIPSET_8_SERIES_LYNX_POINT_LP, CHIPSET_8_SERIES_WELLSBURG, CHIPSET_9_SERIES_WILDCAT_POINT, + CHIPSET_9_SERIES_WILDCAT_POINT_LP, }; /* ichspi.c */ -- To view, visit https://review.coreboot.org/21802 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: stable Gerrit-MessageType: newchange Gerrit-Change-Id: Ib68704b4a720cb4539d4dd65495ccf6fead64724 Gerrit-Change-Number: 21802 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de>

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Change in flashrom[stable]: ich_descriptors: Fix more odd +1s
by Nico Huber (Code Review) 30 Sep '17

30 Sep '17

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/21801 Change subject: ich_descriptors: Fix more odd +1s ...................................................................... ich_descriptors: Fix more odd +1s +1 on everything doesn't make software greater per se. v2: o Fix another +1. o Amend style of similar (not +1 suffering) code, too. Original-Change-Id: Ifa5455c999e90ff9121aed29f542d71ac9ca2b1c Original-Reviewed-on: https://review.coreboot.org/19044 Original-Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Original-Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude(a)gmail.com> Original-Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Change-Id: I218475648010430f17942224f7a805e821115139 Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- M ich_descriptors.c 1 file changed, 7 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/01/21801/1 diff --git a/ich_descriptors.c b/ich_descriptors.c index ecc2b95..66dbb44 100644 --- a/ich_descriptors.c +++ b/ich_descriptors.c @@ -611,26 +611,24 @@ unsigned int i, max_count; msg_pdbg2("=== Softstraps ===\n"); - if (sizeof(desc->north.STRPs) / 4 + 1 < desc->content.MSL) { - max_count = sizeof(desc->north.STRPs) / 4 + 1; + max_count = min(ARRAY_SIZE(desc->north.STRPs), desc->content.MSL); + if (max_count < desc->content.MSL) { msg_pdbg2("MSL (%u) is greater than the current maximum of %u entries.\n", - desc->content.MSL, max_count + 1); + desc->content.MSL, max_count); msg_pdbg2("Only the first %u entries will be printed.\n", max_count); - } else - max_count = desc->content.MSL; + } msg_pdbg2("--- North/MCH/PROC (%d entries) ---\n", max_count); for (i = 0; i < max_count; i++) msg_pdbg2("STRP%-2d = 0x%08x\n", i, desc->north.STRPs[i]); msg_pdbg2("\n"); - if (sizeof(desc->south.STRPs) / 4 < desc->content.ISL) { - max_count = sizeof(desc->south.STRPs) / 4; + max_count = min(ARRAY_SIZE(desc->south.STRPs), desc->content.ISL); + if (max_count < desc->content.ISL) { msg_pdbg2("ISL (%u) is greater than the current maximum of %u entries.\n", desc->content.ISL, max_count); msg_pdbg2("Only the first %u entries will be printed.\n", max_count); - } else - max_count = desc->content.ISL; + } msg_pdbg2("--- South/ICH/PCH (%d entries) ---\n", max_count); for (i = 0; i < max_count; i++) -- To view, visit https://review.coreboot.org/21801 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: stable Gerrit-MessageType: newchange Gerrit-Change-Id: I218475648010430f17942224f7a805e821115139 Gerrit-Change-Number: 21801 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de>

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Change in flashrom[stable]: dediprog: Reimplement target chip option
by build bot (Jenkins) (Code Review) 30 Sep '17

30 Sep '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21780 ) Change subject: dediprog: Reimplement target chip option ...................................................................... Patch Set 1: Verified-1 Build Failed https://qa.coreboot.org/job/flashrom-customrules/575/ : FAILURE https://qa.coreboot.org/job/flashrom_gerrit/520/ : SUCCESS -- To view, visit https://review.coreboot.org/21780 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: stable Gerrit-MessageType: comment Gerrit-Change-Id: I94576967e2892e08295daa829caabace5a367fa0 Gerrit-Change-Number: 21780 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 30 Sep 2017 20:48:37 +0000 Gerrit-HasComments: No

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Change in flashrom[stable]: ich_descriptors: Fix range checks for dumps
by Nico Huber (Code Review) 30 Sep '17

30 Sep '17

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/21800 Change subject: ich_descriptors: Fix range checks for dumps ...................................................................... ich_descriptors: Fix range checks for dumps These explicit off-by-one calculations were... off-by-one. Original-Change-Id: If57c92ba28f91c4d72123ef0cfd2d9d5ac0a0656 Original-Reviewed-on: https://review.coreboot.org/19031 Original-Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Original-Reviewed-by: David Hendricks <david.hendricks(a)gmail.com> Change-Id: I8ff9e54aba01aea6e2714a13a3efe0d2bb9714de Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- M ich_descriptors.c 1 file changed, 5 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/00/21800/1 diff --git a/ich_descriptors.c b/ich_descriptors.c index 4af8764..ecc2b95 100644 --- a/ich_descriptors.c +++ b/ich_descriptors.c @@ -719,7 +719,7 @@ } /* map */ - if (len < (4 + pch_bug_offset) * 4 - 1) + if (len < (4 + pch_bug_offset) * 4) return ICH_RET_OOB; desc->content.FLVALSIG = dump[0 + pch_bug_offset]; desc->content.FLMAP0 = dump[1 + pch_bug_offset]; @@ -727,14 +727,14 @@ desc->content.FLMAP2 = dump[3 + pch_bug_offset]; /* component */ - if (len < (getFCBA(&desc->content) + 3 * 4 - 1)) + if (len < getFCBA(&desc->content) + 3 * 4) return ICH_RET_OOB; desc->component.FLCOMP = dump[(getFCBA(&desc->content) >> 2) + 0]; desc->component.FLILL = dump[(getFCBA(&desc->content) >> 2) + 1]; desc->component.FLPB = dump[(getFCBA(&desc->content) >> 2) + 2]; /* region */ - if (len < (getFRBA(&desc->content) + 5 * 4 - 1)) + if (len < getFRBA(&desc->content) + 5 * 4) return ICH_RET_OOB; desc->region.FLREGs[0] = dump[(getFRBA(&desc->content) >> 2) + 0]; desc->region.FLREGs[1] = dump[(getFRBA(&desc->content) >> 2) + 1]; @@ -743,7 +743,7 @@ desc->region.FLREGs[4] = dump[(getFRBA(&desc->content) >> 2) + 4]; /* master */ - if (len < (getFMBA(&desc->content) + 3 * 4 - 1)) + if (len < getFMBA(&desc->content) + 3 * 4) return ICH_RET_OOB; desc->master.FLMSTR1 = dump[(getFMBA(&desc->content) >> 2) + 0]; desc->master.FLMSTR2 = dump[(getFMBA(&desc->content) >> 2) + 1]; @@ -758,7 +758,7 @@ * the maximum of 255 gives us 127.5 SPI components(!?) 8 bytes each. A * check ensures that the maximum offset actually accessed is available. */ - if (len < (getVTBA(&desc->upper) + (desc->upper.VTL / 2 * 8) - 1)) + if (len < getVTBA(&desc->upper) + (desc->upper.VTL / 2 * 8)) return ICH_RET_OOB; for (i = 0; i < desc->upper.VTL/2; i++) { -- To view, visit https://review.coreboot.org/21800 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: stable Gerrit-MessageType: newchange Gerrit-Change-Id: I8ff9e54aba01aea6e2714a13a3efe0d2bb9714de Gerrit-Change-Number: 21800 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de>

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Change in flashrom[stable]: ich_descriptors_tool: Fix an off-by-one
by Nico Huber (Code Review) 30 Sep '17

30 Sep '17

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/21799 Change subject: ich_descriptors_tool: Fix an off-by-one ...................................................................... ich_descriptors_tool: Fix an off-by-one Original-Change-Id: I008abd78c7c42bf3f17e68c192cd79dd427c5cb5 Original-Reviewed-on: https://review.coreboot.org/19045 Original-Tested-by: build bot (Jenkins) Original-Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Change-Id: If494234e9529d83564c21799bf8ea424ae633667 Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- M util/ich_descriptors_tool/ich_descriptors_tool.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/99/21799/1 diff --git a/util/ich_descriptors_tool/ich_descriptors_tool.c b/util/ich_descriptors_tool/ich_descriptors_tool.c index 0da27d2..250abf0 100644 --- a/util/ich_descriptors_tool/ich_descriptors_tool.c +++ b/util/ich_descriptors_tool/ich_descriptors_tool.c @@ -230,7 +230,7 @@ prettyprint_ich_descriptors(cs, &desc); pMAC = (uint8_t *) &buf[ICH_FREG_BASE(desc.region.reg3_base) >> 2]; - if (len >= ICH_FREG_BASE(desc.region.reg3_base) + 5 && pMAC[0] != 0xff) + if (len >= ICH_FREG_BASE(desc.region.reg3_base) + 6 && pMAC[0] != 0xff) printf("The MAC address might be at offset 0x%x: " "%02x:%02x:%02x:%02x:%02x:%02x\n", ICH_FREG_BASE(desc.region.reg3_base), -- To view, visit https://review.coreboot.org/21799 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: stable Gerrit-MessageType: newchange Gerrit-Change-Id: If494234e9529d83564c21799bf8ea424ae633667 Gerrit-Change-Number: 21799 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de>

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Change in flashrom[stable]: dediprog: Fix bug where too many transfers would be queued
by build bot (Jenkins) (Code Review) 30 Sep '17

30 Sep '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21781 ) Change subject: dediprog: Fix bug where too many transfers would be queued ...................................................................... Patch Set 1: Verified-1 Build Failed https://qa.coreboot.org/job/flashrom-customrules/576/ : FAILURE https://qa.coreboot.org/job/flashrom_gerrit/521/ : SUCCESS -- To view, visit https://review.coreboot.org/21781 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: stable Gerrit-MessageType: comment Gerrit-Change-Id: Ie0d516f0fb2923a772a0ca7020ca5118ab260dc5 Gerrit-Change-Number: 21781 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 30 Sep 2017 20:48:34 +0000 Gerrit-HasComments: No

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Change in flashrom[stable]: flashchips: Add untested Winbond W25Q128.W
by Nico Huber (Code Review) 30 Sep '17

30 Sep '17

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/21798 Change subject: flashchips: Add untested Winbond W25Q128.W ...................................................................... flashchips: Add untested Winbond W25Q128.W Only difference to its sibling W25Q128.V seems to be the supply voltage. Original-Change-Id: I34ce7f1bdd0d2fb1b065031e5a689bb16ffc70db Original-Reviewed-on: https://review.coreboot.org/19436 Original-Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Original-Reviewed-by: David Hendricks <david.hendricks(a)gmail.com> Change-Id: Ie4f996698b0807ec3e97c8dec3fcd4e3c16557c2 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M flashchips.c M flashchips.h 2 files changed, 41 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/98/21798/1 diff --git a/flashchips.c b/flashchips.c index 40b6b8e..7ef361b 100644 --- a/flashchips.c +++ b/flashchips.c @@ -14825,6 +14825,46 @@ { .vendor = "Winbond", + .name = "W25Q128.W", + .bustype = BUS_SPI, + .manufacture_id = WINBOND_NEX_ID, + .model_id = WINBOND_NEX_W25Q128_W, + .total_size = 16384, + .page_size = 256, + /* supports SFDP */ + /* OTP: 1024B total, 256B reserved; read 0x48; write 0x42, erase 0x44, read ID 0x4B */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_QPI, + .tested = TEST_UNTESTED, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 4096} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {32 * 1024, 512} }, + .block_erase = spi_block_erase_52, + }, { + .eraseblocks = { {64 * 1024, 256} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {16 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {16 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, + .printlock = spi_prettyprint_status_register_plain, /* TODO: improve */ + .unlock = spi_disable_blockprotect, + .write = spi_chip_write_256, + .read = spi_chip_read, + .voltage = {1650, 1950}, + }, + + { + .vendor = "Winbond", .name = "W25X10", .bustype = BUS_SPI, .manufacture_id = WINBOND_NEX_ID, diff --git a/flashchips.h b/flashchips.h index 9ffb30f..28a155d 100644 --- a/flashchips.h +++ b/flashchips.h @@ -906,7 +906,7 @@ #define WINBOND_NEX_W25Q16_W 0x6015 /* W25Q16DW */ #define WINBOND_NEX_W25Q32_W 0x6016 /* W25Q32DW; W25Q32FV in QPI mode */ #define WINBOND_NEX_W25Q64_W 0x6017 /* W25Q64DW; W25Q64FV in QPI mode */ -#define WINBOND_NEX_W25Q128_W 0x6018 /* (No W version known) W25Q128FV in QPI mode */ +#define WINBOND_NEX_W25Q128_W 0x6018 /* W25Q128FW; W25Q128FV in QPI mode */ #define WINBOND_ID 0xDA /* Winbond */ #define WINBOND_W19B160BB 0x49 -- To view, visit https://review.coreboot.org/21798 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: stable Gerrit-MessageType: newchange Gerrit-Change-Id: Ie4f996698b0807ec3e97c8dec3fcd4e3c16557c2 Gerrit-Change-Number: 21798 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de>

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Change in flashrom[stable]: util: Add CH341a to z60_flashrom.rules
by build bot (Jenkins) (Code Review) 30 Sep '17

30 Sep '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21778 ) Change subject: util: Add CH341a to z60_flashrom.rules ...................................................................... Patch Set 1: Verified-1 Build Failed https://qa.coreboot.org/job/flashrom-customrules/574/ : FAILURE https://qa.coreboot.org/job/flashrom_gerrit/518/ : SUCCESS -- To view, visit https://review.coreboot.org/21778 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: stable Gerrit-MessageType: comment Gerrit-Change-Id: Id1ceebbf406f81a28bd6dae44acd6e569e0c834c Gerrit-Change-Number: 21778 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 30 Sep 2017 20:48:30 +0000 Gerrit-HasComments: No

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Change in flashrom[stable]: Whitelist Roda/RV11 laptop
by Nico Huber (Code Review) 30 Sep '17

30 Sep '17

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/21797 Change subject: Whitelist Roda/RV11 laptop ...................................................................... Whitelist Roda/RV11 laptop Original-Change-Id: I036c1f8cb914c8e3cca9d17eb221b582d7414ae9 Original-Reviewed-on: https://review.coreboot.org/18739 Original-Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Original-Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Change-Id: I03e711894b00eca11abcf2eca7512b833550679d Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- M board_enable.c 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/97/21797/1 diff --git a/board_enable.c b/board_enable.c index c85bd15..b6e17ef 100644 --- a/board_enable.c +++ b/board_enable.c @@ -2458,6 +2458,7 @@ {0x10DE, 0x0360, 0x1462, 0x7250, 0x10DE, 0x0368, 0x1462, 0x7250, NULL, NULL, NULL, P3, "MSI", "MS-7250 (K9N SLI)", 0, OK, nvidia_mcp_gpio2_raise}, {0x1011, 0x0019, 0xaa55, 0xaa55, 0x8086, 0x7190, 0, 0, NULL, NULL, NULL, P3, "Nokia", "IP530", 0, OK, fdc37b787_gpio50_raise_3f0}, {0x8086, 0x3B30, 0x1025, 0x0379, 0x8086, 0x3B09, 0x1025, 0x0379, "^EasyNote LM85$", NULL, NULL, P2, "Packard Bell","EasyNote LM85", 0, OK, p2_whitelist_laptop}, + {0x8086, 0x0154, 0x8086, 0x0154, 0x8086, 0x1e55, 0x8086, 0x1e55, "RV11$", "Roda", "Lizard RV11", P2, "Roda", "RV11", 0, OK, p2_whitelist_laptop}, {0x8086, 0x24d3, 0x144d, 0xb025, 0x8086, 0x1050, 0x144d, 0xb025, NULL, NULL, NULL, P3, "Samsung", "Polaris 32", 0, OK, intel_ich_gpio21_raise}, {0x1106, 0x3099, 0, 0, 0x1106, 0x3074, 0, 0, NULL, "shuttle", "ak31", P3, "Shuttle", "AK31", 0, OK, w836xx_memw_enable_2e}, {0x1106, 0x3104, 0x1297, 0xa238, 0x1106, 0x3059, 0x1297, 0xc063, NULL, NULL, NULL, P3, "Shuttle", "AK38N", 256, OK, NULL}, -- To view, visit https://review.coreboot.org/21797 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: stable Gerrit-MessageType: newchange Gerrit-Change-Id: I03e711894b00eca11abcf2eca7512b833550679d Gerrit-Change-Number: 21797 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de>

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flashrom-gerrit September 2017