September 2017 - flashrom-gerrit

Change in flashrom[stable]: Make image parameter of cb_check_image const
by build bot (Jenkins) (Code Review) 30 Sep '17

30 Sep '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21783 ) Change subject: Make image parameter of cb_check_image const ...................................................................... Patch Set 1: Verified-1 Build Failed https://qa.coreboot.org/job/flashrom-customrules/579/ : FAILURE https://qa.coreboot.org/job/flashrom_gerrit/524/ : SUCCESS -- To view, visit https://review.coreboot.org/21783 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: stable Gerrit-MessageType: comment Gerrit-Change-Id: I605386b6e903acfce85b19ad1e029e62e88df839 Gerrit-Change-Number: 21783 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 30 Sep 2017 20:48:53 +0000 Gerrit-HasComments: No

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Change in flashrom[stable]: chipset_enable: Set 100 series chipsets to NT
by Nico Huber (Code Review) 30 Sep '17

30 Sep '17

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/21810 Change subject: chipset_enable: Set 100 series chipsets to NT ...................................................................... chipset_enable: Set 100 series chipsets to NT Original-Change-Id: I9376a0c180b7e73751fbd3c8c37b693d358cbfb8 Original-Reviewed-on: https://review.coreboot.org/19047 Original-Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Original-Reviewed-by: David Hendricks <david.hendricks(a)gmail.com> Original-Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Change-Id: I2635d01245856136cf4dc8d723378160b1978004 Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- M chipset_enable.c 1 file changed, 30 insertions(+), 30 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/10/21810/1 diff --git a/chipset_enable.c b/chipset_enable.c index a85ae21..20d2662 100644 --- a/chipset_enable.c +++ b/chipset_enable.c @@ -1880,36 +1880,36 @@ {0x8086, 0x9cc7, NT, "Intel", "Broadwell Y Premium", enable_flash_pch9_lp}, {0x8086, 0x9cc9, NT, "Intel", "Broadwell Y Base", enable_flash_pch9_lp}, {0x8086, 0x9ccb, NT, "Intel", "Broadwell H", enable_flash_pch9}, - {0x8086, 0x9d41, BAD, "Intel", "Skylake / Kaby Lake Sample", enable_flash_pch100}, - {0x8086, 0x9d43, BAD, "Intel", "Skylake U Base", enable_flash_pch100}, - {0x8086, 0x9d46, BAD, "Intel", "Skylake Y Premium", enable_flash_pch100}, - {0x8086, 0x9d48, BAD, "Intel", "Skylake U Premium", enable_flash_pch100}, - {0x8086, 0x9d4b, BAD, "Intel", "Kaby Lake Y w/ iHDCP2.2 Prem.", enable_flash_pch100}, - {0x8086, 0x9d4e, BAD, "Intel", "Kaby Lake U w/ iHDCP2.2 Prem.", enable_flash_pch100}, - {0x8086, 0x9d50, BAD, "Intel", "Kaby Lake U w/ iHDCP2.2 Base", enable_flash_pch100}, - {0x8086, 0x9d51, BAD, "Intel", "Kabe Lake w/ iHDCP2.2 Sample", enable_flash_pch100}, - {0x8086, 0x9d53, BAD, "Intel", "Kaby Lake U Base", enable_flash_pch100}, - {0x8086, 0x9d56, BAD, "Intel", "Kaby Lake Y Premium", enable_flash_pch100}, - {0x8086, 0x9d58, BAD, "Intel", "Kaby Lake U Premium", enable_flash_pch100}, - {0x8086, 0xa141, BAD, "Intel", "Sunrise Point Desktop Sample", enable_flash_pch100}, - {0x8086, 0xa142, BAD, "Intel", "Sunrise Point Unknown Sample", enable_flash_pch100}, - {0x8086, 0xa143, BAD, "Intel", "H110", enable_flash_pch100}, - {0x8086, 0xa144, BAD, "Intel", "H170", enable_flash_pch100}, - {0x8086, 0xa145, BAD, "Intel", "Z170", enable_flash_pch100}, - {0x8086, 0xa146, BAD, "Intel", "Q170", enable_flash_pch100}, - {0x8086, 0xa147, BAD, "Intel", "Q150", enable_flash_pch100}, - {0x8086, 0xa148, BAD, "Intel", "B150", enable_flash_pch100}, - {0x8086, 0xa149, BAD, "Intel", "C236", enable_flash_pch100}, - {0x8086, 0xa14a, BAD, "Intel", "C232", enable_flash_pch100}, - {0x8086, 0xa14b, BAD, "Intel", "Sunrise Point Server Sample", enable_flash_pch100}, - {0x8086, 0xa14d, BAD, "Intel", "QM170", enable_flash_pch100}, - {0x8086, 0xa14e, BAD, "Intel", "HM170", enable_flash_pch100}, - {0x8086, 0xa150, BAD, "Intel", "CM236", enable_flash_pch100}, - {0x8086, 0xa151, BAD, "Intel", "QMS180", enable_flash_pch100}, - {0x8086, 0xa152, BAD, "Intel", "HM175", enable_flash_pch100}, - {0x8086, 0xa153, BAD, "Intel", "QM175", enable_flash_pch100}, - {0x8086, 0xa154, BAD, "Intel", "CM238", enable_flash_pch100}, - {0x8086, 0xa155, BAD, "Intel", "QMU185", enable_flash_pch100}, + {0x8086, 0x9d41, NT, "Intel", "Skylake / Kaby Lake Sample", enable_flash_pch100}, + {0x8086, 0x9d43, NT, "Intel", "Skylake U Base", enable_flash_pch100}, + {0x8086, 0x9d46, NT, "Intel", "Skylake Y Premium", enable_flash_pch100}, + {0x8086, 0x9d48, NT, "Intel", "Skylake U Premium", enable_flash_pch100}, + {0x8086, 0x9d4b, NT, "Intel", "Kaby Lake Y w/ iHDCP2.2 Prem.", enable_flash_pch100}, + {0x8086, 0x9d4e, NT, "Intel", "Kaby Lake U w/ iHDCP2.2 Prem.", enable_flash_pch100}, + {0x8086, 0x9d50, NT, "Intel", "Kaby Lake U w/ iHDCP2.2 Base", enable_flash_pch100}, + {0x8086, 0x9d51, NT, "Intel", "Kabe Lake w/ iHDCP2.2 Sample", enable_flash_pch100}, + {0x8086, 0x9d53, NT, "Intel", "Kaby Lake U Base", enable_flash_pch100}, + {0x8086, 0x9d56, NT, "Intel", "Kaby Lake Y Premium", enable_flash_pch100}, + {0x8086, 0x9d58, NT, "Intel", "Kaby Lake U Premium", enable_flash_pch100}, + {0x8086, 0xa141, NT, "Intel", "Sunrise Point Desktop Sample", enable_flash_pch100}, + {0x8086, 0xa142, NT, "Intel", "Sunrise Point Unknown Sample", enable_flash_pch100}, + {0x8086, 0xa143, NT, "Intel", "H110", enable_flash_pch100}, + {0x8086, 0xa144, NT, "Intel", "H170", enable_flash_pch100}, + {0x8086, 0xa145, NT, "Intel", "Z170", enable_flash_pch100}, + {0x8086, 0xa146, NT, "Intel", "Q170", enable_flash_pch100}, + {0x8086, 0xa147, NT, "Intel", "Q150", enable_flash_pch100}, + {0x8086, 0xa148, NT, "Intel", "B150", enable_flash_pch100}, + {0x8086, 0xa149, NT, "Intel", "C236", enable_flash_pch100}, + {0x8086, 0xa14a, NT, "Intel", "C232", enable_flash_pch100}, + {0x8086, 0xa14b, NT, "Intel", "Sunrise Point Server Sample", enable_flash_pch100}, + {0x8086, 0xa14d, NT, "Intel", "QM170", enable_flash_pch100}, + {0x8086, 0xa14e, NT, "Intel", "HM170", enable_flash_pch100}, + {0x8086, 0xa150, NT, "Intel", "CM236", enable_flash_pch100}, + {0x8086, 0xa151, NT, "Intel", "QMS180", enable_flash_pch100}, + {0x8086, 0xa152, NT, "Intel", "HM175", enable_flash_pch100}, + {0x8086, 0xa153, NT, "Intel", "QM175", enable_flash_pch100}, + {0x8086, 0xa154, NT, "Intel", "CM238", enable_flash_pch100}, + {0x8086, 0xa155, NT, "Intel", "QMU185", enable_flash_pch100}, #endif {0}, }; -- To view, visit https://review.coreboot.org/21810 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: stable Gerrit-MessageType: newchange Gerrit-Change-Id: I2635d01245856136cf4dc8d723378160b1978004 Gerrit-Change-Number: 21810 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de>

1 0

Change in flashrom[stable]: Remove undefined behavior
by build bot (Jenkins) (Code Review) 30 Sep '17

30 Sep '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21782 ) Change subject: Remove undefined behavior ...................................................................... Patch Set 1: Verified-1 Build Failed https://qa.coreboot.org/job/flashrom-customrules/577/ : FAILURE https://qa.coreboot.org/job/flashrom_gerrit/522/ : SUCCESS -- To view, visit https://review.coreboot.org/21782 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: stable Gerrit-MessageType: comment Gerrit-Change-Id: Ib8bb468622fa158d3bf5ef797049ecb549cc1f40 Gerrit-Change-Number: 21782 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 30 Sep 2017 20:48:52 +0000 Gerrit-HasComments: No

1 0

Change in flashrom[stable]: ich_descriptors: Update for Intel Skylake
by Nico Huber (Code Review) 30 Sep '17

30 Sep '17

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/21809 Change subject: ich_descriptors: Update for Intel Skylake ...................................................................... ich_descriptors: Update for Intel Skylake Interpretation of component clocks changed. Also more regions and more masters are supported now. The number of regions (NR) is now static per chipset (10 in the 100 Series case) and not coded into the descriptor any more. v2: o Use guess_ich_chipset() for read_ich_descriptors_from_dump(). o Update region extraction in `ich_descriptors_tool`. TEST=Run `ich_descriptors_tool` over a 100 Series dump and checked that output looks sane. Run `ich_descriptors_tool` over dumps of five different older systems (1 x Sandy Bridge, 3 x Ivy Bridge, 1 x Haswell). Beside whitespace changes, regions not accounted by `NR` are not printed any more. Original-Change-Id: Idd60a857d1ecffcb2e437af21134d9de44dcceb8 Original-Reviewed-on: https://review.coreboot.org/18973 Original-Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Original-Reviewed-by: David Hendricks <david.hendricks(a)gmail.com> Original-Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Change-Id: I34ac844dd414db6f8957763846cbfba75301bae5 Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- M ich_descriptors.c M ich_descriptors.h M util/ich_descriptors_tool/ich_descriptors_tool.c 3 files changed, 265 insertions(+), 163 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/09/21809/1 diff --git a/ich_descriptors.c b/ich_descriptors.c index 4c18dfa..a2aa940 100644 --- a/ich_descriptors.c +++ b/ich_descriptors.c @@ -42,6 +42,36 @@ #define min(a, b) (((a) < (b)) ? (a) : (b)) #endif +ssize_t ich_number_of_regions(const enum ich_chipset cs, const struct ich_desc_content *const cont) +{ + switch (cs) { + case CHIPSET_100_SERIES_SUNRISE_POINT: + return 10; + case CHIPSET_9_SERIES_WILDCAT_POINT_LP: + case CHIPSET_9_SERIES_WILDCAT_POINT: + case CHIPSET_8_SERIES_LYNX_POINT_LP: + case CHIPSET_8_SERIES_LYNX_POINT: + case CHIPSET_8_SERIES_WELLSBURG: + if (cont->NR <= 6) + return cont->NR + 1; + else + return -1; + default: + if (cont->NR <= 4) + return cont->NR + 1; + else + return -1; + } +} + +ssize_t ich_number_of_masters(const enum ich_chipset cs, const struct ich_desc_content *const cont) +{ + if (cont->NM < MAX_NUM_MASTERS) + return cont->NM + 1; + else + return -1; +} + void prettyprint_ich_reg_vscc(uint32_t reg_val, int verbosity, bool print_vcl) { print(verbosity, "BES=0x%x, ", (reg_val & VSCC_BES) >> VSCC_BES_OFF); @@ -62,10 +92,10 @@ void prettyprint_ich_descriptors(enum ich_chipset cs, const struct ich_descriptors *desc) { - prettyprint_ich_descriptor_content(&desc->content); + prettyprint_ich_descriptor_content(cs, &desc->content); prettyprint_ich_descriptor_component(cs, desc); - prettyprint_ich_descriptor_region(desc); - prettyprint_ich_descriptor_master(&desc->master); + prettyprint_ich_descriptor_region(cs, desc); + prettyprint_ich_descriptor_master(cs, desc); #ifdef ICH_DESCRIPTORS_FROM_DUMP_ONLY if (cs >= CHIPSET_ICH8) { prettyprint_ich_descriptor_upper_map(&desc->upper); @@ -74,7 +104,7 @@ #endif /* ICH_DESCRIPTORS_FROM_DUMP_ONLY */ } -void prettyprint_ich_descriptor_content(const struct ich_desc_content *cont) +void prettyprint_ich_descriptor_content(enum ich_chipset cs, const struct ich_desc_content *cont) { msg_pdbg2("=== Content Section ===\n"); msg_pdbg2("FLVALSIG 0x%08x\n", cont->FLVALSIG); @@ -84,16 +114,16 @@ msg_pdbg2("\n"); msg_pdbg2("--- Details ---\n"); - msg_pdbg2("NR (Number of Regions): %5d\n", cont->NR + 1); - msg_pdbg2("FRBA (Flash Region Base Address): 0x%03x\n", getFRBA(cont)); - msg_pdbg2("NC (Number of Components): %5d\n", cont->NC + 1); - msg_pdbg2("FCBA (Flash Component Base Address): 0x%03x\n", getFCBA(cont)); - msg_pdbg2("ISL (ICH/PCH Strap Length): %5d\n", cont->ISL); - msg_pdbg2("FISBA/FPSBA (Flash ICH/PCH Strap Base Address): 0x%03x\n", getFISBA(cont)); - msg_pdbg2("NM (Number of Masters): %5d\n", cont->NM + 1); - msg_pdbg2("FMBA (Flash Master Base Address): 0x%03x\n", getFMBA(cont)); - msg_pdbg2("MSL/PSL (MCH/PROC Strap Length): %5d\n", cont->MSL); - msg_pdbg2("FMSBA (Flash MCH/PROC Strap Base Address): 0x%03x\n", getFMSBA(cont)); + msg_pdbg2("NR (Number of Regions): %5zd\n", ich_number_of_regions(cs, cont)); + msg_pdbg2("FRBA (Flash Region Base Address): 0x%03x\n", getFRBA(cont)); + msg_pdbg2("NC (Number of Components): %5d\n", cont->NC + 1); + msg_pdbg2("FCBA (Flash Component Base Address): 0x%03x\n", getFCBA(cont)); + msg_pdbg2("ISL (ICH/PCH Strap Length): %5d\n", cont->ISL); + msg_pdbg2("FISBA/FPSBA (Flash ICH/PCH Strap Base Address): 0x%03x\n", getFISBA(cont)); + msg_pdbg2("NM (Number of Masters): %5zd\n", ich_number_of_masters(cs, cont)); + msg_pdbg2("FMBA (Flash Master Base Address): 0x%03x\n", getFMBA(cont)); + msg_pdbg2("MSL/PSL (MCH/PROC Strap Length): %5d\n", cont->MSL); + msg_pdbg2("FMSBA (Flash MCH/PROC Strap Base Address): 0x%03x\n", getFMSBA(cont)); msg_pdbg2("\n"); } @@ -140,7 +170,8 @@ case CHIPSET_8_SERIES_LYNX_POINT_LP: case CHIPSET_8_SERIES_WELLSBURG: case CHIPSET_9_SERIES_WILDCAT_POINT: - case CHIPSET_9_SERIES_WILDCAT_POINT_LP: { + case CHIPSET_9_SERIES_WILDCAT_POINT_LP: + case CHIPSET_100_SERIES_SUNRISE_POINT: { uint8_t size_enc; if (idx == 0) { size_enc = desc->component.dens_new.comp1_density; @@ -159,7 +190,7 @@ static const char *pprint_freq(enum ich_chipset cs, uint8_t value) { - static const char * const freq_str[8] = { + static const char *const freq_str[2][8] = { { "20 MHz", /* 000 */ "33 MHz", /* 001 */ "reserved", /* 010 */ @@ -168,7 +199,16 @@ "reserved", /* 101 */ "reserved", /* 110 */ "reserved" /* 111 */ - }; + }, { + "reserved", /* 000 */ + "reserved", /* 001 */ + "48 MHz", /* 010 */ + "reserved", /* 011 */ + "30 MHz", /* 100 */ + "reserved", /* 101 */ + "17 MHz", /* 110 */ + "reserved" /* 111 */ + } }; switch (cs) { case CHIPSET_ICH8: @@ -185,7 +225,9 @@ case CHIPSET_8_SERIES_WELLSBURG: case CHIPSET_9_SERIES_WILDCAT_POINT: case CHIPSET_9_SERIES_WILDCAT_POINT_LP: - return freq_str[value]; + return freq_str[0][value]; + case CHIPSET_100_SERIES_SUNRISE_POINT: + return freq_str[1][value]; case CHIPSET_ICH_UNKNOWN: default: return "unknown"; @@ -198,6 +240,8 @@ msg_pdbg2("=== Component Section ===\n"); msg_pdbg2("FLCOMP 0x%08x\n", desc->component.FLCOMP); msg_pdbg2("FLILL 0x%08x\n", desc->component.FLILL ); + if (cs == CHIPSET_100_SERIES_SUNRISE_POINT) + msg_pdbg2("FLILL1 0x%08x\n", desc->component.FLILL1); msg_pdbg2("\n"); msg_pdbg2("--- Details ---\n"); @@ -216,9 +260,10 @@ if (cs > CHIPSET_6_SERIES_COUGAR_POINT) msg_pdbg2("Dual Output Fast Read Support: %sabled\n", desc->component.modes.dual_output ? "dis" : "en"); - if (desc->component.FLILL == 0) + if (desc->component.FLILL == 0 && + (cs != CHIPSET_100_SERIES_SUNRISE_POINT || desc->component.FLILL1 == 0)) { msg_pdbg2("No forbidden opcodes.\n"); - else { + } else { msg_pdbg2("Invalid instruction 0: 0x%02x\n", desc->component.invalid_instr0); msg_pdbg2("Invalid instruction 1: 0x%02x\n", @@ -227,76 +272,116 @@ desc->component.invalid_instr2); msg_pdbg2("Invalid instruction 3: 0x%02x\n", desc->component.invalid_instr3); + if (cs == CHIPSET_100_SERIES_SUNRISE_POINT) { + msg_pdbg2("Invalid instruction 4: 0x%02x\n", + desc->component.invalid_instr4); + msg_pdbg2("Invalid instruction 5: 0x%02x\n", + desc->component.invalid_instr5); + msg_pdbg2("Invalid instruction 6: 0x%02x\n", + desc->component.invalid_instr6); + msg_pdbg2("Invalid instruction 7: 0x%02x\n", + desc->component.invalid_instr7); + } } msg_pdbg2("\n"); } static void pprint_freg(const struct ich_desc_region *reg, uint32_t i) { - static const char *const region_names[5] = { - "Descr.", "BIOS", "ME", "GbE", "Platf." + static const char *const region_names[] = { + "Descr.", "BIOS", "ME", "GbE", "Platf.", "unknown", "unknown", "unknown", + "EC", "unknown", }; - if (i >= 5) { + if (i >= ARRAY_SIZE(region_names)) { msg_pdbg2("%s: region index too high.\n", __func__); return; } uint32_t base = ICH_FREG_BASE(reg->FLREGs[i]); uint32_t limit = ICH_FREG_LIMIT(reg->FLREGs[i]); - msg_pdbg2("Region %d (%-6s) ", i, region_names[i]); + msg_pdbg2("Region %d (%-7s) ", i, region_names[i]); if (base > limit) msg_pdbg2("is unused.\n"); else msg_pdbg2("0x%08x - 0x%08x\n", base, limit); } -void prettyprint_ich_descriptor_region(const struct ich_descriptors *desc) +void prettyprint_ich_descriptor_region(const enum ich_chipset cs, const struct ich_descriptors *const desc) { - uint8_t i; - uint8_t nr = desc->content.NR + 1; + size_t i; + const ssize_t nr = ich_number_of_regions(cs, &desc->content); msg_pdbg2("=== Region Section ===\n"); - if (nr > 5) { + if (nr < 0) { msg_pdbg2("%s: number of regions too high (%d).\n", __func__, - nr); + desc->content.NR + 1); return; } - for (i = 0; i < 5; i++) - msg_pdbg2("FLREG%d 0x%08x\n", i, desc->region.FLREGs[i]); + for (i = 0; i < nr; i++) + msg_pdbg2("FLREG%zu 0x%08x\n", i, desc->region.FLREGs[i]); msg_pdbg2("\n"); msg_pdbg2("--- Details ---\n"); - for (i = 0; i < 5; i++) + for (i = 0; i < nr; i++) pprint_freg(&desc->region, i); msg_pdbg2("\n"); } -void prettyprint_ich_descriptor_master(const struct ich_desc_master *mstr) +void prettyprint_ich_descriptor_master(const enum ich_chipset cs, const struct ich_descriptors *const desc) { + size_t i; + const ssize_t nm = ich_number_of_masters(cs, &desc->content); msg_pdbg2("=== Master Section ===\n"); - msg_pdbg2("FLMSTR1 0x%08x\n", mstr->FLMSTR1); - msg_pdbg2("FLMSTR2 0x%08x\n", mstr->FLMSTR2); - msg_pdbg2("FLMSTR3 0x%08x\n", mstr->FLMSTR3); + if (nm < 0) { + msg_pdbg2("%s: number of masters too high (%d).\n", __func__, + desc->content.NM + 1); + return; + } + for (i = 0; i < nm; i++) + msg_pdbg2("FLMSTR%zu 0x%08x\n", i + 1, desc->master.FLMSTRs[i]); msg_pdbg2("\n"); msg_pdbg2("--- Details ---\n"); - msg_pdbg2(" Descr. BIOS ME GbE Platf.\n"); - msg_pdbg2("BIOS %c%c %c%c %c%c %c%c %c%c\n", - (mstr->BIOS_descr_r) ?'r':' ', (mstr->BIOS_descr_w) ?'w':' ', - (mstr->BIOS_BIOS_r) ?'r':' ', (mstr->BIOS_BIOS_w) ?'w':' ', - (mstr->BIOS_ME_r) ?'r':' ', (mstr->BIOS_ME_w) ?'w':' ', - (mstr->BIOS_GbE_r) ?'r':' ', (mstr->BIOS_GbE_w) ?'w':' ', - (mstr->BIOS_plat_r) ?'r':' ', (mstr->BIOS_plat_w) ?'w':' '); - msg_pdbg2("ME %c%c %c%c %c%c %c%c %c%c\n", - (mstr->ME_descr_r) ?'r':' ', (mstr->ME_descr_w) ?'w':' ', - (mstr->ME_BIOS_r) ?'r':' ', (mstr->ME_BIOS_w) ?'w':' ', - (mstr->ME_ME_r) ?'r':' ', (mstr->ME_ME_w) ?'w':' ', - (mstr->ME_GbE_r) ?'r':' ', (mstr->ME_GbE_w) ?'w':' ', - (mstr->ME_plat_r) ?'r':' ', (mstr->ME_plat_w) ?'w':' '); - msg_pdbg2("GbE %c%c %c%c %c%c %c%c %c%c\n", - (mstr->GbE_descr_r) ?'r':' ', (mstr->GbE_descr_w) ?'w':' ', - (mstr->GbE_BIOS_r) ?'r':' ', (mstr->GbE_BIOS_w) ?'w':' ', - (mstr->GbE_ME_r) ?'r':' ', (mstr->GbE_ME_w) ?'w':' ', - (mstr->GbE_GbE_r) ?'r':' ', (mstr->GbE_GbE_w) ?'w':' ', - (mstr->GbE_plat_r) ?'r':' ', (mstr->GbE_plat_w) ?'w':' '); + if (cs == CHIPSET_100_SERIES_SUNRISE_POINT) { + const char *const master_names[] = { + "BIOS", "ME", "GbE", "unknown", "EC", + }; + if (nm >= ARRAY_SIZE(master_names)) { + msg_pdbg2("%s: number of masters too high (%d).\n", __func__, + desc->content.NM + 1); + return; + } + + msg_pdbg2(" FD BIOS ME GbE Pltf Reg5 Reg6 Reg7 EC Reg9\n"); + for (i = 0; i < nm; i++) { + size_t j; + msg_pdbg2("%-4s", master_names[i]); + for (j = 0; j < 10; j++) + msg_pdbg2(" %c%c ", + desc->master.mstr[i].read & (1 << j) ? 'r' : ' ', + desc->master.mstr[i].write & (1 << j) ? 'w' : ' '); + msg_pdbg2("\n"); + } + } else { + const struct ich_desc_master *const mstr = &desc->master; + msg_pdbg2(" Descr. BIOS ME GbE Platf.\n"); + msg_pdbg2("BIOS %c%c %c%c %c%c %c%c %c%c\n", + (mstr->BIOS_descr_r) ?'r':' ', (mstr->BIOS_descr_w) ?'w':' ', + (mstr->BIOS_BIOS_r) ?'r':' ', (mstr->BIOS_BIOS_w) ?'w':' ', + (mstr->BIOS_ME_r) ?'r':' ', (mstr->BIOS_ME_w) ?'w':' ', + (mstr->BIOS_GbE_r) ?'r':' ', (mstr->BIOS_GbE_w) ?'w':' ', + (mstr->BIOS_plat_r) ?'r':' ', (mstr->BIOS_plat_w) ?'w':' '); + msg_pdbg2("ME %c%c %c%c %c%c %c%c %c%c\n", + (mstr->ME_descr_r) ?'r':' ', (mstr->ME_descr_w) ?'w':' ', + (mstr->ME_BIOS_r) ?'r':' ', (mstr->ME_BIOS_w) ?'w':' ', + (mstr->ME_ME_r) ?'r':' ', (mstr->ME_ME_w) ?'w':' ', + (mstr->ME_GbE_r) ?'r':' ', (mstr->ME_GbE_w) ?'w':' ', + (mstr->ME_plat_r) ?'r':' ', (mstr->ME_plat_w) ?'w':' '); + msg_pdbg2("GbE %c%c %c%c %c%c %c%c %c%c\n", + (mstr->GbE_descr_r) ?'r':' ', (mstr->GbE_descr_w) ?'w':' ', + (mstr->GbE_BIOS_r) ?'r':' ', (mstr->GbE_BIOS_w) ?'w':' ', + (mstr->GbE_ME_r) ?'r':' ', (mstr->GbE_ME_w) ?'w':' ', + (mstr->GbE_GbE_r) ?'r':' ', (mstr->GbE_GbE_w) ?'w':' ', + (mstr->GbE_plat_r) ?'r':' ', (mstr->GbE_plat_w) ?'w':' '); + } msg_pdbg2("\n"); } @@ -739,8 +824,8 @@ * only valid value since. Skylake is currently the most important dis- * tinction because of the dropped number of regions field (NR). */ -enum ich_chipset guess_ich_chipset(const struct ich_desc_content *const content, - const struct ich_desc_component *const component) +static enum ich_chipset guess_ich_chipset(const struct ich_desc_content *const content, + const struct ich_desc_component *const component) { const enum ich_chipset guess = guess_ich_chipset_from_content(content); @@ -765,9 +850,10 @@ } /* len is the length of dump in bytes */ -int read_ich_descriptors_from_dump(const uint32_t *dump, unsigned int len, struct ich_descriptors *desc) +int read_ich_descriptors_from_dump(const uint32_t *const dump, const size_t len, + enum ich_chipset *const cs, struct ich_descriptors *const desc) { - unsigned int i, max_count; + size_t i, max_count; uint8_t pch_bug_offset = 0; if (dump == NULL || desc == NULL) @@ -795,21 +881,22 @@ desc->component.FLILL = dump[(getFCBA(&desc->content) >> 2) + 1]; desc->component.FLPB = dump[(getFCBA(&desc->content) >> 2) + 2]; + if (*cs == CHIPSET_ICH_UNKNOWN) + *cs = guess_ich_chipset(&desc->content, &desc->component); + /* region */ - if (len < getFRBA(&desc->content) + 5 * 4) + const ssize_t nr = ich_number_of_regions(*cs, &desc->content); + if (nr < 0 || len < getFRBA(&desc->content) + nr * 4) return ICH_RET_OOB; - desc->region.FLREGs[0] = dump[(getFRBA(&desc->content) >> 2) + 0]; - desc->region.FLREGs[1] = dump[(getFRBA(&desc->content) >> 2) + 1]; - desc->region.FLREGs[2] = dump[(getFRBA(&desc->content) >> 2) + 2]; - desc->region.FLREGs[3] = dump[(getFRBA(&desc->content) >> 2) + 3]; - desc->region.FLREGs[4] = dump[(getFRBA(&desc->content) >> 2) + 4]; + for (i = 0; i < nr; i++) + desc->region.FLREGs[i] = dump[(getFRBA(&desc->content) >> 2) + i]; /* master */ - if (len < getFMBA(&desc->content) + 3 * 4) + const ssize_t nm = ich_number_of_masters(*cs, &desc->content); + if (nm < 0 || len < getFMBA(&desc->content) + nm * 4) return ICH_RET_OOB; - desc->master.FLMSTR1 = dump[(getFMBA(&desc->content) >> 2) + 0]; - desc->master.FLMSTR2 = dump[(getFMBA(&desc->content) >> 2) + 1]; - desc->master.FLMSTR3 = dump[(getFMBA(&desc->content) >> 2) + 2]; + for (i = 0; i < nm; i++) + desc->master.FLMSTRs[i] = dump[(getFMBA(&desc->content) >> 2) + i]; /* upper map */ desc->upper.FLUMAP1 = dump[(UPPER_MAP_OFFSET >> 2) + 0]; @@ -929,8 +1016,7 @@ int read_ich_descriptors_via_fdo(enum ich_chipset cs, void *spibar, struct ich_descriptors *desc) { - uint8_t i; - uint8_t nr; + size_t i; struct ich_desc_region *r = &desc->region; /* Test if bit-fields are working as expected. @@ -938,20 +1024,20 @@ */ for (i = 0; i < 4; i++) desc->region.FLREGs[i] = 0x5A << (i * 8); - if (r->reg0_base != 0x005A || r->reg0_limit != 0x0000 || - r->reg1_base != 0x1A00 || r->reg1_limit != 0x0000 || - r->reg2_base != 0x0000 || r->reg2_limit != 0x005A || - r->reg3_base != 0x0000 || r->reg3_limit != 0x1A00) { + if (r->old_reg[0].base != 0x005A || r->old_reg[0].limit != 0x0000 || + r->old_reg[1].base != 0x1A00 || r->old_reg[1].limit != 0x0000 || + r->old_reg[2].base != 0x0000 || r->old_reg[2].limit != 0x005A || + r->old_reg[3].base != 0x0000 || r->old_reg[3].limit != 0x1A00) { msg_pdbg("The combination of compiler and CPU architecture used" "does not lay out bit-fields as expected, sorry.\n"); - msg_pspew("r->reg0_base = 0x%04X (0x005A)\n", r->reg0_base); - msg_pspew("r->reg0_limit = 0x%04X (0x0000)\n", r->reg0_limit); - msg_pspew("r->reg1_base = 0x%04X (0x1A00)\n", r->reg1_base); - msg_pspew("r->reg1_limit = 0x%04X (0x0000)\n", r->reg1_limit); - msg_pspew("r->reg2_base = 0x%04X (0x0000)\n", r->reg2_base); - msg_pspew("r->reg2_limit = 0x%04X (0x005A)\n", r->reg2_limit); - msg_pspew("r->reg3_base = 0x%04X (0x0000)\n", r->reg3_base); - msg_pspew("r->reg3_limit = 0x%04X (0x1A00)\n", r->reg3_limit); + msg_pspew("r->old_reg[0].base = 0x%04X (0x005A)\n", r->old_reg[0].base); + msg_pspew("r->old_reg[0].limit = 0x%04X (0x0000)\n", r->old_reg[0].limit); + msg_pspew("r->old_reg[1].base = 0x%04X (0x1A00)\n", r->old_reg[1].base); + msg_pspew("r->old_reg[1].limit = 0x%04X (0x0000)\n", r->old_reg[1].limit); + msg_pspew("r->old_reg[2].base = 0x%04X (0x0000)\n", r->old_reg[2].base); + msg_pspew("r->old_reg[2].limit = 0x%04X (0x005A)\n", r->old_reg[2].limit); + msg_pspew("r->old_reg[3].base = 0x%04X (0x0000)\n", r->old_reg[3].base); + msg_pspew("r->old_reg[3].limit = 0x%04X (0x1A00)\n", r->old_reg[3].limit); return ICH_RET_ERR; } @@ -968,19 +1054,24 @@ desc->component.FLPB = read_descriptor_reg(cs, 1, 2, spibar); /* region section */ - nr = desc->content.NR + 1; - if (nr > 5) { + const ssize_t nr = ich_number_of_regions(cs, &desc->content); + if (nr < 0) { msg_pdbg2("%s: number of regions too high (%d) - failed\n", - __func__, nr); + __func__, desc->content.NR + 1); return ICH_RET_ERR; } - for (i = 0; i < 5; i++) + for (i = 0; i < nr; i++) desc->region.FLREGs[i] = read_descriptor_reg(cs, 2, i, spibar); /* master section */ - desc->master.FLMSTR1 = read_descriptor_reg(cs, 3, 0, spibar); - desc->master.FLMSTR2 = read_descriptor_reg(cs, 3, 1, spibar); - desc->master.FLMSTR3 = read_descriptor_reg(cs, 3, 2, spibar); + const ssize_t nm = ich_number_of_masters(cs, &desc->content); + if (nm < 0) { + msg_pdbg2("%s: number of masters too high (%d) - failed\n", + __func__, desc->content.NM + 1); + return ICH_RET_ERR; + } + for (i = 0; i < nm; i++) + desc->master.FLMSTRs[i] = read_descriptor_reg(cs, 3, i, spibar); /* Accessing the strap section via FDOC/D is only possible on ICH8 and * reading the upper map is impossible on all chipsets, so don't bother. @@ -1003,16 +1094,19 @@ */ int layout_from_ich_descriptors(struct ich_layout *const layout, const void *const dump, const size_t len) { - static const char *regions[] = { "fd", "bios", "me", "gbe", "pd" }; + static const char *const regions[] = { + "fd", "bios", "me", "gbe", "pd", "reg5", "reg6", "reg7", "ec", "reg9" + }; struct ich_descriptors desc; - if (read_ich_descriptors_from_dump(dump, len, &desc)) + enum ich_chipset cs = CHIPSET_ICH_UNKNOWN; + if (read_ich_descriptors_from_dump(dump, len, &cs, &desc)) return 1; memset(layout, 0x00, sizeof(*layout)); - size_t i, j; - for (i = 0, j = 0; i < min(desc.content.NR + 1, ARRAY_SIZE(regions)); ++i) { + ssize_t i, j; + for (i = 0, j = 0; i < min(ich_number_of_regions(cs, &desc.content), ARRAY_SIZE(regions)); ++i) { const chipoff_t base = ICH_FREG_BASE(desc.region.FLREGs[i]); const chipoff_t limit = ICH_FREG_LIMIT(desc.region.FLREGs[i]); if (limit <= base) diff --git a/ich_descriptors.h b/ich_descriptors.h index 920e098..bccea27 100644 --- a/ich_descriptors.h +++ b/ich_descriptors.h @@ -62,8 +62,8 @@ #define VSCC_VCL (0x1 << VSCC_VCL_OFF) /* 24-31: reserved */ -#define ICH_FREG_BASE(flreg) (((flreg) << 12) & 0x01fff000) -#define ICH_FREG_LIMIT(flreg) ((((flreg) >> 4) & 0x01fff000) | 0x00000fff) +#define ICH_FREG_BASE(flreg) (((flreg) << 12) & 0x07fff000) +#define ICH_FREG_LIMIT(flreg) ((((flreg) >> 4) & 0x07fff000) | 0x00000fff) void prettyprint_ich_reg_vscc(uint32_t reg_val, int verbosity, bool print_vcl); @@ -76,7 +76,7 @@ NC :2, /* Number Of Components */ :6, FRBA :8, /* Flash Region Base Address */ - NR :3, /* Number Of Regions */ + NR :3, /* Number Of Regions (reserved from Skylake on) */ :5; }; }; @@ -116,7 +116,8 @@ * Patsburg: 50 30 5 0:2, 3:5 * Panther Point/7 50 30 5 0:2, 3:5 * Lynx Point/8: 50 30 7 0:3, 4:7 - * Wildcat Point/9: 50 ?? (multi I/O) ? ?:?, ?:? + * Wildcat Point/9: 50 30 (multi I/O) 7 0:3, 4:7 + * Sunrise Point/100: 48 30 7 0:3, 4:7 */ struct { uint32_t :17, @@ -149,55 +150,49 @@ }; }; union { /* 0x08 */ - uint32_t FLPB; /* Flash Partition Boundary Register */ + uint32_t FLPB; /* Flash Partition Boundary Register, until Panther Point/7 */ struct { uint32_t FPBA :13, /* Flash Partition Boundary Addr */ :19; }; - }; -}; - -struct ich_desc_region { - union { - uint32_t FLREGs[5]; + uint32_t FLILL1; /* Flash Invalid Instructions Register, new since Sunrise Point/100 */ struct { - struct { /* FLREG0 Flash Descriptor */ - uint32_t reg0_base :13, - :3, - reg0_limit :13, - :3; - }; - struct { /* FLREG1 BIOS */ - uint32_t reg1_base :13, - :3, - reg1_limit :13, - :3; - }; - struct { /* FLREG2 ME */ - uint32_t reg2_base :13, - :3, - reg2_limit :13, - :3; - }; - struct { /* FLREG3 GbE */ - uint32_t reg3_base :13, - :3, - reg3_limit :13, - :3; - }; - struct { /* FLREG4 Platform */ - uint32_t reg4_base :13, - :3, - reg4_limit :13, - :3; - }; + uint32_t invalid_instr4 :8, + invalid_instr5 :8, + invalid_instr6 :8, + invalid_instr7 :8; }; }; }; +#define MAX_NUM_FLREGS 10 /* 16 on unsupported Lewisburg PCH */ +struct ich_desc_region { + /* + * Number of entries and width differ on various generations: + * + * Chipset/Generation #FLREGs width (bits) + * ICH8 .. Panther Point/7 5 13 + * Lynx Point/8 .. Wildcat Point/9 7 15 + * Sunrise Point/100 .. 10 15 + */ + union { + uint32_t FLREGs[MAX_NUM_FLREGS]; /* Flash Descriptor Regions */ + + /* only used for bit-field check */ + struct { + uint32_t base :13, + :3, + limit :13, + :3; + } old_reg[MAX_NUM_FLREGS]; + }; +}; + +#define MAX_NUM_MASTERS 5 /* 6 on unsupported Lewisburg PCH */ struct ich_desc_master { union { - uint32_t FLMSTR1; + uint32_t FLMSTRs[MAX_NUM_MASTERS]; /* Flash Masters */ + /* For pre-Skylake platforms */ struct { uint32_t BIOS_req_ID :16, BIOS_descr_r :1, @@ -212,11 +207,6 @@ BIOS_GbE_w :1, BIOS_plat_w :1, :3; - }; - }; - union { - uint32_t FLMSTR2; - struct { uint32_t ME_req_ID :16, ME_descr_r :1, ME_BIOS_r :1, @@ -230,11 +220,6 @@ ME_GbE_w :1, ME_plat_w :1, :3; - }; - }; - union { - uint32_t FLMSTR3; - struct { uint32_t GbE_req_ID :16, GbE_descr_r :1, GbE_BIOS_r :1, @@ -249,6 +234,12 @@ GbE_plat_w :1, :3; }; + /* From Skylake on */ + struct { + uint32_t :8, + read :12, + write :12; + } mstr[MAX_NUM_MASTERS]; }; }; @@ -573,16 +564,19 @@ struct ich_desc_upper_map upper; }; +ssize_t ich_number_of_regions(enum ich_chipset cs, const struct ich_desc_content *content); +ssize_t ich_number_of_masters(enum ich_chipset cs, const struct ich_desc_content *content); + void prettyprint_ich_descriptors(enum ich_chipset cs, const struct ich_descriptors *desc); -void prettyprint_ich_descriptor_content(const struct ich_desc_content *content); +void prettyprint_ich_descriptor_content(enum ich_chipset cs, const struct ich_desc_content *content); void prettyprint_ich_descriptor_component(enum ich_chipset cs, const struct ich_descriptors *desc); -void prettyprint_ich_descriptor_region(const struct ich_descriptors *desc); -void prettyprint_ich_descriptor_master(const struct ich_desc_master *master); +void prettyprint_ich_descriptor_region(enum ich_chipset cs, const struct ich_descriptors *desc); +void prettyprint_ich_descriptor_master(enum ich_chipset cs, const struct ich_descriptors *desc); void prettyprint_ich_descriptor_upper_map(const struct ich_desc_upper_map *umap); void prettyprint_ich_descriptor_straps(enum ich_chipset cs, const struct ich_descriptors *desc); -int read_ich_descriptors_from_dump(const uint32_t *dump, unsigned int len, struct ich_descriptors *desc); +int read_ich_descriptors_from_dump(const uint32_t *dump, size_t len, enum ich_chipset *cs, struct ich_descriptors *desc); int read_ich_descriptors_via_fdo(enum ich_chipset cs, void *spibar, struct ich_descriptors *desc); int getFCBA_component_density(enum ich_chipset cs, const struct ich_descriptors *desc, uint8_t idx); diff --git a/util/ich_descriptors_tool/ich_descriptors_tool.c b/util/ich_descriptors_tool/ich_descriptors_tool.c index 7dfa5c0..82c74bd 100644 --- a/util/ich_descriptors_tool/ich_descriptors_tool.c +++ b/util/ich_descriptors_tool/ich_descriptors_tool.c @@ -40,15 +40,18 @@ #include <sys/mman.h> #endif -static void dump_file(const char *prefix, const uint32_t *dump, unsigned int len, struct ich_desc_region *reg, unsigned int i) +static const char *const region_names[] = { + "Descriptor", "BIOS", "ME", "GbE", "Platform", + "Region5", "Region6", "Region7", "EC", "Region9", +}; + +static void dump_file(const char *prefix, const uint32_t *dump, unsigned int len, + const struct ich_desc_region *const reg, unsigned int i) { int ret; char *fn; const char *reg_name; uint32_t file_len; - const char *const region_names[5] = { - "Descriptor", "BIOS", "ME", "GbE", "Platform" - }; uint32_t base = ICH_FREG_BASE(reg->FLREGs[i]); uint32_t limit = ICH_FREG_LIMIT(reg->FLREGs[i]); @@ -94,12 +97,19 @@ close(fh); } -void dump_files(const char *name, const uint32_t *buf, unsigned int len, struct ich_desc_region *reg) +int min(int a, int b) { - unsigned int i; + return (a < b) ? a : b; +} + +static void dump_files(const char *name, const uint32_t *buf, unsigned int len, + const enum ich_chipset cs, const struct ich_descriptors *const desc) +{ + ssize_t i; + const ssize_t nr = min(ich_number_of_regions(cs, &desc->content), ARRAY_SIZE(region_names)); printf("=== Dumping region files ===\n"); - for (i = 0; i < 5; i++) - dump_file(name, buf, len, reg, i); + for (i = 0; i < nr; i++) + dump_file(name, buf, len, &desc->region, i); printf("\n"); } @@ -123,6 +133,7 @@ "\t- \"7\" or \"panther\" for Intel's 7 series chipsets.\n" "\t- \"8\" or \"lynx\" for Intel's 8 series chipsets.\n" "\t- \"9\" or \"wildcat\" for Intel's 9 series chipsets.\n" +"\t- \"100\" or \"sunrise\" for Intel's 100 series chipsets.\n" "If '-d' is specified some regions such as the BIOS image as seen by the CPU or\n" "the GbE blob that is required to initialize the GbE are also dumped to files.\n", argv[0], argv[0]); @@ -208,9 +219,12 @@ else if ((strcmp(csn, "9") == 0) || (strcmp(csn, "wildcat") == 0)) cs = CHIPSET_9_SERIES_WILDCAT_POINT; + else if ((strcmp(csn, "100") == 0) || + (strcmp(csn, "sunrise") == 0)) + cs = CHIPSET_100_SERIES_SUNRISE_POINT; } - ret = read_ich_descriptors_from_dump(buf, len, &desc); + ret = read_ich_descriptors_from_dump(buf, len, &cs, &desc); switch (ret) { case ICH_RET_OK: break; @@ -228,15 +242,15 @@ prettyprint_ich_descriptors(cs, &desc); - pMAC = (uint8_t *) &buf[ICH_FREG_BASE(desc.region.reg3_base) >> 2]; - if (len >= ICH_FREG_BASE(desc.region.reg3_base) + 6 && pMAC[0] != 0xff) + pMAC = (uint8_t *) &buf[ICH_FREG_BASE(desc.region.FLREGs[3]) >> 2]; + if (len >= ICH_FREG_BASE(desc.region.FLREGs[3]) + 6 && pMAC[0] != 0xff) printf("The MAC address might be at offset 0x%x: " "%02x:%02x:%02x:%02x:%02x:%02x\n", - ICH_FREG_BASE(desc.region.reg3_base), + ICH_FREG_BASE(desc.region.FLREGs[3]), pMAC[0], pMAC[1], pMAC[2], pMAC[3], pMAC[4], pMAC[5]); if (dump == 1) - dump_files(fn, buf, len, &desc.region); + dump_files(fn, buf, len, cs, &desc); return 0; } -- To view, visit https://review.coreboot.org/21809 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: stable Gerrit-MessageType: newchange Gerrit-Change-Id: I34ac844dd414db6f8957763846cbfba75301bae5 Gerrit-Change-Number: 21809 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de>

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Change in flashrom[stable]: ich_descriptors: Add function to guess chipset version
by Nico Huber (Code Review) 30 Sep '17

30 Sep '17

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/21808 Change subject: ich_descriptors: Add function to guess chipset version ...................................................................... ich_descriptors: Add function to guess chipset version Add guess_ich_chipset() that takes fields from a descriptor dump and returns the lowest possible chipset version. Intel did several incompatible changes to the descriptor through the years. However, they forgot to add a version number. So we have to apply some heuristics to detect the chipset version in case of exter- nal flashing. Original-Change-Id: Ie1736663dc33801b19d3e695c072c61a6c6345a2 Original-Reviewed-on: https://review.coreboot.org/20246 Original-Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Original-Reviewed-by: David Hendricks <david.hendricks(a)gmail.com> Original-Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Change-Id: I3968901a9e82a34356e8c5edb14354b82bf27305 Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- M ich_descriptors.c M ich_descriptors.h 2 files changed, 66 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/08/21808/1 diff --git a/ich_descriptors.c b/ich_descriptors.c index 3e53ec9..4c18dfa 100644 --- a/ich_descriptors.c +++ b/ich_descriptors.c @@ -702,6 +702,68 @@ msg_pdbg2("\n"); } +/* + * Guesses a minimum chipset version based on the maximum number of + * soft straps per generation. + */ +static enum ich_chipset guess_ich_chipset_from_content(const struct ich_desc_content *const content) +{ + if (content->ICCRIBA == 0x00) { + if (content->MSL == 0 && content->ISL <= 2) + return CHIPSET_ICH8; + else if (content->ISL <= 2) + return CHIPSET_ICH9; + else if (content->ISL <= 10) + return CHIPSET_ICH10; + else if (content->ISL <= 16) + return CHIPSET_5_SERIES_IBEX_PEAK; + msg_pwarn("Peculiar firmware descriptor, assuming Ibex Peak compatibility.\n"); + return CHIPSET_5_SERIES_IBEX_PEAK; + } else if (content->ICCRIBA < 0x31 && content->FMSBA < 0x30) { + if (content->MSL == 0 && content->ISL <= 17) + return CHIPSET_BAYTRAIL; + else if (content->MSL <= 1 && content->ISL <= 18) + return CHIPSET_6_SERIES_COUGAR_POINT; + else if (content->MSL <= 1 && content->ISL <= 21) + return CHIPSET_8_SERIES_LYNX_POINT; + msg_pwarn("Peculiar firmware descriptor, assuming Wildcat Point compatibility.\n"); + return CHIPSET_9_SERIES_WILDCAT_POINT; + } else { + return CHIPSET_100_SERIES_SUNRISE_POINT; + } +} + +/* + * As an additional measure, we check the read frequency like `ifdtool`. + * The frequency value 6 (17MHz) was reserved before Skylake and is the + * only valid value since. Skylake is currently the most important dis- + * tinction because of the dropped number of regions field (NR). + */ +enum ich_chipset guess_ich_chipset(const struct ich_desc_content *const content, + const struct ich_desc_component *const component) +{ + const enum ich_chipset guess = guess_ich_chipset_from_content(content); + + if (component->modes.freq_read == 6) { + if (guess != CHIPSET_100_SERIES_SUNRISE_POINT) + msg_pwarn("\nThe firmware descriptor has the read frequency set to 17MHz. However,\n" + "it doesn't look like a Skylake/Sunrise Point compatible descriptor.\n" + "Please report this message, the output of `ich_descriptors_tool` for\n" + "your descriptor and the output of `lspci -nn` to flashrom(a)flashrom.org\n\n"); + return CHIPSET_100_SERIES_SUNRISE_POINT; + } else { + if (guess == CHIPSET_100_SERIES_SUNRISE_POINT) { + msg_pwarn("\nThe firmware descriptor looks like a Skylake/Sunrise Point descriptor.\n" + "However, the read frequency isn't set to 17MHz (the only valid value).\n" + "Please report this message, the output of `ich_descriptors_tool` for\n" + "your descriptor and the output of `lspci -nn` to flashrom(a)flashrom.org\n\n"); + return CHIPSET_9_SERIES_WILDCAT_POINT; + } + } + + return guess; +} + /* len is the length of dump in bytes */ int read_ich_descriptors_from_dump(const uint32_t *dump, unsigned int len, struct ich_descriptors *desc) { diff --git a/ich_descriptors.h b/ich_descriptors.h index ec85e0c..920e098 100644 --- a/ich_descriptors.h +++ b/ich_descriptors.h @@ -93,9 +93,10 @@ union { /* 0x0c */ uint32_t FLMAP2; struct { - uint32_t FMSBA :8, /* Flash (G)MCH Strap Base Addr. */ - MSL :8, /* MCH Strap Length */ - :16; + uint32_t FMSBA :8, /* Flash (G)MCH Strap Base Addr. */ + MSL :8, /* MCH Strap Length */ + ICCRIBA :8, /* ICC Reg. Init Base Addr. (new since Sandy Bridge) */ + RIL :8; /* Register Init Length (new since Hawell) */ }; }; }; -- To view, visit https://review.coreboot.org/21808 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: stable Gerrit-MessageType: newchange Gerrit-Change-Id: I3968901a9e82a34356e8c5edb14354b82bf27305 Gerrit-Change-Number: 21808 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de>

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Change in flashrom[stable]: ich_descriptors: Draw +0xfff into ICH_FREG_LIMIT()
by Nico Huber (Code Review) 30 Sep '17

30 Sep '17

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/21807 Change subject: ich_descriptors: Draw +0xfff into ICH_FREG_LIMIT() ...................................................................... ich_descriptors: Draw +0xfff into ICH_FREG_LIMIT() The condition `base > limit` is still valid since `base` is always at least 4096 greater than `limit` in this case. Original-Change-Id: I11ac0a50b3f32f47879e7cfb7a26068cd0572ede Original-Reviewed-on: https://review.coreboot.org/19046 Original-Reviewed-by: David Hendricks <david.hendricks(a)gmail.com> Original-Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Change-Id: Idfa1a13292e1dcd5e92bb2dbfe11392693952698 Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- M ich_descriptors.c M ich_descriptors.h M ichspi.c M util/ich_descriptors_tool/ich_descriptors_tool.c 4 files changed, 6 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/07/21807/1 diff --git a/ich_descriptors.c b/ich_descriptors.c index 1fc8835..3e53ec9 100644 --- a/ich_descriptors.c +++ b/ich_descriptors.c @@ -246,7 +246,7 @@ if (base > limit) msg_pdbg2("is unused.\n"); else - msg_pdbg2("0x%08x - 0x%08x\n", base, limit | 0x0fff); + msg_pdbg2("0x%08x - 0x%08x\n", base, limit); } void prettyprint_ich_descriptor_region(const struct ich_descriptors *desc) @@ -952,7 +952,7 @@ size_t i, j; for (i = 0, j = 0; i < min(desc.content.NR + 1, ARRAY_SIZE(regions)); ++i) { const chipoff_t base = ICH_FREG_BASE(desc.region.FLREGs[i]); - const chipoff_t limit = ICH_FREG_LIMIT(desc.region.FLREGs[i]) + 0xfff; + const chipoff_t limit = ICH_FREG_LIMIT(desc.region.FLREGs[i]); if (limit <= base) continue; layout->entries[j].start = base; diff --git a/ich_descriptors.h b/ich_descriptors.h index 831341a..ec85e0c 100644 --- a/ich_descriptors.h +++ b/ich_descriptors.h @@ -63,7 +63,7 @@ /* 24-31: reserved */ #define ICH_FREG_BASE(flreg) (((flreg) << 12) & 0x01fff000) -#define ICH_FREG_LIMIT(flreg) (((flreg) >> 4) & 0x01fff000) +#define ICH_FREG_LIMIT(flreg) ((((flreg) >> 4) & 0x01fff000) | 0x00000fff) void prettyprint_ich_reg_vscc(uint32_t reg_val, int verbosity, bool print_vcl); diff --git a/ichspi.c b/ichspi.c index ecf0c42..5f3e394 100644 --- a/ichspi.c +++ b/ichspi.c @@ -1566,14 +1566,12 @@ msg_pdbg("0x%02X: 0x%08x ", offset, freg); if (rwperms == 0x3) { msg_pdbg("FREG%i: %s region (0x%08x-0x%08x) is %s.\n", i, - region_name, base, (limit | 0x0fff), - access_names[rwperms]); + region_name, base, limit, access_names[rwperms]); return 0; } msg_pwarn("FREG%i: Warning: %s region (0x%08x-0x%08x) is %s.\n", i, - region_name, base, (limit | 0x0fff), - access_names[rwperms]); + region_name, base, limit, access_names[rwperms]); return 1; } @@ -1608,7 +1606,7 @@ msg_pdbg("0x%02X: 0x%08x ", off, pr); msg_pwarn("%sPR%u: Warning: 0x%08x-0x%08x is %s.\n", prefix, i, ICH_FREG_BASE(pr), - ICH_FREG_LIMIT(pr) | 0x0fff, access_names[rwperms]); + ICH_FREG_LIMIT(pr), access_names[rwperms]); return 1; } diff --git a/util/ich_descriptors_tool/ich_descriptors_tool.c b/util/ich_descriptors_tool/ich_descriptors_tool.c index 250abf0..7dfa5c0 100644 --- a/util/ich_descriptors_tool/ich_descriptors_tool.c +++ b/util/ich_descriptors_tool/ich_descriptors_tool.c @@ -58,7 +58,6 @@ return; } - limit = limit | 0x0fff; file_len = limit + 1 - base; if (base + file_len > len) { printf("The %s region is spanning 0x%08x-0x%08x, but it is " -- To view, visit https://review.coreboot.org/21807 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: stable Gerrit-MessageType: newchange Gerrit-Change-Id: Idfa1a13292e1dcd5e92bb2dbfe11392693952698 Gerrit-Change-Number: 21807 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de>

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Change in flashrom[stable]: ichspi: Add support for Intel Skylake
by Nico Huber (Code Review) 30 Sep '17

30 Sep '17

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/21806 Change subject: ichspi: Add support for Intel Skylake ...................................................................... ichspi: Add support for Intel Skylake The Sunrise Point PCH, paired with Skylake, has some minor changes in the HW sequencing interface: * Support for more flash regions moved PR* registers * Only 4KiB erase blocks are supported by the primary erase command * A second erase command for 64KiB pages was added * More commands were added for status register access etc. * A "Dedicated Lock Bits" register was added No support for the new commands was added. The SW sequencing interface seems to have moved register location and is not supported any more officially. It's also untested. Changes are loosely based on the Skylake support commit in Chromium OS by Ramya Vijaykumar: commit a9a64f9e4d52c39fcd3c5f7d7b88065baed189b1 Author: Ramya Vijaykumar <ramya.vijaykumar(a)intel.com> flashrom: Add Skylake platform support Original-Change-Id: I0f4565a3c39f5fe3aec4fc8863605cebed1ad4ee Original-Reviewed-on: https://review.coreboot.org/18962 Original-Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Original-Reviewed-by: David Hendricks <david.hendricks(a)gmail.com> Original-Reviewed-by: Youness Alaoui <snifikino(a)gmail.com> Change-Id: Ifc5a5fc9ad22a8151e66850ef70c5cf406a83a37 Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- M ich_descriptors.c M ich_descriptors.h M ichspi.c 3 files changed, 233 insertions(+), 87 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/06/21806/1 diff --git a/ich_descriptors.c b/ich_descriptors.c index a12022c..1fc8835 100644 --- a/ich_descriptors.c +++ b/ich_descriptors.c @@ -824,6 +824,7 @@ case CHIPSET_8_SERIES_WELLSBURG: case CHIPSET_9_SERIES_WILDCAT_POINT: case CHIPSET_9_SERIES_WILDCAT_POINT_LP: + case CHIPSET_100_SERIES_SUNRISE_POINT: if (idx == 0) { size_enc = desc->component.dens_new.comp1_density; } else { @@ -849,16 +850,22 @@ /* Only used by ichspi.c */ #if CONFIG_INTERNAL == 1 && (defined(__i386__) || defined(__x86_64__)) -static uint32_t read_descriptor_reg(uint8_t section, uint16_t offset, void *spibar) +static uint32_t read_descriptor_reg(enum ich_chipset cs, uint8_t section, uint16_t offset, void *spibar) { uint32_t control = 0; control |= (section << FDOC_FDSS_OFF) & FDOC_FDSS; control |= (offset << FDOC_FDSI_OFF) & FDOC_FDSI; - mmio_le_writel(control, spibar + ICH9_REG_FDOC); - return mmio_le_readl(spibar + ICH9_REG_FDOD); + if (cs == CHIPSET_100_SERIES_SUNRISE_POINT) { + mmio_le_writel(control, spibar + PCH100_REG_FDOC); + return mmio_le_readl(spibar + PCH100_REG_FDOD); + } else { + mmio_le_writel(control, spibar + ICH9_REG_FDOC); + return mmio_le_readl(spibar + ICH9_REG_FDOD); + } + } -int read_ich_descriptors_via_fdo(void *spibar, struct ich_descriptors *desc) +int read_ich_descriptors_via_fdo(enum ich_chipset cs, void *spibar, struct ich_descriptors *desc) { uint8_t i; uint8_t nr; @@ -888,15 +895,15 @@ msg_pdbg2("Reading flash descriptors mapped by the chipset via FDOC/FDOD..."); /* content section */ - desc->content.FLVALSIG = read_descriptor_reg(0, 0, spibar); - desc->content.FLMAP0 = read_descriptor_reg(0, 1, spibar); - desc->content.FLMAP1 = read_descriptor_reg(0, 2, spibar); - desc->content.FLMAP2 = read_descriptor_reg(0, 3, spibar); + desc->content.FLVALSIG = read_descriptor_reg(cs, 0, 0, spibar); + desc->content.FLMAP0 = read_descriptor_reg(cs, 0, 1, spibar); + desc->content.FLMAP1 = read_descriptor_reg(cs, 0, 2, spibar); + desc->content.FLMAP2 = read_descriptor_reg(cs, 0, 3, spibar); /* component section */ - desc->component.FLCOMP = read_descriptor_reg(1, 0, spibar); - desc->component.FLILL = read_descriptor_reg(1, 1, spibar); - desc->component.FLPB = read_descriptor_reg(1, 2, spibar); + desc->component.FLCOMP = read_descriptor_reg(cs, 1, 0, spibar); + desc->component.FLILL = read_descriptor_reg(cs, 1, 1, spibar); + desc->component.FLPB = read_descriptor_reg(cs, 1, 2, spibar); /* region section */ nr = desc->content.NR + 1; @@ -906,12 +913,12 @@ return ICH_RET_ERR; } for (i = 0; i < 5; i++) - desc->region.FLREGs[i] = read_descriptor_reg(2, i, spibar); + desc->region.FLREGs[i] = read_descriptor_reg(cs, 2, i, spibar); /* master section */ - desc->master.FLMSTR1 = read_descriptor_reg(3, 0, spibar); - desc->master.FLMSTR2 = read_descriptor_reg(3, 1, spibar); - desc->master.FLMSTR3 = read_descriptor_reg(3, 2, spibar); + desc->master.FLMSTR1 = read_descriptor_reg(cs, 3, 0, spibar); + desc->master.FLMSTR2 = read_descriptor_reg(cs, 3, 1, spibar); + desc->master.FLMSTR3 = read_descriptor_reg(cs, 3, 2, spibar); /* Accessing the strap section via FDOC/D is only possible on ICH8 and * reading the upper map is impossible on all chipsets, so don't bother. diff --git a/ich_descriptors.h b/ich_descriptors.h index ecf44bf..831341a 100644 --- a/ich_descriptors.h +++ b/ich_descriptors.h @@ -33,6 +33,7 @@ #define ICH_RET_OOB -4 #define ICH9_REG_FDOC 0xB0 /* 32 Bits Flash Descriptor Observability Control */ +#define PCH100_REG_FDOC 0xB4 /* New offset from Sunrise Point on */ /* 0-1: reserved */ #define FDOC_FDSI_OFF 2 /* 2-11: Flash Descriptor Section Index */ #define FDOC_FDSI (0x3f << FDOC_FDSI_OFF) @@ -41,6 +42,7 @@ /* 15-31: reserved */ #define ICH9_REG_FDOD 0xB4 /* 32 Bits Flash Descriptor Observability Data */ +#define PCH100_REG_FDOD 0xB8 /* New offset from Sunrise Point on */ /* Field locations and semantics for LVSCC, UVSCC and related words in the flash * descriptor are equal therefore they all share the same macros below. */ @@ -581,7 +583,7 @@ void prettyprint_ich_descriptor_straps(enum ich_chipset cs, const struct ich_descriptors *desc); int read_ich_descriptors_from_dump(const uint32_t *dump, unsigned int len, struct ich_descriptors *desc); -int read_ich_descriptors_via_fdo(void *spibar, struct ich_descriptors *desc); +int read_ich_descriptors_via_fdo(enum ich_chipset cs, void *spibar, struct ich_descriptors *desc); int getFCBA_component_density(enum ich_chipset cs, const struct ich_descriptors *desc, uint8_t idx); int layout_from_ich_descriptors(struct ich_layout *, const void *dump, size_t len); diff --git a/ichspi.c b/ichspi.c index be13f91..ecf0c42 100644 --- a/ichspi.c +++ b/ichspi.c @@ -33,6 +33,60 @@ #include "spi.h" #include "ich_descriptors.h" +/* Sunrise Point */ + +/* Added HSFS Status bits */ +#define HSFS_WRSDIS_OFF 11 /* 11: Flash Configuration Lock-Down */ +#define HSFS_WRSDIS (0x1 << HSFS_WRSDIS_OFF) +#define HSFS_PRR34_LOCKDN_OFF 12 /* 12: PRR3 PRR4 Lock-Down */ +#define HSFS_PRR34_LOCKDN (0x1 << HSFS_PRR34_LOCKDN_OFF) +/* HSFS_BERASE vanished */ + +/* + * HSFC and HSFS 16-bit registers are combined into the 32-bit + * BIOS_HSFSTS_CTL register in the Sunrise Point datasheet, + * however we still treat them separately in order to reuse code. + */ + +/* Changed HSFC Control bits */ +#define PCH100_HSFC_FCYCLE_OFF (17 - 16) /* 1-4: FLASH Cycle */ +#define PCH100_HSFC_FCYCLE (0xf << PCH100_HSFC_FCYCLE_OFF) +/* New HSFC Control bit */ +#define HSFC_WET_OFF (21 - 16) /* 5: Write Enable Type */ +#define HSFC_WET (0x1 << HSFC_WET_OFF) + +#define PCH100_FADDR_FLA 0x07ffffff + +#define PCH100_REG_DLOCK 0x0c /* 32 Bits Discrete Lock Bits */ +#define DLOCK_BMWAG_LOCKDN_OFF 0 +#define DLOCK_BMWAG_LOCKDN (0x1 << DLOCK_BMWAG_LOCKDN_OFF) +#define DLOCK_BMRAG_LOCKDN_OFF 1 +#define DLOCK_BMRAG_LOCKDN (0x1 << DLOCK_BMRAG_LOCKDN_OFF) +#define DLOCK_SBMWAG_LOCKDN_OFF 2 +#define DLOCK_SBMWAG_LOCKDN (0x1 << DLOCK_SBMWAG_LOCKDN_OFF) +#define DLOCK_SBMRAG_LOCKDN_OFF 3 +#define DLOCK_SBMRAG_LOCKDN (0x1 << DLOCK_SBMRAG_LOCKDN_OFF) +#define DLOCK_PR0_LOCKDN_OFF 8 +#define DLOCK_PR0_LOCKDN (0x1 << DLOCK_PR0_LOCKDN_OFF) +#define DLOCK_PR1_LOCKDN_OFF 9 +#define DLOCK_PR1_LOCKDN (0x1 << DLOCK_PR1_LOCKDN_OFF) +#define DLOCK_PR2_LOCKDN_OFF 10 +#define DLOCK_PR2_LOCKDN (0x1 << DLOCK_PR2_LOCKDN_OFF) +#define DLOCK_PR3_LOCKDN_OFF 11 +#define DLOCK_PR3_LOCKDN (0x1 << DLOCK_PR3_LOCKDN_OFF) +#define DLOCK_PR4_LOCKDN_OFF 12 +#define DLOCK_PR4_LOCKDN (0x1 << DLOCK_PR4_LOCKDN_OFF) +#define DLOCK_SSEQ_LOCKDN_OFF 16 +#define DLOCK_SSEQ_LOCKDN (0x1 << DLOCK_SSEQ_LOCKDN_OFF) + +#define PCH100_REG_FPR0 0x84 /* 32 Bits Protected Range 0 */ +#define PCH100_REG_GPR0 0x98 /* 32 Bits Global Protected Range 0 */ + +#define PCH100_REG_SSFSC 0xA0 /* 32 Bits Status (8) + Control (24) */ +#define PCH100_REG_PREOP 0xA4 /* 16 Bits */ +#define PCH100_REG_OPTYPE 0xA6 /* 16 Bits */ +#define PCH100_REG_OPMENU 0xA8 /* 64 Bits */ + /* ICH9 controller register definition */ #define ICH9_REG_HSFS 0x04 /* 16 Bits Hardware Sequencing Flash Status */ #define HSFS_FDONE_OFF 0 /* 0: Flash Cycle Done */ @@ -66,6 +120,7 @@ #define HSFC_SME (0x1 << HSFC_SME_OFF) #define ICH9_REG_FADDR 0x08 /* 32 Bits */ +#define ICH9_FADDR_FLA 0x01ffffff #define ICH9_REG_FDATA0 0x10 /* 64 Bytes */ #define ICH9_REG_FRAP 0x50 /* 32 Bytes Flash Region Access Permissions */ @@ -325,7 +380,8 @@ ops->preop[1]); } -#define pprint_reg(reg, bit, val, sep) msg_pdbg("%s=%d" sep, #bit, (val & reg##_##bit)>>reg##_##bit##_OFF) +#define _pprint_reg(bit, mask, off, val, sep) msg_pdbg("%s=%d" sep, #bit, (val & mask) >> off) +#define pprint_reg(reg, bit, val, sep) _pprint_reg(bit, reg##_##bit, reg##_##bit##_OFF, val, sep) static void prettyprint_ich9_reg_hsfs(uint16_t reg_val) { @@ -333,8 +389,14 @@ pprint_reg(HSFS, FDONE, reg_val, ", "); pprint_reg(HSFS, FCERR, reg_val, ", "); pprint_reg(HSFS, AEL, reg_val, ", "); - pprint_reg(HSFS, BERASE, reg_val, ", "); + if (ich_generation != CHIPSET_100_SERIES_SUNRISE_POINT) { + pprint_reg(HSFS, BERASE, reg_val, ", "); + } pprint_reg(HSFS, SCIP, reg_val, ", "); + if (ich_generation == CHIPSET_100_SERIES_SUNRISE_POINT) { + pprint_reg(HSFS, PRR34_LOCKDN, reg_val, ", "); + pprint_reg(HSFS, WRSDIS, reg_val, ", "); + } pprint_reg(HSFS, FDOPSS, reg_val, ", "); pprint_reg(HSFS, FDV, reg_val, ", "); pprint_reg(HSFS, FLOCKDN, reg_val, "\n"); @@ -344,7 +406,12 @@ { msg_pdbg("HSFC: "); pprint_reg(HSFC, FGO, reg_val, ", "); - pprint_reg(HSFC, FCYCLE, reg_val, ", "); + if (ich_generation != CHIPSET_100_SERIES_SUNRISE_POINT) { + pprint_reg(HSFC, FCYCLE, reg_val, ", "); + } else { + _pprint_reg(HSFC, PCH100_HSFC_FCYCLE, PCH100_HSFC_FCYCLE_OFF, reg_val, ", "); + pprint_reg(HSFC, WET, reg_val, ", "); + } pprint_reg(HSFC, FDBC, reg_val, ", "); pprint_reg(HSFC, SME, reg_val, "\n"); } @@ -369,6 +436,28 @@ pprint_reg(SSFC, SME, reg_val, ", "); pprint_reg(SSFC, SCF, reg_val, "\n"); } + +static void prettyprint_pch100_reg_dlock(const uint32_t reg_val) +{ + msg_pdbg("DLOCK: "); + pprint_reg(DLOCK, BMWAG_LOCKDN, reg_val, ", "); + pprint_reg(DLOCK, BMRAG_LOCKDN, reg_val, ", "); + pprint_reg(DLOCK, SBMWAG_LOCKDN, reg_val, ", "); + pprint_reg(DLOCK, SBMRAG_LOCKDN, reg_val, ",\n "); + pprint_reg(DLOCK, PR0_LOCKDN, reg_val, ", "); + pprint_reg(DLOCK, PR1_LOCKDN, reg_val, ", "); + pprint_reg(DLOCK, PR2_LOCKDN, reg_val, ", "); + pprint_reg(DLOCK, PR3_LOCKDN, reg_val, ", "); + pprint_reg(DLOCK, PR4_LOCKDN, reg_val, ",\n "); + pprint_reg(DLOCK, SSEQ_LOCKDN, reg_val, "\n"); +} + +static struct { + size_t reg_ssfsc; + size_t reg_preop; + size_t reg_optype; + size_t reg_opmenu; +} swseq_data; static uint8_t lookup_spi_type(uint8_t opcode) { @@ -475,10 +564,10 @@ break; case CHIPSET_ICH8: default: /* Future version might behave the same */ - preop = REGREAD16(ICH9_REG_PREOP); - optype = REGREAD16(ICH9_REG_OPTYPE); - opmenu[0] = REGREAD32(ICH9_REG_OPMENU); - opmenu[1] = REGREAD32(ICH9_REG_OPMENU + 4); + preop = REGREAD16(swseq_data.reg_preop); + optype = REGREAD16(swseq_data.reg_optype); + opmenu[0] = REGREAD32(swseq_data.reg_opmenu); + opmenu[1] = REGREAD32(swseq_data.reg_opmenu + 4); break; } @@ -558,15 +647,15 @@ default: /* Future version might behave the same */ /* Register undo only for enable_undo=1, i.e. first call. */ if (enable_undo) { - rmmio_valw(ich_spibar + ICH9_REG_PREOP); - rmmio_valw(ich_spibar + ICH9_REG_OPTYPE); - rmmio_vall(ich_spibar + ICH9_REG_OPMENU); - rmmio_vall(ich_spibar + ICH9_REG_OPMENU + 4); + rmmio_valw(ich_spibar + swseq_data.reg_preop); + rmmio_valw(ich_spibar + swseq_data.reg_optype); + rmmio_vall(ich_spibar + swseq_data.reg_opmenu); + rmmio_vall(ich_spibar + swseq_data.reg_opmenu + 4); } - mmio_writew(preop, ich_spibar + ICH9_REG_PREOP); - mmio_writew(optype, ich_spibar + ICH9_REG_OPTYPE); - mmio_writel(opmenu[0], ich_spibar + ICH9_REG_OPMENU); - mmio_writel(opmenu[1], ich_spibar + ICH9_REG_OPMENU + 4); + mmio_writew(preop, ich_spibar + swseq_data.reg_preop); + mmio_writew(optype, ich_spibar + swseq_data.reg_optype); + mmio_writel(opmenu[0], ich_spibar + swseq_data.reg_opmenu); + mmio_writel(opmenu[1], ich_spibar + swseq_data.reg_opmenu + 4); break; } @@ -853,7 +942,7 @@ } timeout = 100 * 60; /* 60 ms are 9.6 million cycles at 16 MHz. */ - while ((REGREAD8(ICH9_REG_SSFS) & SSFS_SCIP) && --timeout) { + while ((REGREAD8(swseq_data.reg_ssfsc) & SSFS_SCIP) && --timeout) { programmer_delay(10); } if (!timeout) { @@ -871,12 +960,12 @@ ich_fill_data(data, datalength, ICH9_REG_FDATA0); /* Assemble SSFS + SSFC */ - temp32 = REGREAD32(ICH9_REG_SSFS); + temp32 = REGREAD32(swseq_data.reg_ssfsc); /* Keep reserved bits only */ temp32 &= SSFS_RESERVED_MASK | SSFC_RESERVED_MASK; /* Clear cycle done and cycle error status registers */ temp32 |= (SSFS_FDONE | SSFS_FCERR); - REGWRITE32(ICH9_REG_SSFS, temp32); + REGWRITE32(swseq_data.reg_ssfsc, temp32); /* Use 20 MHz */ temp32 |= SSFC_SCF_20MHZ; @@ -930,21 +1019,21 @@ temp32 |= SSFC_SCGO; /* write it */ - REGWRITE32(ICH9_REG_SSFS, temp32); + REGWRITE32(swseq_data.reg_ssfsc, temp32); /* Wait for Cycle Done Status or Flash Cycle Error. */ - while (((REGREAD32(ICH9_REG_SSFS) & (SSFS_FDONE | SSFS_FCERR)) == 0) && + while (((REGREAD32(swseq_data.reg_ssfsc) & (SSFS_FDONE | SSFS_FCERR)) == 0) && --timeout) { programmer_delay(10); } if (!timeout) { - msg_perr("timeout, ICH9_REG_SSFS=0x%08x\n", - REGREAD32(ICH9_REG_SSFS)); + msg_perr("timeout, REG_SSFS=0x%08x\n", + REGREAD32(swseq_data.reg_ssfsc)); return 1; } /* FIXME make sure we do not needlessly cause transaction errors. */ - temp32 = REGREAD32(ICH9_REG_SSFS); + temp32 = REGREAD32(swseq_data.reg_ssfsc); if (temp32 & SSFS_FCERR) { msg_perr("Transaction error!\n"); prettyprint_ich9_reg_ssfs(temp32); @@ -952,7 +1041,7 @@ /* keep reserved bits */ temp32 &= SSFS_RESERVED_MASK | SSFC_RESERVED_MASK; /* Clear the transaction error. */ - REGWRITE32(ICH9_REG_SSFS, temp32 | SSFS_FCERR); + REGWRITE32(swseq_data.reg_ssfsc, temp32 | SSFS_FCERR); return 1; } @@ -1117,13 +1206,16 @@ static struct hwseq_data { uint32_t size_comp0; uint32_t size_comp1; + uint32_t addr_mask; + bool only_4k; + uint32_t hsfc_fcycle; } hwseq_data; -/* Sets FLA in FADDR to (addr & 0x01FFFFFF) without touching other bits. */ +/* Sets FLA in FADDR to (addr & hwseq_data.addr_mask) without touching other bits. */ static void ich_hwseq_set_addr(uint32_t addr) { - uint32_t addr_old = REGREAD32(ICH9_REG_FADDR) & ~0x01FFFFFF; - REGWRITE32(ICH9_REG_FADDR, (addr & 0x01FFFFFF) | addr_old); + uint32_t addr_old = REGREAD32(ICH9_REG_FADDR) & ~hwseq_data.addr_mask; + REGWRITE32(ICH9_REG_FADDR, (addr & hwseq_data.addr_mask) | addr_old); } /* Sets FADDR.FLA to 'addr' and returns the erase block size in bytes @@ -1135,18 +1227,21 @@ */ static uint32_t ich_hwseq_get_erase_block_size(unsigned int addr) { - uint8_t enc_berase; - static const uint32_t dec_berase[4] = { - 256, - 4 * 1024, - 8 * 1024, - 64 * 1024 - }; + if (hwseq_data.only_4k) { + return 4 * 1024; + } else { + uint8_t enc_berase; + static const uint32_t dec_berase[4] = { + 256, + 4 * 1024, + 8 * 1024, + 64 * 1024 + }; - ich_hwseq_set_addr(addr); - enc_berase = (REGREAD16(ICH9_REG_HSFS) & HSFS_BERASE) >> - HSFS_BERASE_OFF; - return dec_berase[enc_berase]; + ich_hwseq_set_addr(addr); + enc_berase = (REGREAD16(ICH9_REG_HSFS) & HSFS_BERASE) >> HSFS_BERASE_OFF; + return dec_berase[enc_berase]; + } } /* Polls for Cycle Done Status, Flash Cycle Error or timeout in 8 us intervals. @@ -1167,7 +1262,7 @@ } REGWRITE16(ICH9_REG_HSFS, REGREAD16(ICH9_REG_HSFS)); if (!timeout) { - addr = REGREAD32(ICH9_REG_FADDR) & 0x01FFFFFF; + addr = REGREAD32(ICH9_REG_FADDR) & hwseq_data.addr_mask; msg_perr("Timeout error between offset 0x%08x and " "0x%08x (= 0x%08x + %d)!\n", addr, addr + len - 1, addr, len - 1); @@ -1177,7 +1272,7 @@ } if (hsfs & HSFS_FCERR) { - addr = REGREAD32(ICH9_REG_FADDR) & 0x01FFFFFF; + addr = REGREAD32(ICH9_REG_FADDR) & hwseq_data.addr_mask; msg_perr("Transaction error between offset 0x%08x and " "0x%08x (= 0x%08x + %d)!\n", addr, addr + len - 1, addr, len - 1); @@ -1205,7 +1300,10 @@ flash->chip->total_size = total_size / 1024; eraser = &(flash->chip->block_erasers[0]); - boundary = (REGREAD32(ICH9_REG_FPB) & FPB_FPBA) << 12; + if (!hwseq_data.only_4k) + boundary = (REGREAD32(ICH9_REG_FPB) & FPB_FPBA) << 12; + else + boundary = 0; size_high = total_size - boundary; erase_size_high = ich_hwseq_get_erase_block_size(boundary); @@ -1279,7 +1377,7 @@ REGWRITE16(ICH9_REG_HSFS, REGREAD16(ICH9_REG_HSFS)); hsfc = REGREAD16(ICH9_REG_HSFC); - hsfc &= ~HSFC_FCYCLE; /* clear operation */ + hsfc &= ~hwseq_data.hsfc_fcycle; /* clear operation */ hsfc |= (0x3 << HSFC_FCYCLE_OFF); /* set erase operation */ hsfc |= HSFC_FGO; /* start */ msg_pdbg("HSFC used for block erasing: "); @@ -1316,7 +1414,7 @@ ich_hwseq_set_addr(addr); hsfc = REGREAD16(ICH9_REG_HSFC); - hsfc &= ~HSFC_FCYCLE; /* set read operation */ + hsfc &= ~hwseq_data.hsfc_fcycle; /* set read operation */ hsfc &= ~HSFC_FDBC; /* clear byte count */ /* set byte count */ hsfc |= (((block_len - 1) << HSFC_FDBC_OFF) & HSFC_FDBC); @@ -1357,7 +1455,7 @@ block_len = min(block_len, 256 - (addr & 0xFF)); ich_fill_data(buf, block_len, ICH9_REG_FDATA0); hsfc = REGREAD16(ICH9_REG_HSFC); - hsfc &= ~HSFC_FCYCLE; /* clear operation */ + hsfc &= ~hwseq_data.hsfc_fcycle; /* clear operation */ hsfc |= (0x2 << HSFC_FCYCLE_OFF); /* set write operation */ hsfc &= ~HSFC_FDBC; /* clear byte count */ /* set byte count */ @@ -1449,6 +1547,8 @@ "Flash Descriptor", "BIOS", "Management Engine", "Gigabit Ethernet", "Platform Data" }; + const char *const region_name = i < ARRAY_SIZE(region_names) ? region_names[i] : "unknown"; + uint32_t base, limit; int rwperms = (((ICH_BRWA(frap) >> i) & 1) << 1) | (((ICH_BRRA(frap) >> i) & 1) << 0); @@ -1460,19 +1560,19 @@ if (base > limit || (freg == 0 && i > 0)) { /* this FREG is disabled */ msg_pdbg2("0x%02X: 0x%08x FREG%i: %s region is unused.\n", - offset, freg, i, region_names[i]); + offset, freg, i, region_name); return 0; } msg_pdbg("0x%02X: 0x%08x ", offset, freg); if (rwperms == 0x3) { msg_pdbg("FREG%i: %s region (0x%08x-0x%08x) is %s.\n", i, - region_names[i], base, (limit | 0x0fff), + region_name, base, (limit | 0x0fff), access_names[rwperms]); return 0; } msg_pwarn("FREG%i: Warning: %s region (0x%08x-0x%08x) is %s.\n", i, - region_names[i], base, (limit | 0x0fff), + region_name, base, (limit | 0x0fff), access_names[rwperms]); return 1; } @@ -1487,31 +1587,36 @@ ((~((pr) >> PR_WP_OFF) & 1) << 1)) /* returns 0 if range is unused (i.e. r/w) */ -static int ich9_handle_pr(int i) +static int ich9_handle_pr(const size_t reg_pr0, int i) { static const char *const access_names[3] = { "locked", "read-only", "write-only" }; - uint8_t off = ICH9_REG_PR0 + (i * 4); + uint8_t off = reg_pr0 + (i * 4); uint32_t pr = mmio_readl(ich_spibar + off); unsigned int rwperms = ICH_PR_PERMS(pr); + /* From 5 on we have GPR registers and start from 0 again. */ + const char *const prefix = i >= 5 ? "G" : ""; + if (i >= 5) + i -= 5; + if (rwperms == 0x3) { - msg_pdbg2("0x%02X: 0x%08x (PR%u is unused)\n", off, pr, i); + msg_pdbg2("0x%02X: 0x%08x (%sPR%u is unused)\n", off, pr, prefix, i); return 0; } msg_pdbg("0x%02X: 0x%08x ", off, pr); - msg_pwarn("PR%u: Warning: 0x%08x-0x%08x is %s.\n", i, ICH_FREG_BASE(pr), + msg_pwarn("%sPR%u: Warning: 0x%08x-0x%08x is %s.\n", prefix, i, ICH_FREG_BASE(pr), ICH_FREG_LIMIT(pr) | 0x0fff, access_names[rwperms]); return 1; } /* Set/Clear the read and write protection enable bits of PR register @i * according to @read_prot and @write_prot. */ -static void ich9_set_pr(int i, int read_prot, int write_prot) +static void ich9_set_pr(const size_t reg_pr0, int i, int read_prot, int write_prot) { - void *addr = ich_spibar + ICH9_REG_PR0 + (i * 4); + void *addr = ich_spibar + reg_pr0 + (i * 4); uint32_t old = mmio_readl(addr); uint32_t new; @@ -1576,9 +1681,35 @@ ich_hwseq, ich_swseq } ich_spi_mode = ich_auto; + size_t num_freg, num_pr, reg_pr0; ich_generation = ich_gen; ich_spibar = spibar; + + /* Moving registers / bits */ + if (ich_generation == CHIPSET_100_SERIES_SUNRISE_POINT) { + num_freg = 10; + num_pr = 6; + reg_pr0 = PCH100_REG_FPR0; + swseq_data.reg_ssfsc = PCH100_REG_SSFSC; + swseq_data.reg_preop = PCH100_REG_PREOP; + swseq_data.reg_optype = PCH100_REG_OPTYPE; + swseq_data.reg_opmenu = PCH100_REG_OPMENU; + hwseq_data.addr_mask = PCH100_FADDR_FLA; + hwseq_data.only_4k = true; + hwseq_data.hsfc_fcycle = PCH100_HSFC_FCYCLE; + } else { + num_freg = 5; + num_pr = 5; + reg_pr0 = ICH9_REG_PR0; + swseq_data.reg_ssfsc = ICH9_REG_SSFS; + swseq_data.reg_preop = ICH9_REG_PREOP; + swseq_data.reg_optype = ICH9_REG_OPTYPE; + swseq_data.reg_opmenu = ICH9_REG_OPMENU; + hwseq_data.addr_mask = ICH9_FADDR_FLA; + hwseq_data.only_4k = false; + hwseq_data.hsfc_fcycle = HSFC_FCYCLE; + } switch (ich_generation) { case CHIPSET_ICH7: @@ -1679,6 +1810,12 @@ tmp = mmio_readl(ich_spibar + ICH9_REG_FADDR); msg_pdbg2("0x08: 0x%08x (FADDR)\n", tmp); + if (ich_gen == CHIPSET_100_SERIES_SUNRISE_POINT) { + const uint32_t dlock = mmio_readl(ich_spibar + PCH100_REG_DLOCK); + msg_pdbg("0x0c: 0x%08x (DLOCK)\n", dlock); + prettyprint_pch100_reg_dlock(dlock); + } + if (desc_valid) { tmp = mmio_readl(ich_spibar + ICH9_REG_FRAP); msg_pdbg("0x50: 0x%08x (FRAP)\n", tmp); @@ -1688,7 +1825,7 @@ msg_pdbg("BRRA 0x%02x\n", ICH_BRRA(tmp)); /* Handle FREGx and FRAP registers */ - for (i = 0; i < 5; i++) + for (i = 0; i < num_freg; i++) ich_spi_rw_restricted |= ich9_handle_frap(tmp, i); if (ich_spi_rw_restricted) msg_pwarn("Not all flash regions are freely accessible by flashrom. This is " @@ -1697,11 +1834,11 @@ } /* Handle PR registers */ - for (i = 0; i < 5; i++) { + for (i = 0; i < num_pr; i++) { /* if not locked down try to disable PR locks first */ if (!ichspi_lock) - ich9_set_pr(i, 0, 0); - ich_spi_rw_restricted |= ich9_handle_pr(i); + ich9_set_pr(reg_pr0, i, 0, 0); + ich_spi_rw_restricted |= ich9_handle_pr(reg_pr0, i); } if (ich_spi_rw_restricted) { @@ -1716,30 +1853,30 @@ msg_pinfo("Continuing with write support because the user forced us to!\n"); } - tmp = mmio_readl(ich_spibar + ICH9_REG_SSFS); - msg_pdbg("0x90: 0x%02x (SSFS)\n", tmp & 0xff); + tmp = mmio_readl(ich_spibar + swseq_data.reg_ssfsc); + msg_pdbg("0x%zx: 0x%02x (SSFS)\n", swseq_data.reg_ssfsc, tmp & 0xff); prettyprint_ich9_reg_ssfs(tmp); if (tmp & SSFS_FCERR) { msg_pdbg("Clearing SSFS.FCERR\n"); - mmio_writeb(SSFS_FCERR, ich_spibar + ICH9_REG_SSFS); + mmio_writeb(SSFS_FCERR, ich_spibar + swseq_data.reg_ssfsc); } - msg_pdbg("0x91: 0x%06x (SSFC)\n", tmp >> 8); + msg_pdbg("0x%zx: 0x%06x (SSFC)\n", swseq_data.reg_ssfsc + 1, tmp >> 8); prettyprint_ich9_reg_ssfc(tmp); - msg_pdbg("0x94: 0x%04x (PREOP)\n", - mmio_readw(ich_spibar + ICH9_REG_PREOP)); - msg_pdbg("0x96: 0x%04x (OPTYPE)\n", - mmio_readw(ich_spibar + ICH9_REG_OPTYPE)); - msg_pdbg("0x98: 0x%08x (OPMENU)\n", - mmio_readl(ich_spibar + ICH9_REG_OPMENU)); - msg_pdbg("0x9C: 0x%08x (OPMENU+4)\n", - mmio_readl(ich_spibar + ICH9_REG_OPMENU + 4)); + msg_pdbg("0x%zx: 0x%04x (PREOP)\n", + swseq_data.reg_preop, mmio_readw(ich_spibar + swseq_data.reg_preop)); + msg_pdbg("0x%zx: 0x%04x (OPTYPE)\n", + swseq_data.reg_optype, mmio_readw(ich_spibar + swseq_data.reg_optype)); + msg_pdbg("0x%zx: 0x%08x (OPMENU)\n", + swseq_data.reg_opmenu, mmio_readl(ich_spibar + swseq_data.reg_opmenu)); + msg_pdbg("0x%zx: 0x%08x (OPMENU+4)\n", + swseq_data.reg_opmenu + 4, mmio_readl(ich_spibar + swseq_data.reg_opmenu + 4)); if (ich_generation == CHIPSET_ICH8 && desc_valid) { tmp = mmio_readl(ich_spibar + ICH8_REG_VSCC); msg_pdbg("0xC1: 0x%08x (VSCC)\n", tmp); msg_pdbg("VSCC: "); prettyprint_ich_reg_vscc(tmp, FLASHROM_MSG_DEBUG, true); - } else { + } else if (ich_generation != CHIPSET_100_SERIES_SUNRISE_POINT) { if (ich_generation != CHIPSET_BAYTRAIL && desc_valid) { ichspi_bbar = mmio_readl(ich_spibar + ICH9_REG_BBAR); msg_pdbg("0xA0: 0x%08x (BBAR)\n", @@ -1764,7 +1901,7 @@ } if (desc_valid) { - if (read_ich_descriptors_via_fdo(ich_spibar, &desc) == ICH_RET_OK) + if (read_ich_descriptors_via_fdo(ich_gen, ich_spibar, &desc) == ICH_RET_OK) prettyprint_ich_descriptors(ich_gen, &desc); /* If the descriptor is valid and indicates multiple -- To view, visit https://review.coreboot.org/21806 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: stable Gerrit-MessageType: newchange Gerrit-Change-Id: Ifc5a5fc9ad22a8151e66850ef70c5cf406a83a37 Gerrit-Change-Number: 21806 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de>

1 0

Change in flashrom[stable]: hwaccess: Constify `addr` argument of MMIO read functions
by build bot (Jenkins) (Code Review) 30 Sep '17

30 Sep '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21784 ) Change subject: hwaccess: Constify `addr` argument of MMIO read functions ...................................................................... Patch Set 1: Verified-1 Build Failed https://qa.coreboot.org/job/flashrom-customrules/578/ : FAILURE https://qa.coreboot.org/job/flashrom_gerrit/523/ : SUCCESS -- To view, visit https://review.coreboot.org/21784 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: stable Gerrit-MessageType: comment Gerrit-Change-Id: I9158e8a7b994fe84e71a39483db651843adcf892 Gerrit-Change-Number: 21784 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 30 Sep 2017 20:48:44 +0000 Gerrit-HasComments: No

1 0

Change in flashrom[stable]: chipset_enable: Add support for Intel Skylake / Kabylake
by Nico Huber (Code Review) 30 Sep '17

30 Sep '17

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/21805 Change subject: chipset_enable: Add support for Intel Skylake / Kabylake ...................................................................... chipset_enable: Add support for Intel Skylake / Kabylake All publicly known Skylake / Kabylake / Sunrise Point PCH variants share the same register interface [1..6]. Although all SPI configu- ration is now done through the SPI PCI device 1f.5, we can't probe for it directly since its PCI vendor and device IDs are usually hid- den. To work around the hidden IDs, we use another PCI accessor that doesn't rely on the OS seeing the PCI device. This handles SPI flashes only. While booting from LPC is still sup- ported, it seems nobody uses it any more. Some additional PCI IDs were gathered from driveridentifier.com. TEST=Compiled with B150 set to NT (instead of BAD) and checked for sane register readings. [1] 6th Generation Intel® Core(TM) Processor Families I/O Platform Datasheet - Volume 1 of 2 Revision 002EN Document Number 332995 [2] 6th Generation Intel® Processor I/O Datasheet for U/Y Platforms Volume 2 of 2 Revision 001EN Document Number 332996 [3] 7th Generation Intel® Processor Families I/O Platform Datasheet - Volume 1 of 2 Revision 002 Document Number 334658 [4] 7th Generation Intel® Processor Families I/O for U/Y Platforms Datasheet - Volume 2 of 2 Revision 002 Document Number 334659 [5] Intel® 100 Series and Intel® C230 Series Chipset Family Platform Controller Hub (PCH) Datasheet - Volume 1 of 2 Revision 004EN Document Number 332690 [6] Intel® 100 Series Chipset Family Platform Controller Hub (PCH) Datasheet - Volume 2 of 2 Revision 001EN Document Number 332691 Original-Change-Id: I000819aff25fbe9764f33df85f040093b82cd948 Original-Reviewed-on: https://review.coreboot.org/18925 Original-Reviewed-by: David Hendricks <david.hendricks(a)gmail.com> Original-Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Original-Reviewed-by: Youness Alaoui <snifikino(a)gmail.com> Change-Id: I29ff1546c6236d948c6136ea2acca5017c4f284f Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- M chipset_enable.c M programmer.h 2 files changed, 111 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/05/21805/1 diff --git a/chipset_enable.c b/chipset_enable.c index 83c470f..a85ae21 100644 --- a/chipset_enable.c +++ b/chipset_enable.c @@ -7,6 +7,8 @@ * Copyright (C) 2007,2008,2009 Carl-Daniel Hailfinger * Copyright (C) 2009 Kontron Modular Computers GmbH * Copyright (C) 2011, 2012 Stefan Tauner + * Copyright (C) 2017 secunet Security Networks AG + * (Written by Nico Huber <nico.huber(a)secunet.com> for secunet) * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -588,21 +590,32 @@ const uint8_t *const rcrb) { uint32_t gcs; - bool top_swap; + const char *reg_name; + bool bild, top_swap; switch (ich_generation) { case CHIPSET_BAYTRAIL: + reg_name = "GCS"; gcs = mmio_readl(rcrb + 0); + bild = gcs & 1; top_swap = (gcs & 2) >> 1; break; + case CHIPSET_100_SERIES_SUNRISE_POINT: + reg_name = "BIOS_SPI_BC"; + gcs = pci_read_long(dev, 0xdc); + bild = (gcs >> 7) & 1; + top_swap = (gcs >> 4) & 1; + break; default: + reg_name = "GCS"; gcs = mmio_readl(rcrb + 0x3410); + bild = gcs & 1; top_swap = mmio_readb(rcrb + 0x3414) & 1; break; } - msg_pdbg("GCS = 0x%x: ", gcs); - msg_pdbg("BIOS Interface Lock-Down: %sabled, ", (gcs & 0x1) ? "en" : "dis"); + msg_pdbg("%s = 0x%x: ", reg_name, gcs); + msg_pdbg("BIOS Interface Lock-Down: %sabled, ", bild ? "en" : "dis"); static const char *const straps_names_EP80579[] = { "SPI", "reserved", "reserved", "LPC" }; static const char *const straps_names_ich7_nm10[] = { "reserved", "SPI", "PCI", "LPC" }; @@ -644,6 +657,7 @@ break; case CHIPSET_8_SERIES_LYNX_POINT_LP: case CHIPSET_9_SERIES_WILDCAT_POINT_LP: + case CHIPSET_100_SERIES_SUNRISE_POINT: straps_names = straps_names_pch8_lp; break; case CHIPSET_8_SERIES_WELLSBURG: // FIXME: check datasheet @@ -665,6 +679,9 @@ case CHIPSET_9_SERIES_WILDCAT_POINT_LP: /* LP PCHs use a single bit for BBS */ bbs = (gcs >> 10) & 0x1; + break; + case CHIPSET_100_SERIES_SUNRISE_POINT: + bbs = (gcs >> 6) & 0x1; break; default: /* Other chipsets use two bits for BBS */ @@ -804,6 +821,66 @@ static int enable_flash_pch9_lp(struct pci_dev *dev, const char *name) { return enable_flash_ich_spi(dev, CHIPSET_9_SERIES_WILDCAT_POINT_LP, 0xdc); +} + +/* Sunrise Point */ +static int enable_flash_pch100_shutdown(void *const pci_acc) +{ + pci_cleanup(pci_acc); + return 0; +} + +static int enable_flash_pch100(struct pci_dev *const dev, const char *const name) +{ + const enum ich_chipset pch_generation = CHIPSET_100_SERIES_SUNRISE_POINT; + int ret = ERROR_FATAL; + + /* + * The SPI PCI device is usually hidden (by hiding PCI vendor + * and device IDs). So we need a PCI access method that works + * even when the OS doesn't know the PCI device. We can't use + * this method globally since it would bring along other con- + * straints (e.g. on PCI domains, extended PCIe config space). + */ + struct pci_access *const pci_acc = pci_alloc(); + if (!pci_acc) { + msg_perr("Can't allocate PCI accessor.\n"); + return ret; + } + pci_acc->method = PCI_ACCESS_I386_TYPE1; + pci_init(pci_acc); + register_shutdown(enable_flash_pch100_shutdown, pci_acc); + + struct pci_dev *const spi_dev = pci_get_dev(pci_acc, dev->domain, dev->bus, 0x1f, 5); + if (!spi_dev) { + msg_perr("Can't allocate PCI device.\n"); + return ret; + } + + enable_flash_ich_report_gcs(spi_dev, pch_generation, NULL); + + const int ret_bc = enable_flash_ich_bios_cntl_config_space(spi_dev, pch_generation, 0xdc); + if (ret_bc == ERROR_FATAL) + goto _freepci_ret; + + const uint32_t phys_spibar = pci_read_long(spi_dev, PCI_BASE_ADDRESS_0) & 0xfffff000; + void *const spibar = rphysmap("SPIBAR", phys_spibar, 0x1000); + if (spibar == ERROR_PTR) + goto _freepci_ret; + msg_pdbg("SPIBAR = 0x%0*" PRIxPTR " (phys = 0x%08x)\n", PRIxPTR_WIDTH, (uintptr_t)spibar, phys_spibar); + + /* This adds BUS_SPI */ + const int ret_spi = ich_init_spi(spibar, pch_generation); + if (ret_spi != ERROR_FATAL) { + if (ret_bc || ret_spi) + ret = ERROR_NONFATAL; + else + ret = 0; + } + +_freepci_ret: + pci_free_dev(spi_dev); + return ret; } /* Silvermont architecture: Bay Trail(-T/-I), Avoton/Rangeley. @@ -1803,10 +1880,36 @@ {0x8086, 0x9cc7, NT, "Intel", "Broadwell Y Premium", enable_flash_pch9_lp}, {0x8086, 0x9cc9, NT, "Intel", "Broadwell Y Base", enable_flash_pch9_lp}, {0x8086, 0x9ccb, NT, "Intel", "Broadwell H", enable_flash_pch9}, - {0x8086, 0x9d41, BAD, "Intel", "Sunrise Point (Skylake LP Sample)", NULL}, - {0x8086, 0x9d43, BAD, "Intel", "Sunrise Point (Skylake-U Base)", NULL}, - {0x8086, 0x9d48, BAD, "Intel", "Sunrise Point (Skylake-U Premium)", NULL}, - {0x8086, 0x9d46, BAD, "Intel", "Sunrise Point (Skylake-Y Premium)", NULL}, + {0x8086, 0x9d41, BAD, "Intel", "Skylake / Kaby Lake Sample", enable_flash_pch100}, + {0x8086, 0x9d43, BAD, "Intel", "Skylake U Base", enable_flash_pch100}, + {0x8086, 0x9d46, BAD, "Intel", "Skylake Y Premium", enable_flash_pch100}, + {0x8086, 0x9d48, BAD, "Intel", "Skylake U Premium", enable_flash_pch100}, + {0x8086, 0x9d4b, BAD, "Intel", "Kaby Lake Y w/ iHDCP2.2 Prem.", enable_flash_pch100}, + {0x8086, 0x9d4e, BAD, "Intel", "Kaby Lake U w/ iHDCP2.2 Prem.", enable_flash_pch100}, + {0x8086, 0x9d50, BAD, "Intel", "Kaby Lake U w/ iHDCP2.2 Base", enable_flash_pch100}, + {0x8086, 0x9d51, BAD, "Intel", "Kabe Lake w/ iHDCP2.2 Sample", enable_flash_pch100}, + {0x8086, 0x9d53, BAD, "Intel", "Kaby Lake U Base", enable_flash_pch100}, + {0x8086, 0x9d56, BAD, "Intel", "Kaby Lake Y Premium", enable_flash_pch100}, + {0x8086, 0x9d58, BAD, "Intel", "Kaby Lake U Premium", enable_flash_pch100}, + {0x8086, 0xa141, BAD, "Intel", "Sunrise Point Desktop Sample", enable_flash_pch100}, + {0x8086, 0xa142, BAD, "Intel", "Sunrise Point Unknown Sample", enable_flash_pch100}, + {0x8086, 0xa143, BAD, "Intel", "H110", enable_flash_pch100}, + {0x8086, 0xa144, BAD, "Intel", "H170", enable_flash_pch100}, + {0x8086, 0xa145, BAD, "Intel", "Z170", enable_flash_pch100}, + {0x8086, 0xa146, BAD, "Intel", "Q170", enable_flash_pch100}, + {0x8086, 0xa147, BAD, "Intel", "Q150", enable_flash_pch100}, + {0x8086, 0xa148, BAD, "Intel", "B150", enable_flash_pch100}, + {0x8086, 0xa149, BAD, "Intel", "C236", enable_flash_pch100}, + {0x8086, 0xa14a, BAD, "Intel", "C232", enable_flash_pch100}, + {0x8086, 0xa14b, BAD, "Intel", "Sunrise Point Server Sample", enable_flash_pch100}, + {0x8086, 0xa14d, BAD, "Intel", "QM170", enable_flash_pch100}, + {0x8086, 0xa14e, BAD, "Intel", "HM170", enable_flash_pch100}, + {0x8086, 0xa150, BAD, "Intel", "CM236", enable_flash_pch100}, + {0x8086, 0xa151, BAD, "Intel", "QMS180", enable_flash_pch100}, + {0x8086, 0xa152, BAD, "Intel", "HM175", enable_flash_pch100}, + {0x8086, 0xa153, BAD, "Intel", "QM175", enable_flash_pch100}, + {0x8086, 0xa154, BAD, "Intel", "CM238", enable_flash_pch100}, + {0x8086, 0xa155, BAD, "Intel", "QMU185", enable_flash_pch100}, #endif {0}, }; diff --git a/programmer.h b/programmer.h index fd9da96..ec00bd9 100644 --- a/programmer.h +++ b/programmer.h @@ -650,6 +650,7 @@ CHIPSET_8_SERIES_WELLSBURG, CHIPSET_9_SERIES_WILDCAT_POINT, CHIPSET_9_SERIES_WILDCAT_POINT_LP, + CHIPSET_100_SERIES_SUNRISE_POINT, /* also 6th/7th gen Core i/o (LP) variants */ }; /* ichspi.c */ -- To view, visit https://review.coreboot.org/21805 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: stable Gerrit-MessageType: newchange Gerrit-Change-Id: I29ff1546c6236d948c6136ea2acca5017c4f284f Gerrit-Change-Number: 21805 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de>

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Change in flashrom[stable]: Drop redundant `enum msglevel`
by Nico Huber (Code Review) 30 Sep '17

30 Sep '17

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/21804 Change subject: Drop redundant `enum msglevel` ...................................................................... Drop redundant `enum msglevel` Use `enum flashrom_log_level` instead to avoid further confusion. Original-Change-Id: I1895cb8f60da3abf70c9c2953f52414cd2cc10a9 Original-Reviewed-on: https://review.coreboot.org/20268 Original-Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Original-Reviewed-by: Philippe Mathieu-Daudé <f4bug(a)amsat.org> Original-Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Original-Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Change-Id: I70df0d6564b8f0ea2f597d4d5346bc1bf4de006d Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- M cli_classic.c M cli_output.c M flash.h M ichspi.c M libflashrom.c M libflashrom.h 6 files changed, 38 insertions(+), 45 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/04/21804/1 diff --git a/cli_classic.c b/cli_classic.c index 4c3db4d..441fc91 100644 --- a/cli_classic.c +++ b/cli_classic.c @@ -203,7 +203,7 @@ break; case 'V': verbose_screen++; - if (verbose_screen > MSG_DEBUG2) + if (verbose_screen > FLASHROM_MSG_DEBUG2) verbose_logfile = verbose_screen; break; case 'E': diff --git a/cli_output.c b/cli_output.c index e697985..61a9af6 100644 --- a/cli_output.c +++ b/cli_output.c @@ -25,8 +25,8 @@ #include <errno.h> #include "flash.h" -int verbose_screen = MSG_INFO; -int verbose_logfile = MSG_DEBUG2; +enum flashrom_log_level verbose_screen = FLASHROM_MSG_INFO; +enum flashrom_log_level verbose_logfile = FLASHROM_MSG_DEBUG2; #ifndef STANDALONE static FILE *logfile = NULL; @@ -61,17 +61,17 @@ void start_logging(void) { - enum msglevel oldverbose_screen = verbose_screen; + enum flashrom_log_level oldverbose_screen = verbose_screen; /* Shut up the console. */ - verbose_screen = MSG_ERROR; + verbose_screen = FLASHROM_MSG_ERROR; print_version(); verbose_screen = oldverbose_screen; } #endif /* !STANDALONE */ /* Please note that level is the verbosity, not the importance of the message. */ -int flashrom_print_cb(enum msglevel level, const char *fmt, va_list ap) +int flashrom_print_cb(enum flashrom_log_level level, const char *fmt, va_list ap) { int ret = 0; FILE *output_type = stdout; @@ -79,20 +79,20 @@ va_list logfile_args; va_copy(logfile_args, ap); - if (level < MSG_INFO) + if (level < FLASHROM_MSG_INFO) output_type = stderr; if (level <= verbose_screen) { ret = vfprintf(output_type, fmt, ap); /* msg_*spew often happens inside chip accessors in possibly * time-critical operations. Don't slow them down by flushing. */ - if (level != MSG_SPEW) + if (level != FLASHROM_MSG_SPEW) fflush(output_type); } #ifndef STANDALONE if ((level <= verbose_logfile) && logfile) { ret = vfprintf(logfile, fmt, logfile_args); - if (level != MSG_SPEW) + if (level != FLASHROM_MSG_SPEW) fflush(logfile); } #endif /* !STANDALONE */ diff --git a/flash.h b/flash.h index b5eb99b..67c7d20 100644 --- a/flash.h +++ b/flash.h @@ -38,6 +38,7 @@ #undef max #endif +#include "libflashrom.h" #include "layout.h" #define ERROR_PTR ((void*)-1) @@ -312,47 +313,39 @@ void print_chip_support_status(const struct flashchip *chip); /* cli_output.c */ -extern int verbose_screen; -extern int verbose_logfile; +extern enum flashrom_log_level verbose_screen; +extern enum flashrom_log_level verbose_logfile; #ifndef STANDALONE int open_logfile(const char * const filename); int close_logfile(void); void start_logging(void); #endif -enum msglevel { - MSG_ERROR = 0, - MSG_WARN = 1, - MSG_INFO = 2, - MSG_DEBUG = 3, - MSG_DEBUG2 = 4, - MSG_SPEW = 5, -}; -int flashrom_print_cb(enum msglevel level, const char *fmt, va_list ap); +int flashrom_print_cb(enum flashrom_log_level level, const char *fmt, va_list ap); /* Let gcc and clang check for correct printf-style format strings. */ -int print(enum msglevel level, const char *fmt, ...) +int print(enum flashrom_log_level level, const char *fmt, ...) #ifdef __MINGW32__ __attribute__((format(gnu_printf, 2, 3))); #else __attribute__((format(printf, 2, 3))); #endif -#define msg_gerr(...) print(MSG_ERROR, __VA_ARGS__) /* general errors */ -#define msg_perr(...) print(MSG_ERROR, __VA_ARGS__) /* programmer errors */ -#define msg_cerr(...) print(MSG_ERROR, __VA_ARGS__) /* chip errors */ -#define msg_gwarn(...) print(MSG_WARN, __VA_ARGS__) /* general warnings */ -#define msg_pwarn(...) print(MSG_WARN, __VA_ARGS__) /* programmer warnings */ -#define msg_cwarn(...) print(MSG_WARN, __VA_ARGS__) /* chip warnings */ -#define msg_ginfo(...) print(MSG_INFO, __VA_ARGS__) /* general info */ -#define msg_pinfo(...) print(MSG_INFO, __VA_ARGS__) /* programmer info */ -#define msg_cinfo(...) print(MSG_INFO, __VA_ARGS__) /* chip info */ -#define msg_gdbg(...) print(MSG_DEBUG, __VA_ARGS__) /* general debug */ -#define msg_pdbg(...) print(MSG_DEBUG, __VA_ARGS__) /* programmer debug */ -#define msg_cdbg(...) print(MSG_DEBUG, __VA_ARGS__) /* chip debug */ -#define msg_gdbg2(...) print(MSG_DEBUG2, __VA_ARGS__) /* general debug2 */ -#define msg_pdbg2(...) print(MSG_DEBUG2, __VA_ARGS__) /* programmer debug2 */ -#define msg_cdbg2(...) print(MSG_DEBUG2, __VA_ARGS__) /* chip debug2 */ -#define msg_gspew(...) print(MSG_SPEW, __VA_ARGS__) /* general debug spew */ -#define msg_pspew(...) print(MSG_SPEW, __VA_ARGS__) /* programmer debug spew */ -#define msg_cspew(...) print(MSG_SPEW, __VA_ARGS__) /* chip debug spew */ +#define msg_gerr(...) print(FLASHROM_MSG_ERROR, __VA_ARGS__) /* general errors */ +#define msg_perr(...) print(FLASHROM_MSG_ERROR, __VA_ARGS__) /* programmer errors */ +#define msg_cerr(...) print(FLASHROM_MSG_ERROR, __VA_ARGS__) /* chip errors */ +#define msg_gwarn(...) print(FLASHROM_MSG_WARN, __VA_ARGS__) /* general warnings */ +#define msg_pwarn(...) print(FLASHROM_MSG_WARN, __VA_ARGS__) /* programmer warnings */ +#define msg_cwarn(...) print(FLASHROM_MSG_WARN, __VA_ARGS__) /* chip warnings */ +#define msg_ginfo(...) print(FLASHROM_MSG_INFO, __VA_ARGS__) /* general info */ +#define msg_pinfo(...) print(FLASHROM_MSG_INFO, __VA_ARGS__) /* programmer info */ +#define msg_cinfo(...) print(FLASHROM_MSG_INFO, __VA_ARGS__) /* chip info */ +#define msg_gdbg(...) print(FLASHROM_MSG_DEBUG, __VA_ARGS__) /* general debug */ +#define msg_pdbg(...) print(FLASHROM_MSG_DEBUG, __VA_ARGS__) /* programmer debug */ +#define msg_cdbg(...) print(FLASHROM_MSG_DEBUG, __VA_ARGS__) /* chip debug */ +#define msg_gdbg2(...) print(FLASHROM_MSG_DEBUG2, __VA_ARGS__) /* general debug2 */ +#define msg_pdbg2(...) print(FLASHROM_MSG_DEBUG2, __VA_ARGS__) /* programmer debug2 */ +#define msg_cdbg2(...) print(FLASHROM_MSG_DEBUG2, __VA_ARGS__) /* chip debug2 */ +#define msg_gspew(...) print(FLASHROM_MSG_SPEW, __VA_ARGS__) /* general debug spew */ +#define msg_pspew(...) print(FLASHROM_MSG_SPEW, __VA_ARGS__) /* programmer debug spew */ +#define msg_cspew(...) print(FLASHROM_MSG_SPEW, __VA_ARGS__) /* chip debug spew */ /* layout.c */ int register_include_arg(char *name); diff --git a/ichspi.c b/ichspi.c index 218e3b1..be13f91 100644 --- a/ichspi.c +++ b/ichspi.c @@ -1738,7 +1738,7 @@ tmp = mmio_readl(ich_spibar + ICH8_REG_VSCC); msg_pdbg("0xC1: 0x%08x (VSCC)\n", tmp); msg_pdbg("VSCC: "); - prettyprint_ich_reg_vscc(tmp, MSG_DEBUG, true); + prettyprint_ich_reg_vscc(tmp, FLASHROM_MSG_DEBUG, true); } else { if (ich_generation != CHIPSET_BAYTRAIL && desc_valid) { ichspi_bbar = mmio_readl(ich_spibar + ICH9_REG_BBAR); @@ -1751,12 +1751,12 @@ tmp = mmio_readl(ich_spibar + ICH9_REG_LVSCC); msg_pdbg("0xC4: 0x%08x (LVSCC)\n", tmp); msg_pdbg("LVSCC: "); - prettyprint_ich_reg_vscc(tmp, MSG_DEBUG, true); + prettyprint_ich_reg_vscc(tmp, FLASHROM_MSG_DEBUG, true); tmp = mmio_readl(ich_spibar + ICH9_REG_UVSCC); msg_pdbg("0xC8: 0x%08x (UVSCC)\n", tmp); msg_pdbg("UVSCC: "); - prettyprint_ich_reg_vscc(tmp, MSG_DEBUG, false); + prettyprint_ich_reg_vscc(tmp, FLASHROM_MSG_DEBUG, false); tmp = mmio_readl(ich_spibar + ICH9_REG_FPB); msg_pdbg("0xD0: 0x%08x (FPB)\n", tmp); diff --git a/libflashrom.c b/libflashrom.c index 962e96f..6e0f42c 100644 --- a/libflashrom.c +++ b/libflashrom.c @@ -84,13 +84,13 @@ global_log_callback = log_callback; } /** @private */ -int print(const enum msglevel level, const char *const fmt, ...) +int print(const enum flashrom_log_level level, const char *const fmt, ...) { if (global_log_callback) { int ret; va_list args; va_start(args, fmt); - ret = global_log_callback((enum flashrom_log_level)level, fmt, args); + ret = global_log_callback(level, fmt, args); va_end(args); return ret; } diff --git a/libflashrom.h b/libflashrom.h index c5d972e..d3f3ded 100644 --- a/libflashrom.h +++ b/libflashrom.h @@ -27,7 +27,7 @@ int flashrom_init(int perform_selfcheck); int flashrom_shutdown(void); /** @ingroup flashrom-general */ -enum flashrom_log_level { /* This has to match enum msglevel. */ +enum flashrom_log_level { FLASHROM_MSG_ERROR = 0, FLASHROM_MSG_WARN = 1, FLASHROM_MSG_INFO = 2, -- To view, visit https://review.coreboot.org/21804 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: stable Gerrit-MessageType: newchange Gerrit-Change-Id: I70df0d6564b8f0ea2f597d4d5346bc1bf4de006d Gerrit-Change-Number: 21804 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de>

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flashrom-gerrit September 2017