June 2017 - flashrom-gerrit - mail.coreboot.org

Change in flashrom[staging]: ich_descriptors: Fix more odd +1s
by build bot (Jenkins) (Code Review) 17 Jun '17

17 Jun '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19044 ) Change subject: ich_descriptors: Fix more odd +1s ...................................................................... Patch Set 4: Verified+1 Build Successful https://qa.coreboot.org/job/flashrom_gerrit/365/ : SUCCESS https://qa.coreboot.org/job/flashrom-customrules/375/ : SUCCESS -- To view, visit https://review.coreboot.org/19044 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: staging Gerrit-MessageType: comment Gerrit-Change-Id: Ifa5455c999e90ff9121aed29f542d71ac9ca2b1c Gerrit-Change-Number: 19044 Gerrit-PatchSet: 4 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Stefan Tauner <stefan.tauner(a)gmx.at> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 17 Jun 2017 00:17:32 +0000 Gerrit-HasComments: No

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Change in flashrom[staging]: Handle Intel Wildcat Point *LP* like Lynx Point LP
by build bot (Jenkins) (Code Review) 17 Jun '17

17 Jun '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/18883 ) Change subject: Handle Intel Wildcat Point *LP* like Lynx Point LP ...................................................................... Patch Set 6: Verified+1 Build Successful https://qa.coreboot.org/job/flashrom_gerrit/366/ : SUCCESS https://qa.coreboot.org/job/flashrom-customrules/376/ : SUCCESS -- To view, visit https://review.coreboot.org/18883 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: staging Gerrit-MessageType: comment Gerrit-Change-Id: I6b7ca3c0bde111b04ed7c745ed76d28d3d05f01c Gerrit-Change-Number: 18883 Gerrit-PatchSet: 6 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philippe Mathieu-Daudé <philippe.mathieu.daude(a)gmail.com> Gerrit-Reviewer: Stefan Tauner <stefan.tauner(a)gmx.at> Gerrit-Reviewer: Youness Alaoui <snifikino(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 17 Jun 2017 00:17:31 +0000 Gerrit-HasComments: No

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Change in flashrom[staging]: ich_descriptors: Add function to guess chipset version
by Nico Huber (Code Review) 17 Jun '17

17 Jun '17

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/20246 Change subject: ich_descriptors: Add function to guess chipset version ...................................................................... ich_descriptors: Add function to guess chipset version Add guess_ich_chipset() that takes fields from a descriptor dump and returns the lowest possible chipset version. Intel did several incompatible changes to the descriptor through the years. However, they forgot to add a version number. So we have to apply some heuristics to detect the chipset version in case of exter- nal flashing. Change-Id: Ie1736663dc33801b19d3e695c072c61a6c6345a2 Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- M ich_descriptors.c M ich_descriptors.h 2 files changed, 64 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/46/20246/1 diff --git a/ich_descriptors.c b/ich_descriptors.c index aab686a..9241389 100644 --- a/ich_descriptors.c +++ b/ich_descriptors.c @@ -702,6 +702,66 @@ msg_pdbg2("\n"); } +/* + * Guesses a minimum chipset version based on the maximum number of + * soft straps per generation. + */ +static enum ich_chipset guess_ich_chipset_from_content(const struct ich_desc_content *const content) +{ + if (content->ICCRIBA == 0x00) { + if (content->MSL == 0 && content->ISL <= 2) + return CHIPSET_ICH8; + else if (content->ISL <= 2) + return CHIPSET_ICH9; + else if (content->ISL <= 10) + return CHIPSET_ICH10; + else + return CHIPSET_5_SERIES_IBEX_PEAK; + } else if (content->ICCRIBA < 0x31 && content->FMSBA < 0x30) { + if (content->MSL == 0 && content->ISL <= 17) + return CHIPSET_BAYTRAIL; + else if (content->MSL <= 1 && content->ISL <= 18) + return CHIPSET_6_SERIES_COUGAR_POINT; + else if (content->MSL <= 1 && content->ISL <= 21) + return CHIPSET_8_SERIES_LYNX_POINT; + else + return CHIPSET_100_SERIES_SUNRISE_POINT; + } else { + return CHIPSET_100_SERIES_SUNRISE_POINT; + } +} + +/* + * As an additional measure, we check the read frequency like `ifdtool`. + * The frequency value 6 (17MHz) was reserved before Skylake and is the + * only valid value since. Skylake is currently the most important dis- + * tinction because of the dropped number of regions field (NR). + */ +enum ich_chipset guess_ich_chipset(const struct ich_desc_content *const content, + const struct ich_desc_component *const component) +{ + const enum ich_chipset guess = guess_ich_chipset_from_content(content); + + if (component->modes.freq_read == 6) { + if (guess <= CHIPSET_5_SERIES_IBEX_PEAK) + msg_pwarn("\nThe firmware descriptor has the read frequency set to 17MHz. However,\n" + "it doesn't look like a Skylake/Sunrise Point compatible descriptor.\n" + "Please report this message, the output of `ich_descriptors_tool` for\n" + "your descriptor and the output of `lspci -nn` to flashrom(a)flashrom.org\n\n"); + return CHIPSET_100_SERIES_SUNRISE_POINT; + } else { + if (guess == CHIPSET_100_SERIES_SUNRISE_POINT) { + msg_pwarn("\nThe firmware descriptor looks like a Skylake/Sunrise Point descriptor.\n" + "However, the read frequency isn't set to 17MHz (the only valid value).\n" + "Please report this message, the output of `ich_descriptors_tool` for\n" + "your descriptor and the output of `lspci -nn` to flashrom(a)flashrom.org\n\n"); + return CHIPSET_9_SERIES_WILDCAT_POINT; + } + } + + return guess; +} + /* len is the length of dump in bytes */ int read_ich_descriptors_from_dump(const uint32_t *dump, unsigned int len, struct ich_descriptors *desc) { diff --git a/ich_descriptors.h b/ich_descriptors.h index ec85e0c..920e098 100644 --- a/ich_descriptors.h +++ b/ich_descriptors.h @@ -93,9 +93,10 @@ union { /* 0x0c */ uint32_t FLMAP2; struct { - uint32_t FMSBA :8, /* Flash (G)MCH Strap Base Addr. */ - MSL :8, /* MCH Strap Length */ - :16; + uint32_t FMSBA :8, /* Flash (G)MCH Strap Base Addr. */ + MSL :8, /* MCH Strap Length */ + ICCRIBA :8, /* ICC Reg. Init Base Addr. (new since Sandy Bridge) */ + RIL :8; /* Register Init Length (new since Hawell) */ }; }; }; -- To view, visit https://review.coreboot.org/20246 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: staging Gerrit-MessageType: newchange Gerrit-Change-Id: Ie1736663dc33801b19d3e695c072c61a6c6345a2 Gerrit-Change-Number: 20246 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de>

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Change in flashrom[staging]: ich_descriptors: Update for Intel Skylake
by Nico Huber (Code Review) 17 Jun '17

17 Jun '17

Hello Stefan Tauner, Paul Menzel, David Hendricks, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/18973 to look at the new patch set (#9). Change subject: ich_descriptors: Update for Intel Skylake ...................................................................... ich_descriptors: Update for Intel Skylake Interpretation of component clocks changed. Also more regions and more masters are supported now. The number of regions (NR) is now static per chipset (10 in the 100 Series case) and not coded into the descriptor any more. v2: o Use guess_ich_chipset() for read_ich_descriptors_from_dump(). o Update region extraction in `ich_descriptors_tool`. TEST=Run `ich_descriptors_tool` over a 100 Series dump and checked that output looks sane. Run `ich_descriptors_tool` over dumps of five different older systems (1 x Sandy Bridge, 3 x Ivy Bridge, 1 x Haswell). Beside whitespace changes, regions not accounted by `NR` are not printed any more. Change-Id: Idd60a857d1ecffcb2e437af21134d9de44dcceb8 Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- M ich_descriptors.c M ich_descriptors.h M util/ich_descriptors_tool/ich_descriptors_tool.c 3 files changed, 265 insertions(+), 163 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/73/18973/9 -- To view, visit https://review.coreboot.org/18973 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: staging Gerrit-MessageType: newpatchset Gerrit-Change-Id: Idd60a857d1ecffcb2e437af21134d9de44dcceb8 Gerrit-Change-Number: 18973 Gerrit-PatchSet: 9 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Stefan Tauner <stefan.tauner(a)gmx.at> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in flashrom[staging]: ich_descriptors: Draw +0xfff into ICH_FREG_LIMIT()
by Nico Huber (Code Review) 17 Jun '17

17 Jun '17

Hello Stefan Tauner, David Hendricks, Paul Menzel, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/19046 to look at the new patch set (#6). Change subject: ich_descriptors: Draw +0xfff into ICH_FREG_LIMIT() ...................................................................... ich_descriptors: Draw +0xfff into ICH_FREG_LIMIT() The condition `base > limit` is still valid since `base` is always at least 4096 greater than `limit` in this case. Change-Id: I11ac0a50b3f32f47879e7cfb7a26068cd0572ede Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- M ich_descriptors.c M ich_descriptors.h M ichspi.c M util/ich_descriptors_tool/ich_descriptors_tool.c 4 files changed, 6 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/46/19046/6 -- To view, visit https://review.coreboot.org/19046 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: staging Gerrit-MessageType: newpatchset Gerrit-Change-Id: I11ac0a50b3f32f47879e7cfb7a26068cd0572ede Gerrit-Change-Number: 19046 Gerrit-PatchSet: 6 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Stefan Tauner <stefan.tauner(a)gmx.at> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in flashrom[staging]: ichspi: Add support for Intel Skylake
by Nico Huber (Code Review) 17 Jun '17

17 Jun '17

Hello Stefan Tauner, Youness Alaoui, David Hendricks, Paul Menzel, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/18962 to look at the new patch set (#7). Change subject: ichspi: Add support for Intel Skylake ...................................................................... ichspi: Add support for Intel Skylake The Sunrise Point PCH, paired with Skylake, has some minor changes in the HW sequencing interface: * Support for more flash regions moved PR* registers * Only 4KiB erase blocks are supported by the primary erase command * A second erase command for 64KiB pages was added * More commands were added for status register access etc. * A "Dedicated Lock Bits" register was added No support for the new commands was added. The SW sequencing interface seems to have moved register location and is not supported any more officially. It's also untested. Changes are loosely based on the Skylake support commit in Chromium OS by Ramya Vijaykumar: commit a9a64f9e4d52c39fcd3c5f7d7b88065baed189b1 Author: Ramya Vijaykumar <ramya.vijaykumar(a)intel.com> flashrom: Add Skylake platform support Change-Id: I0f4565a3c39f5fe3aec4fc8863605cebed1ad4ee Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- M ich_descriptors.c M ich_descriptors.h M ichspi.c 3 files changed, 227 insertions(+), 87 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/62/18962/7 -- To view, visit https://review.coreboot.org/18962 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: staging Gerrit-MessageType: newpatchset Gerrit-Change-Id: I0f4565a3c39f5fe3aec4fc8863605cebed1ad4ee Gerrit-Change-Number: 18962 Gerrit-PatchSet: 7 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Stefan Tauner <stefan.tauner(a)gmx.at> Gerrit-Reviewer: Youness Alaoui <snifikino(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in flashrom[staging]: chipset_enable: Add support for Intel Skylake / Kabylake
by Nico Huber (Code Review) 17 Jun '17

17 Jun '17

Hello Stefan Tauner, Youness Alaoui, Paul Menzel, Stefan Reinauer, David Hendricks, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/18925 to look at the new patch set (#6). Change subject: chipset_enable: Add support for Intel Skylake / Kabylake ...................................................................... chipset_enable: Add support for Intel Skylake / Kabylake All publicly known Skylake / Kabylake / Sunrise Point PCH variants share the same register interface [1..6]. Although all SPI configu- ration is now done through the SPI PCI device 1f.5, we can't probe for it directly since its PCI vendor and device IDs are usually hid- den. To work around the hidden IDs, we use another PCI accessor that doesn't rely on the OS seeing the PCI device. This handles SPI flashes only. While booting from LPC is still sup- ported, it seems nobody uses it any more. Some additional PCI IDs were gathered from driveridentifier.com. TEST=Compiled with B150 set to NT (instead of BAD) and checked for sane register readings. [1] 6th Generation Intel® Core(TM) Processor Families I/O Platform Datasheet - Volume 1 of 2 Revision 002EN Document Number 332995 [2] 6th Generation Intel® Processor I/O Datasheet for U/Y Platforms Volume 2 of 2 Revision 001EN Document Number 332996 [3] 7th Generation Intel® Processor Families I/O Platform Datasheet - Volume 1 of 2 Revision 002 Document Number 334658 [4] 7th Generation Intel® Processor Families I/O for U/Y Platforms Datasheet - Volume 2 of 2 Revision 002 Document Number 334659 [5] Intel® 100 Series and Intel® C230 Series Chipset Family Platform Controller Hub (PCH) Datasheet - Volume 1 of 2 Revision 004EN Document Number 332690 [6] Intel® 100 Series Chipset Family Platform Controller Hub (PCH) Datasheet - Volume 2 of 2 Revision 001EN Document Number 332691 Change-Id: I000819aff25fbe9764f33df85f040093b82cd948 Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- M chipset_enable.c M programmer.h 2 files changed, 111 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/25/18925/6 -- To view, visit https://review.coreboot.org/18925 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: staging Gerrit-MessageType: newpatchset Gerrit-Change-Id: I000819aff25fbe9764f33df85f040093b82cd948 Gerrit-Change-Number: 18925 Gerrit-PatchSet: 6 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Stefan Tauner <stefan.tauner(a)gmx.at> Gerrit-Reviewer: Youness Alaoui <snifikino(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in flashrom[staging]: ichspi: Drop `dev` parameter from init functions
by Nico Huber (Code Review) 17 Jun '17

17 Jun '17

Hello Philippe Mathieu-Daudé, Youness Alaoui, David Hendricks, Paul Menzel, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/19460 to look at the new patch set (#2). Change subject: ichspi: Drop `dev` parameter from init functions ...................................................................... ichspi: Drop `dev` parameter from init functions It's never used and has no clear contract (e.g. will the pointer stay valid beyond the call?). Change-Id: I0d4e7cc731364e86eff214b9022b842a577f9ef4 Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- M chipset_enable.c M ichspi.c M programmer.h 3 files changed, 8 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/60/19460/2 -- To view, visit https://review.coreboot.org/19460 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: staging Gerrit-MessageType: newpatchset Gerrit-Change-Id: I0d4e7cc731364e86eff214b9022b842a577f9ef4 Gerrit-Change-Number: 19460 Gerrit-PatchSet: 2 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philippe Mathieu-Daudé <philippe.mathieu.daude(a)gmail.com> Gerrit-Reviewer: Youness Alaoui <snifikino(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in flashrom[staging]: ich_descriptors: Fix more odd +1s
by Nico Huber (Code Review) 17 Jun '17

17 Jun '17

Hello Stefan Tauner, David Hendricks, Paul Menzel, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/19044 to look at the new patch set (#4). Change subject: ich_descriptors: Fix more odd +1s ...................................................................... ich_descriptors: Fix more odd +1s +1 on everything doesn't make software greater per se. v2: o Fix another +1. o Amend style of similar (not +1 suffering) code, too. Change-Id: Ifa5455c999e90ff9121aed29f542d71ac9ca2b1c Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- M ich_descriptors.c 1 file changed, 7 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/44/19044/4 -- To view, visit https://review.coreboot.org/19044 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: staging Gerrit-MessageType: newpatchset Gerrit-Change-Id: Ifa5455c999e90ff9121aed29f542d71ac9ca2b1c Gerrit-Change-Number: 19044 Gerrit-PatchSet: 4 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Stefan Tauner <stefan.tauner(a)gmx.at> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in flashrom[staging]: Enable continuous SPI reads
by Nico Huber (Code Review) 16 Jun '17

16 Jun '17

Nico Huber has posted comments on this change. ( https://review.coreboot.org/20223 ) Change subject: Enable continuous SPI reads ...................................................................... Patch Set 3: Code-Review+2 (1 comment) https://review.coreboot.org/#/c/20223/3//COMMIT_MSG Commit Message: https://review.coreboot.org/#/c/20223/3//COMMIT_MSG@8 PS3, Line 8: Please mention that we now completely remove the old chip-page walking. And that it likely was never necessary... -- To view, visit https://review.coreboot.org/20223 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: staging Gerrit-MessageType: comment Gerrit-Change-Id: Iadf909c9216578b1c5dacd4c4991bb436e32edc9 Gerrit-Change-Number: 20223 Gerrit-PatchSet: 3 Gerrit-Owner: Urja Rannikko <urjaman(a)gmail.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Stefan Tauner <stefan.tauner(a)gmx.at> Gerrit-Reviewer: Urja Rannikko <urjaman(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 16 Jun 2017 12:19:49 +0000 Gerrit-HasComments: Yes

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