April 2017 - flashrom-gerrit - mail.coreboot.org

Change in flashrom[staging]: ichspi: Add support for Intel Skylake
by build bot (Jenkins) (Code Review) 26 Apr '17

26 Apr '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/18962 ) Change subject: ichspi: Add support for Intel Skylake ...................................................................... Patch Set 4: Verified+1 Build Successful https://qa.coreboot.org/job/flashrom-customrules/254/ : SUCCESS https://qa.coreboot.org/job/flashrom_gerrit/263/ : SUCCESS -- To view, visit https://review.coreboot.org/18962 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I0f4565a3c39f5fe3aec4fc8863605cebed1ad4ee Gerrit-PatchSet: 4 Gerrit-Project: flashrom Gerrit-Branch: staging Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Stefan Tauner <stefan.tauner(a)gmx.at> Gerrit-Reviewer: build bot (Jenkins) Gerrit-HasComments: No

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Change in flashrom[staging]: Handle Intel Wildcat Point *LP* like Lynx Point LP
by build bot (Jenkins) (Code Review) 26 Apr '17

26 Apr '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/18883 ) Change subject: Handle Intel Wildcat Point *LP* like Lynx Point LP ...................................................................... Patch Set 5: Verified+1 Build Successful https://qa.coreboot.org/job/flashrom-customrules/252/ : SUCCESS https://qa.coreboot.org/job/flashrom_gerrit/261/ : SUCCESS -- To view, visit https://review.coreboot.org/18883 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I6b7ca3c0bde111b04ed7c745ed76d28d3d05f01c Gerrit-PatchSet: 5 Gerrit-Project: flashrom Gerrit-Branch: staging Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Stefan Tauner <stefan.tauner(a)gmx.at> Gerrit-Reviewer: Youness Alaoui <snifikino(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) Gerrit-HasComments: No

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Change in flashrom[staging]: ich_descriptors: Fix more odd +1's
by build bot (Jenkins) (Code Review) 26 Apr '17

26 Apr '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19044 ) Change subject: ich_descriptors: Fix more odd +1's ...................................................................... Patch Set 3: Verified+1 Build Successful https://qa.coreboot.org/job/flashrom-customrules/251/ : SUCCESS https://qa.coreboot.org/job/flashrom_gerrit/259/ : SUCCESS -- To view, visit https://review.coreboot.org/19044 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: Ifa5455c999e90ff9121aed29f542d71ac9ca2b1c Gerrit-PatchSet: 3 Gerrit-Project: flashrom Gerrit-Branch: staging Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Stefan Tauner <stefan.tauner(a)gmx.at> Gerrit-Reviewer: build bot (Jenkins) Gerrit-HasComments: No

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Change in flashrom[staging]: ichspi: Drop `dev` parameter from init functions
by Nico Huber (Code Review) 26 Apr '17

26 Apr '17

Nico Huber has uploaded a new change for review. ( https://review.coreboot.org/19460 ) Change subject: ichspi: Drop `dev` parameter from init functions ...................................................................... ichspi: Drop `dev` parameter from init functions It's never used and has no clear contract (e.g. will the pointer stay beyond the call?). Change-Id: I0d4e7cc731364e86eff214b9022b842a577f9ef4 Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- M chipset_enable.c M ichspi.c M programmer.h 3 files changed, 8 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/60/19460/1 diff --git a/chipset_enable.c b/chipset_enable.c index 208cd3a..83c470f 100644 --- a/chipset_enable.c +++ b/chipset_enable.c @@ -718,7 +718,7 @@ void *spibar = rcrb + spibar_offset; /* This adds BUS_SPI */ - int ret_spi = ich_init_spi(dev, spibar, ich_generation); + int ret_spi = ich_init_spi(spibar, ich_generation); if (ret_spi == ERROR_FATAL) return ret_spi; @@ -846,7 +846,7 @@ */ enable_flash_ich_bios_cntl_memmapped(ich_generation, spibar + 0xFC); - int ret_spi = ich_init_spi(dev, spibar, ich_generation); + int ret_spi = ich_init_spi(spibar, ich_generation); if (ret_spi == ERROR_FATAL) return ret_spi; @@ -949,12 +949,12 @@ return ERROR_FATAL; } - return via_init_spi(dev, spi0_mm_base); + return via_init_spi(spi0_mm_base); } static int enable_flash_vt8237s_spi(struct pci_dev *dev, const char *name) { - return via_init_spi(dev, pci_read_long(dev, 0xbc) << 8); + return via_init_spi(pci_read_long(dev, 0xbc) << 8); } static int enable_flash_cs5530(struct pci_dev *dev, const char *name) diff --git a/ichspi.c b/ichspi.c index e1395ee..218e3b1 100644 --- a/ichspi.c +++ b/ichspi.c @@ -1561,7 +1561,7 @@ .erase = ich_hwseq_block_erase, }; -int ich_init_spi(struct pci_dev *dev, void *spibar, enum ich_chipset ich_gen) +int ich_init_spi(void *spibar, enum ich_chipset ich_gen) { int i; uint16_t tmp2; @@ -1828,7 +1828,7 @@ .write_aai = default_spi_write_aai, }; -int via_init_spi(struct pci_dev *dev, uint32_t mmio_base) +int via_init_spi(uint32_t mmio_base) { int i; diff --git a/programmer.h b/programmer.h index 9beaf98..fd9da96 100644 --- a/programmer.h +++ b/programmer.h @@ -655,8 +655,8 @@ /* ichspi.c */ #if CONFIG_INTERNAL == 1 extern uint32_t ichspi_bbar; -int ich_init_spi(struct pci_dev *dev, void *spibar, enum ich_chipset ich_generation); -int via_init_spi(struct pci_dev *dev, uint32_t mmio_base); +int ich_init_spi(void *spibar, enum ich_chipset ich_generation); +int via_init_spi(uint32_t mmio_base); /* amd_imc.c */ int amd_imc_shutdown(struct pci_dev *dev); -- To view, visit https://review.coreboot.org/19460 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newchange Gerrit-Change-Id: I0d4e7cc731364e86eff214b9022b842a577f9ef4 Gerrit-PatchSet: 1 Gerrit-Project: flashrom Gerrit-Branch: staging Gerrit-Owner: Nico Huber <nico.h(a)gmx.de>

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Change in flashrom[staging]: Handle Intel Wildcat Point *LP* like Lynx Point LP
by Nico Huber (Code Review) 26 Apr '17

26 Apr '17

Hello Paul Menzel, David Hendricks, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/18883 to look at the new patch set (#5). Change subject: Handle Intel Wildcat Point *LP* like Lynx Point LP ...................................................................... Handle Intel Wildcat Point *LP* like Lynx Point LP The subtle difference was ignored when adding these chipsets. The integrated Wildcat Point LP PCH is documented in [1]. I'm not sure how to account for "Broadwell H" which seems not publicly documented. Maybe it's an unreleased HM9*, in which case the non-LP path should be correct. [1] Mobile 5th Generation Intel® Core(TM) Processor Family I/O, Intel® Core(TM) M Processor Family I/O, Mobile Intel® Pentium® Processor Family I/O, and Mobile Intel® Celeron® Processor Family I/O Datasheet Revision 004 Document Number: 330837 Change-Id: I6b7ca3c0bde111b04ed7c745ed76d28d3d05f01c Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- M chipset_enable.c M ich_descriptors.c M programmer.h 3 files changed, 21 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/83/18883/5 -- To view, visit https://review.coreboot.org/18883 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newpatchset Gerrit-Change-Id: I6b7ca3c0bde111b04ed7c745ed76d28d3d05f01c Gerrit-PatchSet: 5 Gerrit-Project: flashrom Gerrit-Branch: staging Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Stefan Tauner <stefan.tauner(a)gmx.at> Gerrit-Reviewer: Youness Alaoui <snifikino(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins)

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Change in flashrom[staging]: chipset_enable: Add support for Intel Skylake
by Nico Huber (Code Review) 26 Apr '17

26 Apr '17

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/18925 to look at the new patch set (#3). Change subject: chipset_enable: Add support for Intel Skylake ...................................................................... chipset_enable: Add support for Intel Skylake All publicly known Skylake / Sunrise Point PCH variants share the same register interface [1..4]. Although all SPI configuration is now done through the SPI PCI device 1f.5, we can't probe for it directly since its PCI vendor and device IDs are usually hidden. To work around the hidden IDs, we use another PCI accessor that doesn't rely on the OS seeing the PCI device. TEST=Compiled with B150 set to NT (instead of BAD) and checked for sane register readings. [1] 6th Generation Intel® Core(TM) Processor Families I/O Platform Datasheet - Volume 1 of 2 Revision 002EN Document Number 332995 [2] 6th Generation Intel® Processor I/O Datasheet for U/Y Platforms Volume 2 of 2 Revision 001EN Document Number 332996 [3] Intel® 100 Series and Intel® C230 Series Chipset Family Platform Controller Hub (PCH) Datasheet - Volume 1 of 2 Revision 004EN Document Number 332690 [4] Intel® 100 Series Chipset Family Platform Controller Hub (PCH) Datasheet - Volume 2 of 2 Revision 001EN Document Number 332691 Change-Id: I000819aff25fbe9764f33df85f040093b82cd948 Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- M chipset_enable.c M programmer.h 2 files changed, 89 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/25/18925/3 -- To view, visit https://review.coreboot.org/18925 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newpatchset Gerrit-Change-Id: I000819aff25fbe9764f33df85f040093b82cd948 Gerrit-PatchSet: 3 Gerrit-Project: flashrom Gerrit-Branch: staging Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Stefan Tauner <stefan.tauner(a)gmx.at> Gerrit-Reviewer: build bot (Jenkins)

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Change in flashrom[staging]: ichspi: Add support for Intel Skylake
by Nico Huber (Code Review) 26 Apr '17

26 Apr '17

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/18962 to look at the new patch set (#4). Change subject: ichspi: Add support for Intel Skylake ...................................................................... ichspi: Add support for Intel Skylake The Sunrise Point PCH, paired with Skylake, has some minor changes in the HW sequencing interface: * Support for more flash regions moved PR* registers * Only 4KiB erase blocks are supported by the primary erase command * A second erase command for 64KiB pages was added * More commands were added for status register access etc. * A "Dedicated Lock Bits" register was added No support for the new commands was added. The SW sequencing interface seems to have moved register location and is not supported any more officially. It's also untested. Changes are loosely based on the Skylake support commit in Chromium OS by Ramya Vijaykumar: commit a9a64f9e4d52c39fcd3c5f7d7b88065baed189b1 Author: Ramya Vijaykumar <ramya.vijaykumar(a)intel.com> flashrom: Add Skylake platform support Change-Id: I0f4565a3c39f5fe3aec4fc8863605cebed1ad4ee Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- M ich_descriptors.c M ich_descriptors.h M ichspi.c 3 files changed, 228 insertions(+), 88 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/62/18962/4 -- To view, visit https://review.coreboot.org/18962 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newpatchset Gerrit-Change-Id: I0f4565a3c39f5fe3aec4fc8863605cebed1ad4ee Gerrit-PatchSet: 4 Gerrit-Project: flashrom Gerrit-Branch: staging Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Stefan Tauner <stefan.tauner(a)gmx.at> Gerrit-Reviewer: build bot (Jenkins)

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Change in flashrom[staging]: ich_descriptors: Update for Intel Skylake
by Nico Huber (Code Review) 26 Apr '17

26 Apr '17

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/18973 to look at the new patch set (#6). Change subject: ich_descriptors: Update for Intel Skylake ...................................................................... ich_descriptors: Update for Intel Skylake Interpretation of component clocks changed. Also more regions and more masters are supported now. The number of regions (NR) is now static per chipset (10 in the 100 Series case) and not coded into the descriptor any more. TEST=Run `ich_descriptors_tool` over a 100 Series dump and checked that output looks sane. Run `ich_descriptors_tool` over dumps of five different older systems (1 x Sandy Bridge, 3 x Ivy Bridge, 1 x Haswell). Beside whitespace changes, regions not accounted by `NR` are not printed any more. Change-Id: Idd60a857d1ecffcb2e437af21134d9de44dcceb8 Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- M ich_descriptors.c M ich_descriptors.h M util/ich_descriptors_tool/ich_descriptors_tool.c 3 files changed, 227 insertions(+), 143 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/73/18973/6 -- To view, visit https://review.coreboot.org/18973 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newpatchset Gerrit-Change-Id: Idd60a857d1ecffcb2e437af21134d9de44dcceb8 Gerrit-PatchSet: 6 Gerrit-Project: flashrom Gerrit-Branch: staging Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Stefan Tauner <stefan.tauner(a)gmx.at> Gerrit-Reviewer: build bot (Jenkins)

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Change in flashrom[staging]: ich_descriptors_tool: Fix an off-by-one
by Nico Huber (Code Review) 26 Apr '17

26 Apr '17

Nico Huber has submitted this change and it was merged. ( https://review.coreboot.org/19045 ) Change subject: ich_descriptors_tool: Fix an off-by-one ...................................................................... ich_descriptors_tool: Fix an off-by-one Change-Id: I008abd78c7c42bf3f17e68c192cd79dd427c5cb5 Signed-off-by: Nico Huber <nico.huber(a)secunet.com> Reviewed-on: https://review.coreboot.org/19045 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- M util/ich_descriptors_tool/ich_descriptors_tool.c 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: Stefan Reinauer: Looks good to me, approved build bot (Jenkins): Verified diff --git a/util/ich_descriptors_tool/ich_descriptors_tool.c b/util/ich_descriptors_tool/ich_descriptors_tool.c index 0da27d2..250abf0 100644 --- a/util/ich_descriptors_tool/ich_descriptors_tool.c +++ b/util/ich_descriptors_tool/ich_descriptors_tool.c @@ -230,7 +230,7 @@ prettyprint_ich_descriptors(cs, &desc); pMAC = (uint8_t *) &buf[ICH_FREG_BASE(desc.region.reg3_base) >> 2]; - if (len >= ICH_FREG_BASE(desc.region.reg3_base) + 5 && pMAC[0] != 0xff) + if (len >= ICH_FREG_BASE(desc.region.reg3_base) + 6 && pMAC[0] != 0xff) printf("The MAC address might be at offset 0x%x: " "%02x:%02x:%02x:%02x:%02x:%02x\n", ICH_FREG_BASE(desc.region.reg3_base), -- To view, visit https://review.coreboot.org/19045 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: merged Gerrit-Change-Id: I008abd78c7c42bf3f17e68c192cd79dd427c5cb5 Gerrit-PatchSet: 3 Gerrit-Project: flashrom Gerrit-Branch: staging Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Stefan Tauner <stefan.tauner(a)gmx.at> Gerrit-Reviewer: build bot (Jenkins)

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Change in flashrom[staging]: chipset_enable: Add support for Intel Skylake
by Nico Huber (Code Review) 26 Apr '17

26 Apr '17

Nico Huber has posted comments on this change. ( https://review.coreboot.org/18925 ) Change subject: chipset_enable: Add support for Intel Skylake ...................................................................... Patch Set 2: (1 comment) https://review.coreboot.org/#/c/18925/2/chipset_enable.c File chipset_enable.c: PS2, Line 869: spi_dev > We do anyways, despite the if constructs below. The parameter is unused in ich_init_spi(). I will just remove it. -- To view, visit https://review.coreboot.org/18925 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I000819aff25fbe9764f33df85f040093b82cd948 Gerrit-PatchSet: 2 Gerrit-Project: flashrom Gerrit-Branch: staging Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Stefan Tauner <stefan.tauner(a)gmx.at> Gerrit-Reviewer: build bot (Jenkins) Gerrit-HasComments: Yes

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