April 2017 - flashrom-gerrit - mail.coreboot.org

Change in flashrom[staging]: ichspi: Add support for Intel Skylake
by build bot (Jenkins) (Code Review) 26 Apr '17

26 Apr '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/18962 ) Change subject: ichspi: Add support for Intel Skylake ...................................................................... Patch Set 5: Verified+1 Build Successful https://qa.coreboot.org/job/flashrom-customrules/260/ : SUCCESS https://qa.coreboot.org/job/flashrom_gerrit/268/ : SUCCESS -- To view, visit https://review.coreboot.org/18962 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I0f4565a3c39f5fe3aec4fc8863605cebed1ad4ee Gerrit-PatchSet: 5 Gerrit-Project: flashrom Gerrit-Branch: staging Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Stefan Tauner <stefan.tauner(a)gmx.at> Gerrit-Reviewer: Youness Alaoui <snifikino(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) Gerrit-HasComments: No

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Change in flashrom[staging]: chipset_enable: Add support for Intel Skylake
by build bot (Jenkins) (Code Review) 26 Apr '17

26 Apr '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/18925 ) Change subject: chipset_enable: Add support for Intel Skylake ...................................................................... Patch Set 4: Verified+1 Build Successful https://qa.coreboot.org/job/flashrom-customrules/259/ : SUCCESS -- To view, visit https://review.coreboot.org/18925 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I000819aff25fbe9764f33df85f040093b82cd948 Gerrit-PatchSet: 4 Gerrit-Project: flashrom Gerrit-Branch: staging Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Stefan Tauner <stefan.tauner(a)gmx.at> Gerrit-Reviewer: Youness Alaoui <snifikino(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) Gerrit-HasComments: No

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Change in flashrom[staging]: chipset_enable: Set 100 series chipsets to NT
by Nico Huber (Code Review) 26 Apr '17

26 Apr '17

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/19047 to look at the new patch set (#3). Change subject: chipset_enable: Set 100 series chipsets to NT ...................................................................... chipset_enable: Set 100 series chipsets to NT Change-Id: I9376a0c180b7e73751fbd3c8c37b693d358cbfb8 Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- M chipset_enable.c 1 file changed, 13 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/47/19047/3 -- To view, visit https://review.coreboot.org/19047 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newpatchset Gerrit-Change-Id: I9376a0c180b7e73751fbd3c8c37b693d358cbfb8 Gerrit-PatchSet: 3 Gerrit-Project: flashrom Gerrit-Branch: staging Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins)

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Change in flashrom[staging]: ich_descriptors: Update for Intel Skylake
by Nico Huber (Code Review) 26 Apr '17

26 Apr '17

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/18973 to look at the new patch set (#7). Change subject: ich_descriptors: Update for Intel Skylake ...................................................................... ich_descriptors: Update for Intel Skylake Interpretation of component clocks changed. Also more regions and more masters are supported now. The number of regions (NR) is now static per chipset (10 in the 100 Series case) and not coded into the descriptor any more. TEST=Run `ich_descriptors_tool` over a 100 Series dump and checked that output looks sane. Run `ich_descriptors_tool` over dumps of five different older systems (1 x Sandy Bridge, 3 x Ivy Bridge, 1 x Haswell). Beside whitespace changes, regions not accounted by `NR` are not printed any more. Change-Id: Idd60a857d1ecffcb2e437af21134d9de44dcceb8 Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- M ich_descriptors.c M ich_descriptors.h M util/ich_descriptors_tool/ich_descriptors_tool.c 3 files changed, 227 insertions(+), 143 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/73/18973/7 -- To view, visit https://review.coreboot.org/18973 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newpatchset Gerrit-Change-Id: Idd60a857d1ecffcb2e437af21134d9de44dcceb8 Gerrit-PatchSet: 7 Gerrit-Project: flashrom Gerrit-Branch: staging Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Stefan Tauner <stefan.tauner(a)gmx.at> Gerrit-Reviewer: build bot (Jenkins)

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Change in flashrom[staging]: ichspi: Add support for Intel Skylake
by Nico Huber (Code Review) 26 Apr '17

26 Apr '17

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/18962 to look at the new patch set (#5). Change subject: ichspi: Add support for Intel Skylake ...................................................................... ichspi: Add support for Intel Skylake The Sunrise Point PCH, paired with Skylake, has some minor changes in the HW sequencing interface: * Support for more flash regions moved PR* registers * Only 4KiB erase blocks are supported by the primary erase command * A second erase command for 64KiB pages was added * More commands were added for status register access etc. * A "Dedicated Lock Bits" register was added No support for the new commands was added. The SW sequencing interface seems to have moved register location and is not supported any more officially. It's also untested. Changes are loosely based on the Skylake support commit in Chromium OS by Ramya Vijaykumar: commit a9a64f9e4d52c39fcd3c5f7d7b88065baed189b1 Author: Ramya Vijaykumar <ramya.vijaykumar(a)intel.com> flashrom: Add Skylake platform support Change-Id: I0f4565a3c39f5fe3aec4fc8863605cebed1ad4ee Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- M ich_descriptors.c M ich_descriptors.h M ichspi.c 3 files changed, 227 insertions(+), 87 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/62/18962/5 -- To view, visit https://review.coreboot.org/18962 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newpatchset Gerrit-Change-Id: I0f4565a3c39f5fe3aec4fc8863605cebed1ad4ee Gerrit-PatchSet: 5 Gerrit-Project: flashrom Gerrit-Branch: staging Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Stefan Tauner <stefan.tauner(a)gmx.at> Gerrit-Reviewer: Youness Alaoui <snifikino(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins)

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Change in flashrom[staging]: chipset_enable: Add support for Intel Skylake
by Nico Huber (Code Review) 26 Apr '17

26 Apr '17

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/18925 to look at the new patch set (#4). Change subject: chipset_enable: Add support for Intel Skylake ...................................................................... chipset_enable: Add support for Intel Skylake All publicly known Skylake / Sunrise Point PCH variants share the same register interface [1..4]. Although all SPI configuration is now done through the SPI PCI device 1f.5, we can't probe for it directly since its PCI vendor and device IDs are usually hidden. To work around the hidden IDs, we use another PCI accessor that doesn't rely on the OS seeing the PCI device. This handles SPI flashes only. While booting from LPC is still sup- ported, it seems nobody uses it any more. TEST=Compiled with B150 set to NT (instead of BAD) and checked for sane register readings. [1] 6th Generation Intel® Core(TM) Processor Families I/O Platform Datasheet - Volume 1 of 2 Revision 002EN Document Number 332995 [2] 6th Generation Intel® Processor I/O Datasheet for U/Y Platforms Volume 2 of 2 Revision 001EN Document Number 332996 [3] Intel® 100 Series and Intel® C230 Series Chipset Family Platform Controller Hub (PCH) Datasheet - Volume 1 of 2 Revision 004EN Document Number 332690 [4] Intel® 100 Series Chipset Family Platform Controller Hub (PCH) Datasheet - Volume 2 of 2 Revision 001EN Document Number 332691 Change-Id: I000819aff25fbe9764f33df85f040093b82cd948 Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- M chipset_enable.c M programmer.h 2 files changed, 89 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/25/18925/4 -- To view, visit https://review.coreboot.org/18925 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newpatchset Gerrit-Change-Id: I000819aff25fbe9764f33df85f040093b82cd948 Gerrit-PatchSet: 4 Gerrit-Project: flashrom Gerrit-Branch: staging Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Stefan Tauner <stefan.tauner(a)gmx.at> Gerrit-Reviewer: Youness Alaoui <snifikino(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins)

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Change in flashrom[staging]: ichspi: Add support for Intel Skylake
by Nico Huber (Code Review) 26 Apr '17

26 Apr '17

Nico Huber has posted comments on this change. ( https://review.coreboot.org/18962 ) Change subject: ichspi: Add support for Intel Skylake ...................................................................... Patch Set 4: (1 comment) https://review.coreboot.org/#/c/18962/4/ich_descriptors.c File ich_descriptors.c: Line 920: for (i = 0; i <= nr; i++) > Here, nr could be == 5 (above check is for nr > 5, not nr >= 5), and the lo Must have happened while juggling with commits. I fixed it again later in the series. -- To view, visit https://review.coreboot.org/18962 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I0f4565a3c39f5fe3aec4fc8863605cebed1ad4ee Gerrit-PatchSet: 4 Gerrit-Project: flashrom Gerrit-Branch: staging Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Stefan Tauner <stefan.tauner(a)gmx.at> Gerrit-Reviewer: Youness Alaoui <snifikino(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) Gerrit-HasComments: Yes

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Change in flashrom[staging]: chipset_enable: Add support for Intel Skylake
by Nico Huber (Code Review) 26 Apr '17

26 Apr '17

Nico Huber has posted comments on this change. ( https://review.coreboot.org/18925 ) Change subject: chipset_enable: Add support for Intel Skylake ...................................................................... Patch Set 3: (2 comments) https://review.coreboot.org/#/c/18925/2/chipset_enable.c File chipset_enable.c: Line 852: > Here, I would do : > Here, I would do : > pci_get_dev(pci_acc, dev->domain, dev->bus, dev->dev, 5); Hmmm, 1f.5 (or rather D31F5) is what one would read in a datasheet and I don't want to make it less recognizable. > Might even make that '5' into a #define to avoid having the magic > number here. > #define PCH_100_SPI_INTERFACE_PCI_FUNCTION I would agree if that number would be used somewhere else to. But as long as that's not the case, I'd choose readability. Line 858: > Any reason this doesn't call enable_flash_ich_fwh ? I'm having a hard time Firmware Hub (FWH) is basically a parallel flash chip on the LPC bus. While booting from LPC is still supported, IIRC, the system needs a SPI chip anyway (Firmware Descriptor, ME etc) and I haven't seen any Intel system with an LPC flash in years. So it doesn't make sense to put any effort there (couldn't test it anyway), but I should probably mention SPI-only in the commit message. -- To view, visit https://review.coreboot.org/18925 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I000819aff25fbe9764f33df85f040093b82cd948 Gerrit-PatchSet: 3 Gerrit-Project: flashrom Gerrit-Branch: staging Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Stefan Tauner <stefan.tauner(a)gmx.at> Gerrit-Reviewer: Youness Alaoui <snifikino(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) Gerrit-HasComments: Yes

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Change in flashrom[staging]: ichspi: Add support for Intel Skylake
by Youness Alaoui (Code Review) 26 Apr '17

26 Apr '17

Youness Alaoui has posted comments on this change. ( https://review.coreboot.org/18962 ) Change subject: ichspi: Add support for Intel Skylake ...................................................................... Patch Set 4: (1 comment) ichspi.c has too much code and too many unknown concepts for me to review at this time. Maybe I'll do that later when I get more familiar with it all... https://review.coreboot.org/#/c/18962/4/ich_descriptors.c File ich_descriptors.c: Line 920: for (i = 0; i <= nr; i++) Here, nr could be == 5 (above check is for nr > 5, not nr >= 5), and the loop now does i<=nr, so 'i' might be == 5 in the loop, but desc->region.FLREGs has a size of 5, so you'll get an out of bounds write. -- To view, visit https://review.coreboot.org/18962 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I0f4565a3c39f5fe3aec4fc8863605cebed1ad4ee Gerrit-PatchSet: 4 Gerrit-Project: flashrom Gerrit-Branch: staging Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Stefan Tauner <stefan.tauner(a)gmx.at> Gerrit-Reviewer: Youness Alaoui <snifikino(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) Gerrit-HasComments: Yes

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Change in flashrom[staging]: ichspi: Drop `dev` parameter from init functions
by Youness Alaoui (Code Review) 26 Apr '17

26 Apr '17

Youness Alaoui has posted comments on this change. ( https://review.coreboot.org/19460 ) Change subject: ichspi: Drop `dev` parameter from init functions ...................................................................... Patch Set 1: Code-Review+1 It looks sane, I think the dev is only used to get the spibar anyways and everything else is done through the SPIBAR MMIO. -- To view, visit https://review.coreboot.org/19460 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I0d4e7cc731364e86eff214b9022b842a577f9ef4 Gerrit-PatchSet: 1 Gerrit-Project: flashrom Gerrit-Branch: staging Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Youness Alaoui <snifikino(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) Gerrit-HasComments: No

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