December 2017 - flashrom-gerrit

Change in flashrom[master]: chipset_enable: VX900 as tested
by Lubomir Rintel (Code Review) 28 Dec '17

28 Dec '17

Lubomir Rintel has uploaded this change for review. ( https://review.coreboot.org/23030 Change subject: chipset_enable: VX900 as tested ...................................................................... chipset_enable: VX900 as tested I can confirm a successful reading and writing of MX25L8005 (SPI) on a HP t5550 Thin Client (AMI BIOS 786R9 v1.04). Change-Id: I190253b0c1920747b710ed7155e78191cce139eb Signed-off-by: Lubomir Rintel <lkundrak(a)v3.sk> --- M chipset_enable.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/30/23030/1 diff --git a/chipset_enable.c b/chipset_enable.c index 5716ebf..a46651f 100644 --- a/chipset_enable.c +++ b/chipset_enable.c @@ -1714,7 +1714,7 @@ {0x1106, 0x8324, OK, "VIA", "CX700", enable_flash_vt823x}, {0x1106, 0x8353, NT, "VIA", "VX800/VX820", enable_flash_vt_vx}, {0x1106, 0x8409, NT, "VIA", "VX855/VX875", enable_flash_vt_vx}, - {0x1106, 0x8410, NT, "VIA", "VX900", enable_flash_vt_vx}, + {0x1106, 0x8410, OK, "VIA", "VX900", enable_flash_vt_vx}, {0x1166, 0x0200, OK, "Broadcom", "OSB4", enable_flash_osb4}, {0x1166, 0x0205, OK, "Broadcom", "HT-1000", enable_flash_ht1000}, {0x17f3, 0x6030, OK, "RDC", "R8610/R3210", enable_flash_rdc_r8610}, -- To view, visit https://review.coreboot.org/23030 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I190253b0c1920747b710ed7155e78191cce139eb Gerrit-Change-Number: 23030 Gerrit-PatchSet: 1 Gerrit-Owner: Lubomir Rintel <lkundrak(a)v3.sk>

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Change in flashrom[master]: vt_vx: check whether the chipset's MMIO range is configured
by Lubomir Rintel (Code Review) 28 Dec '17

28 Dec '17

Lubomir Rintel has uploaded this change for review. ( https://review.coreboot.org/23029 Change subject: vt_vx: check whether the chipset's MMIO range is configured ...................................................................... vt_vx: check whether the chipset's MMIO range is configured Avoid attempting to read the SPI bases from the location 0x00000000, all zeroes mean that the chipset's MMIO area is not enabled. Change-Id: I5d3a1ba695153e854e0979ae634f8ed97e6b6293 Signed-off-by: Lubomir Rintel <lkundrak(a)v3.sk> --- M chipset_enable.c 1 file changed, 8 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/29/23029/1 diff --git a/chipset_enable.c b/chipset_enable.c index a499ba0..5716ebf 100644 --- a/chipset_enable.c +++ b/chipset_enable.c @@ -1013,10 +1013,18 @@ switch(dev->device_id) { case 0x8353: /* VX800/VX820 */ spi0_mm_base = pci_read_long(dev, 0xbc) << 8; + if (spi0_mm_base == 0x0) { + msg_pdbg ("MMIO not enabled!\n"); + return ERROR_FATAL; + } break; case 0x8409: /* VX855/VX875 */ case 0x8410: /* VX900 */ mmio_base = pci_read_long(dev, 0xbc) << 8; + if (mmio_base == 0x0) { + msg_pdbg ("MMIO not enabled!\n"); + return ERROR_FATAL; + } mmio_base_physmapped = physmap("VIA VX MMIO register", mmio_base, SPI_CNTL_LEN); if (mmio_base_physmapped == ERROR_PTR) return ERROR_FATAL; -- To view, visit https://review.coreboot.org/23029 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I5d3a1ba695153e854e0979ae634f8ed97e6b6293 Gerrit-Change-Number: 23029 Gerrit-PatchSet: 1 Gerrit-Owner: Lubomir Rintel <lkundrak(a)v3.sk>

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Change in flashrom[1.0.x]: internal: Fix #if guards for big-endian mips
by build bot (Jenkins) (Code Review) 28 Dec '17

28 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23003 ) Change subject: internal: Fix #if guards for big-endian mips ...................................................................... Patch Set 3: Build Successful https://qa.coreboot.org/job/flashrom-customrules/976/ : SUCCESS -- To view, visit https://review.coreboot.org/23003 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: 1.0.x Gerrit-MessageType: comment Gerrit-Change-Id: Id0508c5241a7bd61b8d92d631cdf42ef7829a8a9 Gerrit-Change-Number: 23003 Gerrit-PatchSet: 3 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 28 Dec 2017 10:59:02 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in flashrom[1.0.x]: internal: Fix #if guards for big-endian mips
by Nico Huber (Code Review) 28 Dec '17

28 Dec '17

Nico Huber has submitted this change and it was merged. ( https://review.coreboot.org/23003 ) Change subject: internal: Fix #if guards for big-endian mips ...................................................................... internal: Fix #if guards for big-endian mips Newer GCC still warns on big-endian mips, cf. 60210de (internal: Fix warnings about unused constants). Change-Id: Id0508c5241a7bd61b8d92d631cdf42ef7829a8a9 Signed-off-by: Nico Huber <nico.h(a)gmx.de> Reviewed-on: https://review.coreboot.org/23003 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> --- M internal.c 1 file changed, 2 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Philipp Deppenwiese: Looks good to me, approved diff --git a/internal.c b/internal.c index 276e14b..cb02753 100644 --- a/internal.c +++ b/internal.c @@ -131,7 +131,7 @@ int is_laptop = 0; int laptop_ok = 0; -#if IS_X86 || IS_MIPS +#if (IS_X86 || IS_MIPS) && defined(__FLASHROM_LITTLE_ENDIAN__) static void internal_chip_writeb(const struct flashctx *flash, uint8_t val, chipaddr addr); static void internal_chip_writew(const struct flashctx *flash, uint16_t val, @@ -360,7 +360,7 @@ } #endif -#if IS_X86 || IS_MIPS +#if (IS_X86 || IS_MIPS) && defined(__FLASHROM_LITTLE_ENDIAN__) static void internal_chip_writeb(const struct flashctx *flash, uint8_t val, chipaddr addr) { -- To view, visit https://review.coreboot.org/23003 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: 1.0.x Gerrit-MessageType: merged Gerrit-Change-Id: Id0508c5241a7bd61b8d92d631cdf42ef7829a8a9 Gerrit-Change-Number: 23003 Gerrit-PatchSet: 3 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in flashrom[master]: flashchips: Revise all 4BA chips
by build bot (Jenkins) (Code Review) 28 Dec '17

28 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22423 ) Change subject: flashchips: Revise all 4BA chips ...................................................................... Patch Set 6: Verified+1 Build Successful https://qa.coreboot.org/job/flashrom-customrules/975/ : SUCCESS https://qa.coreboot.org/job/flashrom_gerrit/836/ : SUCCESS -- To view, visit https://review.coreboot.org/22423 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I0598496ee7058e3b170684d366f58e4014e0e871 Gerrit-Change-Number: 22423 Gerrit-PatchSet: 6 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 28 Dec 2017 10:52:48 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in flashrom[master]: spi25: Revise decision when to enter/exit 4BA mode
by build bot (Jenkins) (Code Review) 28 Dec '17

28 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22422 ) Change subject: spi25: Revise decision when to enter/exit 4BA mode ...................................................................... Patch Set 6: Verified+1 Build Successful https://qa.coreboot.org/job/flashrom-customrules/974/ : SUCCESS https://qa.coreboot.org/job/flashrom_gerrit/835/ : SUCCESS -- To view, visit https://review.coreboot.org/22422 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I877fe817f801fc54bd0ee2ce4e3ead324cbb3673 Gerrit-Change-Number: 22422 Gerrit-PatchSet: 6 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 28 Dec 2017 10:52:46 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in flashrom[master]: spi_master: Introduce SPI_MASTER_4BA feature flag
by build bot (Jenkins) (Code Review) 28 Dec '17

28 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22421 ) Change subject: spi_master: Introduce SPI_MASTER_4BA feature flag ...................................................................... Patch Set 7: Verified+1 Build Successful https://qa.coreboot.org/job/flashrom-customrules/973/ : SUCCESS https://qa.coreboot.org/job/flashrom_gerrit/834/ : SUCCESS -- To view, visit https://review.coreboot.org/22421 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ife66e3fc49b9716f9c99cad957095b528135ec2c Gerrit-Change-Number: 22421 Gerrit-PatchSet: 7 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 28 Dec 2017 10:52:42 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in flashrom[master]: spi_master: Introduce SPI_MASTER_4BA feature flag
by Nico Huber (Code Review) 28 Dec '17

28 Dec '17

Hello Paul Menzel, David Hendricks, Stefan Reinauer, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/22421 to look at the new patch set (#7). Change subject: spi_master: Introduce SPI_MASTER_4BA feature flag ...................................................................... spi_master: Introduce SPI_MASTER_4BA feature flag Add a feature flag SPI_MASTER_4BA to `struct spi_master` that advertises programmer-side support for 4-byte addresses in generic commands (and read/write commands if the master uses the default implementations). Set it for all masters that handle commands address-agnostic. Don't prefer native 4BA instructions if the master doesn't support them. Change-Id: Ife66e3fc49b9716f9c99cad957095b528135ec2c Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M bitbang_spi.c M buspirate_spi.c M ch341a_spi.c M dummyflasher.c M ft2232_spi.c M linux_spi.c M programmer.h M serprog.c M spi25.c 9 files changed, 30 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/21/22421/7 -- To view, visit https://review.coreboot.org/22421 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: Ife66e3fc49b9716f9c99cad957095b528135ec2c Gerrit-Change-Number: 22421 Gerrit-PatchSet: 7 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in flashrom[master]: spi: Move ICH BBAR quirk out of the way
by build bot (Jenkins) (Code Review) 28 Dec '17

28 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22396 ) Change subject: spi: Move ICH BBAR quirk out of the way ...................................................................... Patch Set 6: Build Successful https://qa.coreboot.org/job/flashrom-customrules/972/ : SUCCESS -- To view, visit https://review.coreboot.org/22396 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Icbac513c5339e8aff624870252133284ef85ab73 Gerrit-Change-Number: 22396 Gerrit-PatchSet: 6 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 28 Dec 2017 10:49:17 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in flashrom[master]: spi: Move ICH BBAR quirk out of the way
by Nico Huber (Code Review) 28 Dec '17

28 Dec '17

Nico Huber has submitted this change and it was merged. ( https://review.coreboot.org/22396 ) Change subject: spi: Move ICH BBAR quirk out of the way ...................................................................... spi: Move ICH BBAR quirk out of the way Get rid of the layering violations around ICH's BBAR. Move all the weird address handling into (surprise, surprise) `ichspi.c`. Might fix writes for the `BBAR != 0` case by accident. Background: Some ICHs have a BBAR (BIOS Base Address Configuration Register) that, if set, limits the valid address range to [BBAR, 2^24). Current code lifted addresses for REMS, RES and READ operations by BBAR, now we do it for all addresses in ichspi. Special care has to be taken if the BBAR is not aligned by the flash chip's size. In this case, the lower part of the chip (from BBAR aligned down, up to BBAR) is inacces- sible (this seems to be the original intend behind BBAR) and has to be left out in the address offset calculation. Change-Id: Icbac513c5339e8aff624870252133284ef85ab73 Signed-off-by: Nico Huber <nico.h(a)gmx.de> Reviewed-on: https://review.coreboot.org/22396 Reviewed-by: David Hendricks <david.hendricks(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M flash.h M ichspi.c M programmer.h M spi.c M spi25.c 5 files changed, 29 insertions(+), 85 deletions(-) Approvals: David Hendricks: Looks good to me, approved build bot (Jenkins): Verified diff --git a/flash.h b/flash.h index f310e23..a14c302 100644 --- a/flash.h +++ b/flash.h @@ -375,7 +375,6 @@ #define NULL_SPI_CMD { 0, 0, NULL, NULL, } int spi_send_command(struct flashctx *flash, unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); int spi_send_multicommand(struct flashctx *flash, struct spi_command *cmds); -uint32_t spi_get_valid_read_addr(struct flashctx *flash); enum chipbustype get_buses_supported(void); #endif /* !__FLASH_H__ */ diff --git a/ichspi.c b/ichspi.c index c7bda92..5fe25f6 100644 --- a/ichspi.c +++ b/ichspi.c @@ -229,7 +229,7 @@ static int ichspi_lock = 0; static enum ich_chipset ich_generation = CHIPSET_ICH_UNKNOWN; -uint32_t ichspi_bbar = 0; +static uint32_t ichspi_bbar; static void *ich_spibar = NULL; @@ -1150,19 +1150,6 @@ return SPI_INVALID_LENGTH; } - /* if opcode-type requires an address */ - if (opcode->spi_type == SPI_OPCODE_TYPE_READ_WITH_ADDRESS || - opcode->spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS) { - addr = (writearr[1] << 16) | - (writearr[2] << 8) | (writearr[3] << 0); - if (addr < ichspi_bbar) { - msg_perr("%s: Address 0x%06x below allowed " - "range 0x%06x-0xffffff\n", __func__, - addr, ichspi_bbar); - return SPI_INVALID_ADDRESS; - } - } - /* Translate read/write array/count. * The maximum data length is identical for the maximum read length and * for the maximum write length excluding opcode and address. Opcode and @@ -1181,6 +1168,30 @@ count = readcnt; } + /* if opcode-type requires an address */ + if (cmd == JEDEC_REMS || cmd == JEDEC_RES) { + addr = ichspi_bbar; + } else if (opcode->spi_type == SPI_OPCODE_TYPE_READ_WITH_ADDRESS || + opcode->spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS) { + /* BBAR may cut part of the chip off at the lower end. */ + const uint32_t valid_base = ichspi_bbar & ((flash->chip->total_size * 1024) - 1); + const uint32_t addr_offset = ichspi_bbar - valid_base; + /* Highest address we can program is (2^24 - 1). */ + const uint32_t valid_end = (1 << 24) - addr_offset; + + addr = writearr[1] << 16 | writearr[2] << 8 | writearr[3]; + const uint32_t addr_end = addr + count; + + if (addr < valid_base || + addr_end < addr || /* integer overflow check */ + addr_end > valid_end) { + msg_perr("%s: Addressed region 0x%06x-0x%06x not in allowed range 0x%06x-0x%06x\n", + __func__, addr, addr_end - 1, valid_base, valid_end - 1); + return SPI_INVALID_ADDRESS; + } + addr += addr_offset; + } + result = run_opcode(flash, *opcode, addr, count, data); if (result) { msg_pdbg("Running OPCODE 0x%02x failed ", opcode->opcode); diff --git a/programmer.h b/programmer.h index a98b713..b390a53 100644 --- a/programmer.h +++ b/programmer.h @@ -661,7 +661,6 @@ /* ichspi.c */ #if CONFIG_INTERNAL == 1 -extern uint32_t ichspi_bbar; int ich_init_spi(void *spibar, enum ich_chipset ich_generation); int via_init_spi(uint32_t mmio_base); diff --git a/spi.c b/spi.c index 0a4a618..56f1fdf 100644 --- a/spi.c +++ b/spi.c @@ -103,31 +103,7 @@ int spi_chip_read(struct flashctx *flash, uint8_t *buf, unsigned int start, unsigned int len) { - unsigned int addrbase = 0; - - /* Check if the chip fits between lowest valid and highest possible - * address. Highest possible address with the current SPI implementation - * means 0xffffff, the highest unsigned 24bit number. - */ - addrbase = spi_get_valid_read_addr(flash); - /* Show flash chip size warning if flash chip doesn't support - 4-Bytes Addressing mode and last address excedes 24 bits */ - if (!(flash->chip->feature_bits & FEATURE_4BA_SUPPORT) && - addrbase + flash->chip->total_size * 1024 > (1 << 24)) { - msg_perr("Flash chip size exceeds the allowed access window. "); - msg_perr("Read will probably fail.\n"); - /* Try to get the best alignment subject to constraints. */ - addrbase = (1 << 24) - flash->chip->total_size * 1024; - } - /* Check if alignment is native (at least the largest power of two which - * is a factor of the mapped size of the chip). - */ - if (ffs(flash->chip->total_size * 1024) > (ffs(addrbase) ? : 33)) { - msg_perr("Flash chip is not aligned natively in the allowed " - "access window.\n"); - msg_perr("Read will probably return garbage.\n"); - } - return flash->mst->spi.read(flash, buf, addrbase + start, len); + return flash->mst->spi.read(flash, buf, start, len); } /* @@ -142,27 +118,6 @@ return flash->mst->spi.write_256(flash, buf, start, len); } -/* - * Get the lowest allowed address for read accesses. This often happens to - * be the lowest allowed address for all commands which take an address. - * This is a master limitation. - */ -uint32_t spi_get_valid_read_addr(struct flashctx *flash) -{ - switch (flash->mst->spi.type) { -#if CONFIG_INTERNAL == 1 -#if defined(__i386__) || defined(__x86_64__) - case SPI_CONTROLLER_ICH7: - case SPI_CONTROLLER_ICH9: - /* Return BBAR for ICH chipsets. */ - return ichspi_bbar; -#endif -#endif - default: - return 0; - } -} - int spi_aai_write(struct flashctx *flash, const uint8_t *buf, unsigned int start, unsigned int len) { return flash->mst->spi.write_aai(flash, buf, start, len); diff --git a/spi25.c b/spi25.c index c49f251..dcc7641 100644 --- a/spi25.c +++ b/spi25.c @@ -49,21 +49,10 @@ static int spi_rems(struct flashctx *flash, unsigned char *readarr) { - unsigned char cmd[JEDEC_REMS_OUTSIZE] = { JEDEC_REMS, 0, 0, 0 }; - uint32_t readaddr; + static const unsigned char cmd[JEDEC_REMS_OUTSIZE] = { JEDEC_REMS, }; int ret; - ret = spi_send_command(flash, sizeof(cmd), JEDEC_REMS_INSIZE, cmd, - readarr); - if (ret == SPI_INVALID_ADDRESS) { - /* Find the lowest even address allowed for reads. */ - readaddr = (spi_get_valid_read_addr(flash) + 1) & ~1; - cmd[1] = (readaddr >> 16) & 0xff, - cmd[2] = (readaddr >> 8) & 0xff, - cmd[3] = (readaddr >> 0) & 0xff, - ret = spi_send_command(flash, sizeof(cmd), JEDEC_REMS_INSIZE, - cmd, readarr); - } + ret = spi_send_command(flash, sizeof(cmd), JEDEC_REMS_INSIZE, cmd, readarr); if (ret) return ret; msg_cspew("REMS returned 0x%02x 0x%02x. ", readarr[0], readarr[1]); @@ -72,20 +61,11 @@ static int spi_res(struct flashctx *flash, unsigned char *readarr, int bytes) { - unsigned char cmd[JEDEC_RES_OUTSIZE] = { JEDEC_RES, 0, 0, 0 }; - uint32_t readaddr; + static const unsigned char cmd[JEDEC_RES_OUTSIZE] = { JEDEC_RES, }; int ret; int i; ret = spi_send_command(flash, sizeof(cmd), bytes, cmd, readarr); - if (ret == SPI_INVALID_ADDRESS) { - /* Find the lowest even address allowed for reads. */ - readaddr = (spi_get_valid_read_addr(flash) + 1) & ~1; - cmd[1] = (readaddr >> 16) & 0xff, - cmd[2] = (readaddr >> 8) & 0xff, - cmd[3] = (readaddr >> 0) & 0xff, - ret = spi_send_command(flash, sizeof(cmd), bytes, cmd, readarr); - } if (ret) return ret; msg_cspew("RES returned"); -- To view, visit https://review.coreboot.org/22396 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-MessageType: merged Gerrit-Change-Id: Icbac513c5339e8aff624870252133284ef85ab73 Gerrit-Change-Number: 22396 Gerrit-PatchSet: 6 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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flashrom-gerrit December 2017