October 2017 - flashrom-gerrit

Change in flashrom[stable]: nicintel_eeprom: Support for I210 emulated EEprom
by build bot (Jenkins) (Code Review) 10 Oct '17

10 Oct '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21938 ) Change subject: nicintel_eeprom: Support for I210 emulated EEprom ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/flashrom-customrules/752/ : SUCCESS https://qa.coreboot.org/job/flashrom_gerrit/680/ : SUCCESS -- To view, visit https://review.coreboot.org/21938 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: stable Gerrit-MessageType: comment Gerrit-Change-Id: I96f294eec42fd7609b27b76853e61a9bf18f7079 Gerrit-Change-Number: 21938 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 10 Oct 2017 16:58:45 +0000 Gerrit-HasComments: No

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Change in flashrom[stable]: nicintel_spi: Define BIT() macro
by build bot (Jenkins) (Code Review) 10 Oct '17

10 Oct '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21940 ) Change subject: nicintel_spi: Define BIT() macro ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/flashrom-customrules/753/ : SUCCESS https://qa.coreboot.org/job/flashrom_gerrit/681/ : SUCCESS -- To view, visit https://review.coreboot.org/21940 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: stable Gerrit-MessageType: comment Gerrit-Change-Id: I07cd1180aa290303705730d381e32d4c09df1ae5 Gerrit-Change-Number: 21940 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 10 Oct 2017 16:58:39 +0000 Gerrit-HasComments: No

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Change in flashrom[stable]: sb600spi: Add support for Merlin Falcon Chipset
by build bot (Jenkins) (Code Review) 10 Oct '17

10 Oct '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21937 ) Change subject: sb600spi: Add support for Merlin Falcon Chipset ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/flashrom-customrules/751/ : SUCCESS https://qa.coreboot.org/job/flashrom_gerrit/679/ : SUCCESS -- To view, visit https://review.coreboot.org/21937 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: stable Gerrit-MessageType: comment Gerrit-Change-Id: I44e55fe9bdb5ac00ed118d1d3cdc2c80b5e997cf Gerrit-Change-Number: 21937 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 10 Oct 2017 16:58:28 +0000 Gerrit-HasComments: No

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Change in flashrom[stable]: Add modification date to manpage header instead of the section
by Nico Huber (Code Review) 10 Oct '17

10 Oct '17

Hello Stefan Tauner, build bot (Jenkins), I'd like you to do a code review. Please visit https://review.coreboot.org/21941 to review the following change. Change subject: Add modification date to manpage header instead of the section ...................................................................... Add modification date to manpage header instead of the section "System Manager's Manual" or similar is way less interesting. Change-Id: I45c5d6a2316c51a57a49fd010682dc3f0f915382 Signed-off-by: Stefan Tauner <stefan.tauner(a)gmx.at> Reviewed-on: https://review.coreboot.org/21822 Reviewed-by: Nico Huber <nico.h(a)gmx.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M Makefile 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/41/21941/1 diff --git a/Makefile b/Makefile index 6806e14..68b9e9c 100644 --- a/Makefile +++ b/Makefile @@ -1384,7 +1384,7 @@ $(PROGRAM).8: $(PROGRAM).8.tmpl @# Add the man page change date and version to the man page - @sed -e 's#.TH FLASHROM 8 ".*".*#.TH FLASHROM 8 "$(MAN_DATE)" "$(VERSION)"#' <$< >$@ + @sed -e 's#.TH FLASHROM 8 .*#.TH FLASHROM 8 "$(MAN_DATE)" "$(VERSION)" "$(MAN_DATE)"#' <$< >$@ install: $(PROGRAM)$(EXEC_SUFFIX) $(PROGRAM).8 mkdir -p $(DESTDIR)$(PREFIX)/sbin -- To view, visit https://review.coreboot.org/21941 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: stable Gerrit-MessageType: newchange Gerrit-Change-Id: I45c5d6a2316c51a57a49fd010682dc3f0f915382 Gerrit-Change-Number: 21941 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Stefan Tauner <stefan.tauner(a)gmx.at> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in flashrom[stable]: nicintel_spi: Define BIT() macro
by Nico Huber (Code Review) 10 Oct '17

10 Oct '17

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/21940 Change subject: nicintel_spi: Define BIT() macro ...................................................................... nicintel_spi: Define BIT() macro Replace bit shifts with BIT() macro. This improves the readability of the code. Original-Change-Id: I30315891f18d4d5bfbc247bb9012560479afab90 Original-Reviewed-on: https://review.coreboot.org/21432 Original-Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Original-Reviewed-by: David Hendricks <david.hendricks(a)gmail.com> Change-Id: I07cd1180aa290303705730d381e32d4c09df1ae5 Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda(a)gmail.com> --- M nicintel_spi.c 1 file changed, 12 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/40/21940/1 diff --git a/nicintel_spi.c b/nicintel_spi.c index bbe0afb..3c43e8b 100644 --- a/nicintel_spi.c +++ b/nicintel_spi.c @@ -77,6 +77,8 @@ // #define FL_BUSY 30 // #define FL_ER 31 +#define BIT(x) (1<<(x)) + uint8_t *nicintel_spibar; const struct dev_entry nics_intel_spi[] = { @@ -114,11 +116,11 @@ uint32_t tmp; tmp = pci_mmio_readl(nicintel_spibar + FLA); - tmp |= 1 << FL_REQ; + tmp |= BIT(FL_REQ); pci_mmio_writel(tmp, nicintel_spibar + FLA); /* Wait until we are allowed to use the SPI bus. */ - while (!(pci_mmio_readl(nicintel_spibar + FLA) & (1 << FL_GNT))) ; + while (!(pci_mmio_readl(nicintel_spibar + FLA) & BIT(FL_GNT))) ; } static void nicintel_release_spibus(void) @@ -126,7 +128,7 @@ uint32_t tmp; tmp = pci_mmio_readl(nicintel_spibar + FLA); - tmp &= ~(1 << FL_REQ); + tmp &= ~BIT(FL_REQ); pci_mmio_writel(tmp, nicintel_spibar + FLA); } @@ -135,7 +137,7 @@ uint32_t tmp; tmp = pci_mmio_readl(nicintel_spibar + FLA); - tmp &= ~(1 << FL_CS); + tmp &= ~BIT(FL_CS); tmp |= (val << FL_CS); pci_mmio_writel(tmp, nicintel_spibar + FLA); } @@ -145,7 +147,7 @@ uint32_t tmp; tmp = pci_mmio_readl(nicintel_spibar + FLA); - tmp &= ~(1 << FL_SCK); + tmp &= ~BIT(FL_SCK); tmp |= (val << FL_SCK); pci_mmio_writel(tmp, nicintel_spibar + FLA); } @@ -155,7 +157,7 @@ uint32_t tmp; tmp = pci_mmio_readl(nicintel_spibar + FLA); - tmp &= ~(1 << FL_SI); + tmp &= ~BIT(FL_SI); tmp |= (val << FL_SI); pci_mmio_writel(tmp, nicintel_spibar + FLA); } @@ -225,18 +227,18 @@ uint32_t tmp; tmp = pci_mmio_readl(nicintel_spibar + FLA); - if (tmp & (1 << FL_LOCKED)) { + if (tmp & BIT(FL_LOCKED)) { msg_perr("Flash is in Secure Mode. Abort.\n"); return 1; } - if (!(tmp & (1 << FL_ABORT))) + if (!(tmp & BIT(FL_ABORT))) return 0; - tmp |= (1 << FL_CLR_ERR); + tmp |= BIT(FL_CLR_ERR); pci_mmio_writel(tmp, nicintel_spibar + FLA); tmp = pci_mmio_readl(nicintel_spibar + FLA); - if (!(tmp & (1 << FL_ABORT))) { + if (!(tmp & BIT(FL_ABORT))) { msg_perr("Unable to clear Flash Access Error. Abort\n"); return 1; } -- To view, visit https://review.coreboot.org/21940 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: stable Gerrit-MessageType: newchange Gerrit-Change-Id: I07cd1180aa290303705730d381e32d4c09df1ae5 Gerrit-Change-Number: 21940 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de>

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Change in flashrom[stable]: nicintel_spi: Support for I210/I211 cards
by Nico Huber (Code Review) 10 Oct '17

10 Oct '17

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/21939 Change subject: nicintel_spi: Support for I210/I211 cards ...................................................................... nicintel_spi: Support for I210/I211 cards Implements I210 "raw" flash access as detailed in: http://www.intel.com/content/www/us/en/embedded/products/networking/i210-et… Unfortunately, most of the time the card is in Secure Mode, which means that the raw access is not available. But his should be pretty useful for bringing up boards. Original-Change-Id: I8598ab21297b85dcae1e650a168043aa4cc15c10 Original-Reviewed-on: https://review.coreboot.org/21430 Original-Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Original-Reviewed-by: David Hendricks <david.hendricks(a)gmail.com> Change-Id: Ie1e5127cd3efdfef3489ef85a5f48a58deb37f8a Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda(a)gmail.com> --- M nicintel_spi.c 1 file changed, 71 insertions(+), 23 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/39/21939/1 diff --git a/nicintel_spi.c b/nicintel_spi.c index 9195c79..bbe0afb 100644 --- a/nicintel_spi.c +++ b/nicintel_spi.c @@ -70,6 +70,9 @@ #define FL_SO 3 #define FL_REQ 4 #define FL_GNT 5 +#define FL_LOCKED 6 +#define FL_ABORT 7 +#define FL_CLR_ERR 8 /* Currently unused */ // #define FL_BUSY 30 // #define FL_ER 31 @@ -94,6 +97,14 @@ {PCI_VENDOR_ID_INTEL, 0x1529, NT, "Intel", "82599 10 Gigabit Dual Port Network Controller with FCoE"}, {PCI_VENDOR_ID_INTEL, 0x152a, NT, "Intel", "82599 10 Gigabit Dual Port Backplane Controller with FCoE"}, {PCI_VENDOR_ID_INTEL, 0x1557, NT, "Intel", "82599 10 Gigabit SFI Network Controller"}, + + {PCI_VENDOR_ID_INTEL, 0x1531, OK, "Intel", "I210 Gigabit Network Connection Unprogrammed"}, + {PCI_VENDOR_ID_INTEL, 0x1532, NT, "Intel", "I211 Gigabit Network Connection Unprogrammed"}, + {PCI_VENDOR_ID_INTEL, 0x1533, NT, "Intel", "I210 Gigabit Network Connection"}, + {PCI_VENDOR_ID_INTEL, 0x1536, NT, "Intel", "I210 Gigabit Network Connection SERDES Fiber"}, + {PCI_VENDOR_ID_INTEL, 0x1537, NT, "Intel", "I210 Gigabit Network Connection SERDES Backplane"}, + {PCI_VENDOR_ID_INTEL, 0x1538, NT, "Intel", "I210 Gigabit Network Connection SGMII"}, + {PCI_VENDOR_ID_INTEL, 0x1539, NT, "Intel", "I211 Gigabit Network Connection"}, {0}, }; @@ -182,31 +193,9 @@ return 0; } -int nicintel_spi_init(void) +static int nicintel_spi_82599_enable_flash(void) { - struct pci_dev *dev = NULL; uint32_t tmp; - - if (rget_io_perms()) - return 1; - - dev = pcidev_init(nics_intel_spi, PCI_BASE_ADDRESS_0); - if (!dev) - return 1; - - uint32_t io_base_addr = pcidev_readbar(dev, PCI_BASE_ADDRESS_0); - if (!io_base_addr) - return 1; - - if (dev->device_id < 0x10d8) { - nicintel_spibar = rphysmap("Intel Gigabit NIC w/ SPI flash", io_base_addr, - MEMMAP_SIZE); - } else { - nicintel_spibar = rphysmap("Intel 10 Gigabit NIC w/ SPI flash", io_base_addr + 0x10000, - MEMMAP_SIZE); - } - if (nicintel_spibar == ERROR_PTR) - return 1; /* Automatic restore of EECD on shutdown is not possible because EECD * does not only contain FLASH_WRITES_DISABLED|FLASH_WRITES_ENABLED, @@ -228,6 +217,65 @@ if (register_shutdown(nicintel_spi_shutdown, NULL)) return 1; + return 0; +} + +static int nicintel_spi_i210_enable_flash() +{ + uint32_t tmp; + + tmp = pci_mmio_readl(nicintel_spibar + FLA); + if (tmp & (1 << FL_LOCKED)) { + msg_perr("Flash is in Secure Mode. Abort.\n"); + return 1; + } + + if (!(tmp & (1 << FL_ABORT))) + return 0; + + tmp |= (1 << FL_CLR_ERR); + pci_mmio_writel(tmp, nicintel_spibar + FLA); + tmp = pci_mmio_readl(nicintel_spibar + FLA); + if (!(tmp & (1 << FL_ABORT))) { + msg_perr("Unable to clear Flash Access Error. Abort\n"); + return 1; + } + + return 0; +} + +int nicintel_spi_init(void) +{ + struct pci_dev *dev = NULL; + + if (rget_io_perms()) + return 1; + + dev = pcidev_init(nics_intel_spi, PCI_BASE_ADDRESS_0); + if (!dev) + return 1; + + uint32_t io_base_addr = pcidev_readbar(dev, PCI_BASE_ADDRESS_0); + if (!io_base_addr) + return 1; + + if ((dev->device_id & 0xfff0) == 0x1530) { + nicintel_spibar = rphysmap("Intel I210 Gigabit w/ SPI flash", io_base_addr + 0x12000, + MEMMAP_SIZE); + if (!nicintel_spibar || nicintel_spi_i210_enable_flash()) + return 1; + } else if (dev->device_id < 0x10d8) { + nicintel_spibar = rphysmap("Intel Gigabit NIC w/ SPI flash", io_base_addr, + MEMMAP_SIZE); + if (!nicintel_spibar || nicintel_spi_82599_enable_flash()) + return 1; + } else { + nicintel_spibar = rphysmap("Intel 10 Gigabit NIC w/ SPI flash", io_base_addr + 0x10000, + MEMMAP_SIZE); + if (!nicintel_spibar || nicintel_spi_82599_enable_flash()) + return 1; + } + if (register_spi_bitbang_master(&bitbang_spi_master_nicintel)) return 1; -- To view, visit https://review.coreboot.org/21939 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: stable Gerrit-MessageType: newchange Gerrit-Change-Id: Ie1e5127cd3efdfef3489ef85a5f48a58deb37f8a Gerrit-Change-Number: 21939 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de>

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Change in flashrom[stable]: nicintel_eeprom: Support for I210 emulated EEprom
by Nico Huber (Code Review) 10 Oct '17

10 Oct '17

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/21938 Change subject: nicintel_eeprom: Support for I210 emulated EEprom ...................................................................... nicintel_eeprom: Support for I210 emulated EEprom On the I210 family there is no MAC EEprom, instead there is a big flash (typically around 16Mb) with contents of the old MAC plus other stuff. There is an interface to program the whole flash, but once it is programmed it enters a "Secure Mode" that disables the interface. Luckily, the section with the MAC can still be updated via the EEprom interface. This patch adds support for this interface. root@qt5022-fglrx:~# ./flashrom -p nicintel_eeprom:pci=01:0.0 -w kk.raw -V flashrom v0.9.9-unknown on Linux 4.10.0-qtec-standard (x86_64) flashrom is free software, get the source code at https://flashrom.org flashrom was built with libpci 3.4.1, GCC 5.3.0, little endian Command line (5 args): ./flashrom -p nicintel_eeprom:pci=01:0.0 -w kk.raw -V Calibrating delay loop... OS timer resolution is 1 usecs, 1856M loops per second, 10 myus = 10 us, 100 myus = 102 us, 1000 myus = 1017 us, 10000 myus = 10044 us, 4 myus = 4 us, OK. Initializing nicintel_eeprom programmer Found "Intel I210 Gigabit Network Connection" (8086:1533, BDF 01:00.0). Requested BAR is of type MEM, 32bit, not prefetchable Requested BAR is of type MEM, 32bit, not prefetchable The following protocols are supported: Programmer-specific. Probing for Programmer Opaque flash chip, 0 kB: Found Programmer flash chip "Opaque flash chip" (4 kB, Programmer-specific) on nicintel_eeprom. Found Programmer flash chip "Opaque flash chip" (4 kB, Programmer-specific). Reading old flash chip contents... done. Erasing and writing flash chip... Trying erase function 0... 0x000000-0x000fff:W Erase/write done. Verifying flash... VERIFIED. Original-Change-Id: I553f33e5dcb4412d682fc93095b29bcfed11713c Original-Reviewed-on: https://review.coreboot.org/21431 Original-Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Original-Reviewed-by: David Hendricks <david.hendricks(a)gmail.com> Change-Id: I96f294eec42fd7609b27b76853e61a9bf18f7079 Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda(a)gmail.com> --- M nicintel_eeprom.c 1 file changed, 175 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/38/21938/1 diff --git a/nicintel_eeprom.c b/nicintel_eeprom.c index b5d4202..c787580 100644 --- a/nicintel_eeprom.c +++ b/nicintel_eeprom.c @@ -25,6 +25,12 @@ * 4.7: Access to shared resources (FIXME: we should probably use this semaphore interface) * 7.4: Register Descriptions */ +/* + * Datasheet: Intel Ethernet Controller I210: Datasheet + * 8.4.3: EEPROM-Mode Read Register + * 8.4.6: EEPROM-Mode Write Register + * Write process inspired on kernel e1000_i210.c + */ #include <stdlib.h> #include <unistd.h> @@ -34,10 +40,11 @@ #include "hwaccess.h" #define PCI_VENDOR_ID_INTEL 0x8086 -#define MEMMAP_SIZE (0x14 + 3) /* Only EEC and EERD are needed. */ +#define MEMMAP_SIZE 0x1c /* Only EEC, EERD and EEWR are needed. */ #define EEC 0x10 /* EEPROM/Flash Control Register */ #define EERD 0x14 /* EEPROM Read Register */ +#define EEWR 0x18 /* EEPROM Write Register */ /* EPROM/Flash Control Register bits */ #define EE_SCK 0 @@ -49,6 +56,8 @@ #define EE_PRES 8 #define EE_SIZE 11 #define EE_SIZE_MASK 0xf +#define EE_FLUPD 23 +#define EE_FLUDONE 26 /* EEPROM Read Register bits */ #define EERD_START 0 @@ -56,14 +65,25 @@ #define EERD_ADDR 2 #define EERD_DATA 16 +/* EEPROM Write Register bits */ +#define EEWR_CMDV 0 +#define EEWR_DONE 1 +#define EEWR_ADDR 2 +#define EEWR_DATA 16 + #define BIT(x) (1<<x) #define EE_PAGE_MASK 0x3f static uint8_t *nicintel_eebar; static struct pci_dev *nicintel_pci; +static bool done_i20_write = false; #define UNPROG_DEVICE 0x1509 +/* + * Warning: is_i210() below makes assumptions on these PCI ids. + * It may have to be updated when this list is extended. + */ const struct dev_entry nics_intel_ee[] = { {PCI_VENDOR_ID_INTEL, 0x150e, OK, "Intel", "82580 Quad Gigabit Ethernet Controller (Copper)"}, {PCI_VENDOR_ID_INTEL, 0x150f, NT , "Intel", "82580 Quad Gigabit Ethernet Controller (Fiber)"}, @@ -71,10 +91,35 @@ {PCI_VENDOR_ID_INTEL, 0x1511, NT , "Intel", "82580 Quad Gigabit Ethernet Controller (Ext. PHY)"}, {PCI_VENDOR_ID_INTEL, 0x1511, NT , "Intel", "82580 Dual Gigabit Ethernet Controller (Copper)"}, {PCI_VENDOR_ID_INTEL, UNPROG_DEVICE, OK, "Intel", "Unprogrammed 82580 Quad/Dual Gigabit Ethernet Controller"}, + {PCI_VENDOR_ID_INTEL, 0x1531, NT, "Intel", "I210 Gigabit Network Connection Unprogrammed"}, + {PCI_VENDOR_ID_INTEL, 0x1532, NT, "Intel", "I211 Gigabit Network Connection Unprogrammed"}, + {PCI_VENDOR_ID_INTEL, 0x1533, OK, "Intel", "I210 Gigabit Network Connection"}, + {PCI_VENDOR_ID_INTEL, 0x1536, NT, "Intel", "I210 Gigabit Network Connection SERDES Fiber"}, + {PCI_VENDOR_ID_INTEL, 0x1537, NT, "Intel", "I210 Gigabit Network Connection SERDES Backplane"}, + {PCI_VENDOR_ID_INTEL, 0x1538, NT, "Intel", "I210 Gigabit Network Connection SGMII"}, + {PCI_VENDOR_ID_INTEL, 0x1539, NT, "Intel", "I211 Gigabit Network Connection"}, {0}, }; -static int nicintel_ee_probe(struct flashctx *flash) +static inline bool is_i210(uint16_t device_id) +{ + return (device_id & 0xfff0) == 0x1530; +} + +static int nicintel_ee_probe_i210(struct flashctx *flash) +{ + /* Emulated eeprom has a fixed size of 4 KB */ + flash->chip->total_size = 4; + flash->chip->page_size = flash->chip->total_size * 1024; + flash->chip->tested = TEST_OK_PREW; + flash->chip->gran = write_gran_1byte_implicit_erase; + flash->chip->block_erasers->eraseblocks[0].size = flash->chip->page_size; + flash->chip->block_erasers->eraseblocks[0].count = 1; + + return 1; +} + +static int nicintel_ee_probe_82580(struct flashctx *flash) { if (nicintel_pci->device_id == UNPROG_DEVICE) flash->chip->total_size = 16; /* Fall back to minimum supported size. */ @@ -103,6 +148,15 @@ return 1; } +static int nicintel_ee_probe(struct flashctx *flash) +{ + if (is_i210(nicintel_pci->device_id)) + return nicintel_ee_probe_i210(flash); + + return nicintel_ee_probe_82580(flash); +} + +#define MAX_ATTEMPTS 10000000 static int nicintel_ee_read_word(unsigned int addr, uint16_t *data) { uint32_t tmp = BIT(EERD_START) | (addr << EERD_ADDR); @@ -110,7 +164,7 @@ /* Poll done flag. 10.000.000 cycles seem to be enough. */ uint32_t i; - for (i = 0; i < 10000000; i++) { + for (i = 0; i < MAX_ATTEMPTS; i++) { tmp = pci_mmio_readl(nicintel_eebar + EERD); if (tmp & BIT(EERD_DONE)) { *data = (tmp >> EERD_DATA) & 0xffff; @@ -146,6 +200,85 @@ addr++; len--; } + } + + return 0; +} + +static int nicintel_ee_write_word_i210(unsigned int addr, uint16_t data) +{ + uint32_t eewr; + + eewr = addr << EEWR_ADDR; + eewr |= data << EEWR_DATA; + eewr |= BIT(EEWR_CMDV); + pci_mmio_writel(eewr, nicintel_eebar + EEWR); + + programmer_delay(5); + int i; + for (i = 0; i < MAX_ATTEMPTS; i++) + if (pci_mmio_readl(nicintel_eebar + EEWR) & BIT(EEWR_DONE)) + return 0; + return -1; +} + +static int nicintel_ee_write_i210(struct flashctx *flash, const uint8_t *buf, + unsigned int addr, unsigned int len) +{ + done_i20_write = true; + + if (addr & 1) { + uint16_t data; + + if (nicintel_ee_read_word(addr / 2, &data)) { + msg_perr("Timeout reading heading byte\n"); + return -1; + } + + data &= 0xff; + data |= (buf ? (buf[0]) : 0xff) << 8; + + if (nicintel_ee_write_word_i210(addr / 2, data)) { + msg_perr("Timeout writing heading word\n"); + return -1; + } + + if (buf) + buf ++; + addr ++; + len --; + } + + while (len > 0) { + uint16_t data; + + if (len == 1) { + if (nicintel_ee_read_word(addr / 2, &data)) { + msg_perr("Timeout reading tail byte\n"); + return -1; + } + + data &= 0xff00; + data |= buf ? (buf[0]) : 0xff; + } else { + if (buf) + data = buf[0] | (buf[1] << 8); + else + data = 0xffff; + } + + if (nicintel_ee_write_word_i210(addr / 2, data)) { + msg_perr("Timeout writing Shadow RAM\n"); + return -1; + } + + if (buf) + buf += 2; + if (len > 2) + len -= 2; + else + len = 0; + addr += 2; } return 0; @@ -224,7 +357,7 @@ return 0; } -static int nicintel_ee_write(struct flashctx *flash, const uint8_t *buf, unsigned int addr, unsigned int len) +static int nicintel_ee_write_82580(struct flashctx *flash, const uint8_t *buf, unsigned int addr, unsigned int len) { if (nicintel_ee_req()) return -1; @@ -262,6 +395,13 @@ nicintel_ee_bitset(EEC, EE_REQ, 0); /* Give up direct access. */ return ret; } +static int nicintel_ee_write(struct flashctx *flash, const uint8_t *buf, unsigned int addr, unsigned int len) +{ + if (is_i210(nicintel_pci->device_id)) + return nicintel_ee_write_i210(flash, buf, addr, len); + + return nicintel_ee_write_82580(flash, buf, addr, len); +} static int nicintel_ee_erase(struct flashctx *flash, unsigned int addr, unsigned int len) { @@ -274,6 +414,26 @@ .write = nicintel_ee_write, .erase = nicintel_ee_erase, }; + +static int nicintel_ee_shutdown_i210(void *arg) +{ + if (!done_i20_write) + return 0; + + uint32_t flup = pci_mmio_readl(nicintel_eebar + EEC); + + flup |= BIT(EE_FLUPD); + pci_mmio_writel(flup, nicintel_eebar + EEC); + + int i; + for (i = 0; i < MAX_ATTEMPTS; i++) + if (pci_mmio_readl(nicintel_eebar + EEC) & BIT(EE_FLUDONE)) + return 0; + + msg_perr("Flash update failed\n"); + + return -1; +} static int nicintel_ee_shutdown(void *eecp) { @@ -306,9 +466,14 @@ if (!io_base_addr) return 1; - nicintel_eebar = rphysmap("Intel Gigabit NIC w/ SPI EEPROM", io_base_addr, MEMMAP_SIZE); + nicintel_eebar = rphysmap("Intel Gigabit NIC w/ SPI EEPROM", + io_base_addr + (is_i210(dev->device_id) ? 0x12000 : 0), MEMMAP_SIZE); + if (!nicintel_eebar) + return 1; + nicintel_pci = dev; - if (dev->device_id != UNPROG_DEVICE) { + if ((dev->device_id != UNPROG_DEVICE) && ! is_i210(dev->device_id)) + { uint32_t eec = pci_mmio_readl(nicintel_eebar + EEC); /* C.f. 3.3.1.5 for the detection mechanism (maybe? contradicting the EE_PRES definition), @@ -327,5 +492,9 @@ return 1; } + if (is_i210(dev->device_id)) + if (register_shutdown(nicintel_ee_shutdown_i210, NULL)) + return 1; + return register_opaque_master(&opaque_master_nicintel_ee); } -- To view, visit https://review.coreboot.org/21938 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: stable Gerrit-MessageType: newchange Gerrit-Change-Id: I96f294eec42fd7609b27b76853e61a9bf18f7079 Gerrit-Change-Number: 21938 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de>

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Change in flashrom[stable]: sb600spi: Add support for Merlin Falcon Chipset
by Nico Huber (Code Review) 10 Oct '17

10 Oct '17

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/21937 Change subject: sb600spi: Add support for Merlin Falcon Chipset ...................................................................... sb600spi: Add support for Merlin Falcon Chipset This patch has been tested on a board similar to AMD Bettong. 00:14.0 SMBus [0c05]: Advanced Micro Devices, Inc. [AMD] FCH SMBus Controller [1022:790b] (rev 4a) 00:14.3 ISA bridge [0601]: Advanced Micro Devices, Inc. [AMD] FCH LPC Bridge [1022:790e] (rev 11) root@qt5022-fglrx:~# ./flashrom -p internal -w kk.rom flashrom v0.9.9-unknown on Linux 4.10.0-qtec-standard (x86_64) flashrom is free software, get the source code at https://flashrom.org Calibrating delay loop... OK. coreboot table found at 0x9ffd6000. Found chipset "AMD FP4". Enabling flash write... OK. Found Micron/Numonyx/ST flash chip "N25Q128..1E" (16384 kB, SPI) mapped at physical address 0x00000000ff000000. Reading old flash chip contents... done. Erasing and writing flash chip... Erase/write done. Verifying flash... VERIFIED. Original-Change-Id: I66a240ebc8382cc7e5156686045aee1a9d03fe6d Original-Reviewed-on: https://review.coreboot.org/21429 Original-Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Original-Reviewed-by: David Hendricks <david.hendricks(a)gmail.com> Change-Id: I44e55fe9bdb5ac00ed118d1d3cdc2c80b5e997cf Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda(a)gmail.com> --- M chipset_enable.c M sb600spi.c 2 files changed, 24 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/37/21937/1 diff --git a/chipset_enable.c b/chipset_enable.c index a3b7f8d..3437792 100644 --- a/chipset_enable.c +++ b/chipset_enable.c @@ -1608,6 +1608,7 @@ {0x1022, 0x7440, OK, "AMD", "AMD-768", enable_flash_amd_768_8111}, {0x1022, 0x7468, OK, "AMD", "AMD-8111", enable_flash_amd_768_8111}, {0x1022, 0x780e, OK, "AMD", "FCH", enable_flash_sb600}, + {0x1022, 0x790e, OK, "AMD", "FP4", enable_flash_sb600}, {0x1039, 0x0406, NT, "SiS", "501/5101/5501", enable_flash_sis501}, {0x1039, 0x0496, NT, "SiS", "85C496+497", enable_flash_sis85c496}, {0x1039, 0x0530, OK, "SiS", "530", enable_flash_sis530}, diff --git a/sb600spi.c b/sb600spi.c index 6bd5679..68f8d8a 100644 --- a/sb600spi.c +++ b/sb600spi.c @@ -149,6 +149,23 @@ "Please report this to flashrom(a)flashrom.org and include this log and\n" "the output of lspci -nnvx, thanks!.\n", rev); } + } else if (dev->device_id == 0x790e) { + struct pci_dev *smbus_dev = pci_dev_find(0x1022, 0x790B); + if (smbus_dev == NULL) { + msg_pdbg("No SMBus device with ID 1022:790B found.\n"); + return; + } + uint8_t rev = pci_read_byte(smbus_dev, PCI_REVISION_ID); + if (rev == 0x4a) { + amd_gen = CHIPSET_YANGTZE; + msg_pdbg("Yangtze detected.\n"); + } else { + msg_pwarn("FCH device found but SMBus revision 0x%02x does not match known values.\n" + "Please report this to flashrom(a)flashrom.org and include this log and\n" + "the output of lspci -nnvx, thanks!.\n", rev); + } + + #endif } else msg_pwarn("%s: Unknown LPC device %" PRIx16 ":%" PRIx16 ".\n" @@ -646,12 +663,13 @@ /* Look for the SMBus device. */ smbus_dev = pci_dev_find(0x1002, 0x4385); - if (!smbus_dev) { + if (!smbus_dev) smbus_dev = pci_dev_find(0x1022, 0x780b); /* AMD FCH */ - if (!smbus_dev) { - msg_perr("ERROR: SMBus device not found. Not enabling SPI.\n"); - return ERROR_NONFATAL; - } + if (!smbus_dev) + smbus_dev = pci_dev_find(0x1022, 0x790b); /* AMD FP4 */ + if (!smbus_dev) { + msg_perr("ERROR: SMBus device not found. Not enabling SPI.\n"); + return ERROR_NONFATAL; } /* Note about the bit tests below: If a bit is zero, the GPIO is SPI. */ -- To view, visit https://review.coreboot.org/21937 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: stable Gerrit-MessageType: newchange Gerrit-Change-Id: I44e55fe9bdb5ac00ed118d1d3cdc2c80b5e997cf Gerrit-Change-Number: 21937 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de>

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Change in flashrom[staging]: nicintel_eeprom: Reduce usage of is_i210()
by Nico Huber (Code Review) 10 Oct '17

10 Oct '17

Nico Huber has posted comments on this change. ( https://review.coreboot.org/21935 ) Change subject: nicintel_eeprom: Reduce usage of is_i210() ...................................................................... Patch Set 2: PS2 is a less invasive version (that should work better regarding our wiki features). I revised it after I realized that we already do such fragile PCI id distinctions. I'm good with either version. -- To view, visit https://review.coreboot.org/21935 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: staging Gerrit-MessageType: comment Gerrit-Change-Id: I59164ccf54afbbd64a0598282d13e80ff7fd6fa4 Gerrit-Change-Number: 21935 Gerrit-PatchSet: 2 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 10 Oct 2017 16:48:25 +0000 Gerrit-HasComments: No

1 0

Change in flashrom[staging]: nicintel_eeprom: Reduce usage of is_i210()
by build bot (Jenkins) (Code Review) 10 Oct '17

10 Oct '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21935 ) Change subject: nicintel_eeprom: Reduce usage of is_i210() ...................................................................... Patch Set 2: Verified+1 Build Successful https://qa.coreboot.org/job/flashrom-customrules/750/ : SUCCESS https://qa.coreboot.org/job/flashrom_gerrit/678/ : SUCCESS -- To view, visit https://review.coreboot.org/21935 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: staging Gerrit-MessageType: comment Gerrit-Change-Id: I59164ccf54afbbd64a0598282d13e80ff7fd6fa4 Gerrit-Change-Number: 21935 Gerrit-PatchSet: 2 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 10 Oct 2017 16:45:23 +0000 Gerrit-HasComments: No

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flashrom-gerrit October 2017