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[commit] r1268 - trunk
by repository service 06 Mar '11

06 Mar '11

Author: mkarcher Date: Sun Mar 6 18:58:05 2011 New Revision: 1268 URL: http://flashrom.org/trac/flashrom/changeset/1268 Log: Add W39L040 Signed-off-by: Michael Karcher <flashrom(a)mkarcher.dialup.fu-berlin.de> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: trunk/chipdrivers.h trunk/flashchips.c trunk/w39.c Modified: trunk/chipdrivers.h ============================================================================== --- trunk/chipdrivers.h Sun Mar 6 18:37:30 2011 (r1267) +++ trunk/chipdrivers.h Sun Mar 6 18:58:05 2011 (r1268) @@ -110,6 +110,7 @@ int unlock_sst_fwhub(struct flashchip *flash); /* w39.c */ +int printlock_w39l040(struct flashchip * flash); int printlock_w39v040a(struct flashchip *flash); int printlock_w39v040b(struct flashchip *flash); int printlock_w39v040c(struct flashchip *flash); Modified: trunk/flashchips.c ============================================================================== --- trunk/flashchips.c Sun Mar 6 18:37:30 2011 (r1267) +++ trunk/flashchips.c Sun Mar 6 18:58:05 2011 (r1268) @@ -7820,6 +7820,36 @@ { .vendor = "Winbond", + .name = "W39L040", + .bustype = CHIP_BUSTYPE_PARALLEL, + .manufacture_id = WINBOND_ID, + .model_id = WINBOND_W39L040, + .total_size = 512, + .page_size = 64 * 1024, + .feature_bits = FEATURE_EITHER_RESET, + .tested = TEST_OK_PR, + .probe = probe_jedec, + .probe_timing = 10, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 128} }, + .block_erase = erase_block_jedec, + }, { + .eraseblocks = { {64 * 1024, 8} }, + .block_erase = erase_sector_jedec, + }, { + .eraseblocks = { {512 * 1024, 1} }, + .block_erase = erase_chip_block_jedec, + } + }, + .printlock = printlock_w39l040, + .write = write_jedec_1, + .read = read_memmapped, + }, + + { + .vendor = "Winbond", .name = "W39V040A", .bustype = CHIP_BUSTYPE_LPC, .manufacture_id = WINBOND_ID, Modified: trunk/w39.c ============================================================================== --- trunk/w39.c Sun Mar 6 18:37:30 2011 (r1267) +++ trunk/w39.c Sun Mar 6 18:58:05 2011 (r1268) @@ -161,6 +161,22 @@ return 0; } +int printlock_w39l040(struct flashchip * flash) +{ + uint8_t lock; + int ret; + + lock = w39_idmode_readb(flash, 0x00002); + msg_cdbg("Bottom boot block:\n"); + ret = printlock_w39_bootblock_64k16k(lock); + + lock = w39_idmode_readb(flash, 0x7fff2); + msg_cdbg("Top boot block:\n"); + ret |= printlock_w39_bootblock_64k16k(lock); + + return ret; +} + int printlock_w39v040a(struct flashchip *flash) { uint8_t lock;

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patch resend
by Brandon Dowdy 06 Mar '11

06 Mar '11

This is a resend of the same patch. »[PATCH]« Signed-off-by: Brandon Dowdy <brandonrd7 at gmail.com <http://www.flashrom.org/mailman/listinfo/flashrom>>

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[commit] r1267 - trunk
by repository service 06 Mar '11

06 Mar '11

Author: mkarcher Date: Sun Mar 6 18:37:30 2011 New Revision: 1267 URL: http://flashrom.org/trac/flashrom/changeset/1267 Log: Add coreboot IDs to make manual selection of HP xw9400 possible Signed-off-by: Michael Karcher <flashrom(a)mkarcher.dialup.fu-berlin.de> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: trunk/board_enable.c Modified: trunk/board_enable.c ============================================================================== --- trunk/board_enable.c Sun Mar 6 13:09:05 2011 (r1266) +++ trunk/board_enable.c Sun Mar 6 18:37:30 2011 (r1267) @@ -1965,7 +1965,7 @@ {0x8086, 0x2580, 0x103c, 0x2a08, 0x8086, 0x2640, 0x103c, 0x2a0a, NULL, NULL, NULL, "HP", "Puffer2-UL8E", 0, OK, intel_ich_gpio18_raise}, {0x8086, 0x2415, 0x103c, 0x1249, 0x10b7, 0x9200, 0x103c, 0x1246, NULL, NULL, NULL, "HP", "Vectra VL400", 0, OK, board_hp_vl400}, {0x8086, 0x1a30, 0x103c, 0x1a30, 0x8086, 0x2443, 0x103c, 0x2440, "^VL420$", NULL, NULL, "HP", "Vectra VL420 SFF", 0, OK, intel_ich_gpio22_raise}, - {0x10de, 0x0369, 0x103c, 0x12fe, 0x10de, 0x0364, 0x103c, 0x12fe, NULL, NULL, NULL, "HP", "xw9400", 0, OK, nvidia_mcp_gpio5_raise}, + {0x10de, 0x0369, 0x103c, 0x12fe, 0x10de, 0x0364, 0x103c, 0x12fe, NULL, "hp", "xw9400", "HP", "xw9400", 0, OK, nvidia_mcp_gpio5_raise}, {0x8086, 0x27A0, 0, 0, 0x8086, 0x27B9, 0, 0, NULL, "ibase", "mb899", "IBASE", "MB899", 0, OK, intel_ich_gpio26_raise}, {0x1166, 0x0205, 0x1014, 0x0347, 0x1002, 0x515E, 0x1014, 0x0325, NULL, NULL, NULL, "IBM", "x3455", 0, OK, board_ibm_x3455}, {0x1039, 0x5513, 0x8086, 0xd61f, 0x1039, 0x6330, 0x8086, 0xd61f, NULL, NULL, NULL, "Intel", "D201GLY", 0, OK, wbsio_check_for_spi},

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Re: [flashrom] [PATCH 1/1] Board-enable for GA-K8N51GMF
by Carl-Daniel Hailfinger 06 Mar '11

06 Mar '11

Auf 04.02.2011 10:55, Michael Karcher schrieb: > Gigabyte is not really helpful with their PCI IDs for us, the subsystem > IDs used just mean "gigabyte northbridge" and "gigabyte southbridge". > We should investigate whether autodetection of this board is causing > interference with other boards. > > real version 2: Extend list of PCI IDs for nvidia southbridges. > > flashrom -V: http://paste.flashrom.org/view.php?id=326 > lspic: http://paste.flashrom.org/view.php?id=328 > superiotool: http://paste.flashrom.org/view.php?id=329 > > Signed-off-by: Michael Karcher <flashrom(a)mkarcher.dialup.fu-berlin.de> > Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Regards, Carl-Daniel -- http://www.hailfinger.org/

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Re: [flashrom] [PATCH 1/1] Add HP e-Vectra P2706T
by Carl-Daniel Hailfinger 06 Mar '11

06 Mar '11

Auf 03.03.2011 23:42, Michael Karcher schrieb: > Reported by: Michal Janke <jankeso(a)gmail.com> > Signed-off-by: Michael Karcher <flashrom(a)mkarcher.dialup.fu-berlin.de> > Thanks for reverse engineering this board enable! Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Regards, Carl-Daniel -- http://www.hailfinger.org/

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[commit] r1266 - trunk
by repository service 06 Mar '11

06 Mar '11

Author: mkarcher Date: Sun Mar 6 13:09:05 2011 New Revision: 1266 URL: http://flashrom.org/trac/flashrom/changeset/1266 Log: Board-enable for GA-K8N51GMF Gigabyte is not really helpful with their PCI IDs for us, the subsystem IDs used just mean "gigabyte northbridge" and "gigabyte southbridge". We should investigate whether autodetection of this board is causing interference with other boards. real version 2: Extend list of PCI IDs for nvidia southbridges. flashrom -V: http://paste.flashrom.org/view.php?id=326 lspic: http://paste.flashrom.org/view.php?id=328 superiotool: http://paste.flashrom.org/view.php?id=329 Signed-off-by: Michael Karcher <flashrom(a)mkarcher.dialup.fu-berlin.de> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: trunk/board_enable.c trunk/print.c Modified: trunk/board_enable.c ============================================================================== --- trunk/board_enable.c Sun Mar 6 13:07:19 2011 (r1265) +++ trunk/board_enable.c Sun Mar 6 13:09:05 2011 (r1266) @@ -869,6 +869,7 @@ case 0x00E0: /* CK8 */ break; case 0x0260: /* MCP51 */ + case 0x0261: /* MCP51 */ case 0x0364: /* MCP55 */ /* find SMBus controller on *this* southbridge */ /* The infamous Tyan S2915-E has two south bridges; they are @@ -1029,7 +1030,8 @@ /* * Suited for: - * - GIGABYTE GA-K8N51GMF-9 + * - GIGABYTE GA-K8N51GMF: Socket 754 + Geforce 6100 + MCP51 + * - GIGABYTE GA-K8N51GMF-9: Socket 939 + Geforce 6100 + MCP51 */ static int nvidia_mcp_gpio3b_raise(void) { @@ -1954,6 +1956,7 @@ {0x1106, 0x0686, 0x1106, 0x0686, 0x1106, 0x3058, 0x1458, 0xa000, NULL, NULL, NULL, "GIGABYTE", "GA-7ZM", 512, OK, NULL}, {0x8086, 0x244b, 0x8086, 0x2442, 0x8086, 0x2445, 0x1458, 0xa002, NULL, NULL, NULL, "GIGABYTE", "GA-8IRML", 0, OK, intel_ich_gpio25_raise}, {0x8086, 0x24c3, 0x1458, 0x24c2, 0x8086, 0x24cd, 0x1458, 0x5004, NULL, NULL, NULL, "GIGABYTE", "GA-8PE667 Ultra 2", 0, OK, intel_ich_gpio32_raise}, + {0x10DE, 0x02F1, 0x1458, 0x5000, 0x10DE, 0x0261, 0x1458, 0x5001, NULL, NULL, NULL, "GIGABYTE", "GA-K8N51GMF", 0, OK, nvidia_mcp_gpio3b_raise}, {0x10DE, 0x026C, 0x1458, 0xA102, 0x10DE, 0x0260, 0x1458, 0x5001, NULL, NULL, NULL, "GIGABYTE", "GA-K8N51GMF-9", 0, OK, nvidia_mcp_gpio3b_raise}, {0x10DE, 0x0050, 0x1458, 0x0C11, 0x10DE, 0x005e, 0x1458, 0x5000, NULL, NULL, NULL, "GIGABYTE", "GA-K8N-SLI", 0, OK, nvidia_mcp_gpio21_raise}, {0x8086, 0x2415, 0x103c, 0x1250, 0x10b7, 0x9200, 0x103c, 0x1247, NULL, NULL, NULL, "HP", "e-Vectra P2706T", 0, OK, board_hp_p2706t}, Modified: trunk/print.c ============================================================================== --- trunk/print.c Sun Mar 6 13:07:19 2011 (r1265) +++ trunk/print.c Sun Mar 6 13:09:05 2011 (r1266) @@ -482,6 +482,7 @@ B("GIGABYTE", "GA-EP35-DS3L", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=2778", NULL), B("GIGABYTE", "GA-EX58-UD4P", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=2986", NULL), B("GIGABYTE", "GA-K8N-SLI", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=1928", NULL), + B("GIGABYTE", "GA-K8N51GMF", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=1950", NULL), B("GIGABYTE", "GA-K8N51GMF-9", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=1939", NULL), B("GIGABYTE", "GA-M57SLI-S4", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=2287", NULL), B("GIGABYTE", "GA-M61P-S3", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=2434", NULL),

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[commit] r1265 - trunk
by repository service 06 Mar '11

06 Mar '11

Author: mkarcher Date: Sun Mar 6 13:07:19 2011 New Revision: 1265 URL: http://flashrom.org/trac/flashrom/changeset/1265 Log: Add HP e-Vectra P2706T Reported by: Michal Janke <jankeso(a)gmail.com> flashrom -V: http://paste.flashrom.org/view.php?id=370 lspci: http://paste.flashrom.org/view.php?id=371 superiotool: http://paste.flashrom.org/view.php?id=372 and http://www.flashrom.org/pipermail/flashrom/2011-March/005878.html Signed-off-by: Michael Karcher <flashrom(a)mkarcher.dialup.fu-berlin.de> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: trunk/board_enable.c trunk/print.c Modified: trunk/board_enable.c ============================================================================== --- trunk/board_enable.c Sat Mar 5 17:31:57 2011 (r1264) +++ trunk/board_enable.c Sun Mar 6 13:07:19 2011 (r1265) @@ -543,7 +543,10 @@ return it8707f_write_enable(0x2e); } -static int pc87360_gpio_set(uint8_t gpio, int raise) +#define PC87360_ID 0xE1 +#define PC87364_ID 0xE4 + +static int pc8736x_gpio_set(uint8_t chipid, uint8_t gpio, int raise) { static const int bankbase[] = {0, 4, 8, 10, 12}; int gpio_bank = gpio / 8; @@ -552,13 +555,13 @@ uint8_t id, val; if (gpio_bank > 4) { - msg_perr("PC87360: Invalid GPIO %d\n", gpio); + msg_perr("PC8736x: Invalid GPIO %d\n", gpio); return -1; } id = sio_read(0x2E, 0x20); - if (id != 0xE1) { - msg_perr("PC87360: unexpected ID %02x\n", id); + if (id != chipid) { + msg_perr("PC8736x: unexpected ID %02x (expected %02x)\n", id, chipid); return -1; } @@ -1483,9 +1486,22 @@ int ret; ret = intel_ich_gpio_set(25, 1); /* Master write enable ? */ if (!ret) - ret = pc87360_gpio_set(0x09, 1); /* #WP ? */ + ret = pc8736x_gpio_set(PC87360_ID, 0x09, 1); /* #WP ? */ + if (!ret) + ret = pc8736x_gpio_set(PC87360_ID, 0x27, 1); /* #TBL */ + return ret; +} + +/* + * Suited for: + * - HP e-Vectra P2706T: 810E + ICH + PC87364 + */ +static int board_hp_p2706t(void) +{ + int ret; + ret = pc8736x_gpio_set(PC87364_ID, 0x25, 1); if (!ret) - ret = pc87360_gpio_set(0x27, 1); /* #TBL */ + ret = pc8736x_gpio_set(PC87364_ID, 0x26, 1); return ret; } @@ -1940,6 +1956,7 @@ {0x8086, 0x24c3, 0x1458, 0x24c2, 0x8086, 0x24cd, 0x1458, 0x5004, NULL, NULL, NULL, "GIGABYTE", "GA-8PE667 Ultra 2", 0, OK, intel_ich_gpio32_raise}, {0x10DE, 0x026C, 0x1458, 0xA102, 0x10DE, 0x0260, 0x1458, 0x5001, NULL, NULL, NULL, "GIGABYTE", "GA-K8N51GMF-9", 0, OK, nvidia_mcp_gpio3b_raise}, {0x10DE, 0x0050, 0x1458, 0x0C11, 0x10DE, 0x005e, 0x1458, 0x5000, NULL, NULL, NULL, "GIGABYTE", "GA-K8N-SLI", 0, OK, nvidia_mcp_gpio21_raise}, + {0x8086, 0x2415, 0x103c, 0x1250, 0x10b7, 0x9200, 0x103c, 0x1247, NULL, NULL, NULL, "HP", "e-Vectra P2706T", 0, OK, board_hp_p2706t}, {0x1166, 0x0223, 0x103c, 0x320d, 0x14e4, 0x1678, 0x103c, 0x703e, NULL, "hp", "dl145_g3", "HP", "ProLiant DL145 G3", 0, OK, board_hp_dl145_g3_enable}, {0x1166, 0x0223, 0x103c, 0x320d, 0x14e4, 0x1648, 0x103c, 0x310f, NULL, "hp", "dl165_g6", "HP", "ProLiant DL165 G6", 0, OK, board_hp_dl165_g6_enable}, {0x8086, 0x2580, 0x103c, 0x2a08, 0x8086, 0x2640, 0x103c, 0x2a0a, NULL, NULL, NULL, "HP", "Puffer2-UL8E", 0, OK, intel_ich_gpio18_raise}, Modified: trunk/print.c ============================================================================== --- trunk/print.c Sat Mar 5 17:31:57 2011 (r1264) +++ trunk/print.c Sun Mar 6 13:07:19 2011 (r1265) @@ -493,6 +493,7 @@ B("GIGABYTE", "GA-MA78GPM-DS2H", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=2859", NULL), B("GIGABYTE", "GA-MA790FX-DQ6", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=2690", NULL), B("GIGABYTE", "GA-MA790GP-DS4H", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=2887", NULL), + B("HP", "e-Vectra P2706T", 1, "http://h20000.www2.hp.com/bizsupport/TechSupport/Home.jsp?lang=en&cc=us&pro…", NULL), B("HP", "ProLiant DL145 G3", 1, "http://h20000.www2.hp.com/bizsupport/TechSupport/Document.jsp?objectID=c008…", NULL), B("HP", "ProLiant DL165 G6", 1, "http://h10010.www1.hp.com/wwpc/us/en/sm/WF05a/15351-15351-3328412-241644-33…", NULL), B("HP", "Puffer2-UL8E", 1, "http://h10025.www1.hp.com/ewfrf/wc/document?docname=c00300023", NULL),

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Re: [flashrom] [PATCH] kill central list of SPI programmers
by Carl-Daniel Hailfinger 06 Mar '11

06 Mar '11

Auf 18.07.2010 17:20, Michael Karcher schrieb: > This version really compiles. Forgot the forward declaration after > moving code initially. > > Signed-off-by: Michael Karcher <flashrom(a)mkarcher.dialup.fu-berlin.de> > I like most ideas in there, and have some minor nitpicks. Using a registration function would allow us to handle multiple SPI programmers on one board (e.g. one in the EC and one in the southbridge), but some infrastructure changes elsewhere would be needed. We need that to handle stuff like the Google Cr-48 netbook sanely. One of my post-0.9.4 goals is to register programmer drivers for every bus, not just SPI. The idea is to be able to handle multiple flash chips behind LPC as well, e.g. if they have different base addresses. And stuff like switching between Dual BIOS chips with a GPIO line could be implemented under that scheme as well. > diff --git a/buspirate_spi.c b/buspirate_spi.c > index 55e71c2..36eaa9a 100644 > --- a/buspirate_spi.c > +++ b/buspirate_spi.c > @@ -44,6 +44,8 @@ static int buspirate_serialport_setup(char *dev) > #define sp_flush_incoming(...) 0 > #endif > > +static const struct spi_programmer spi_programmer_buspirate; > + > static int buspirate_sendrecv(unsigned char *buf, unsigned int writecnt, unsigned int readcnt) > { > int i, ret = 0; > @@ -210,7 +212,7 @@ int buspirate_spi_init(void) > } > > buses_supported = CHIP_BUSTYPE_SPI; > - spi_controller = SPI_CONTROLLER_BUSPIRATE; > + spi_programmer = &spi_programmer_buspirate; > You assign the spi_programmer variable directly. While that is a straightforward replacement of the current code, it would be cool if you could use a registration function instead: register_spi_programmer(&spi_programmer_buspirate); Depending on whether modification of the programmer-specific info is desired, it may also be possible to have that registration function copy the struct so later calls can make changes even if the original parameter is const. > > return 0; > } > @@ -250,7 +252,7 @@ int buspirate_spi_shutdown(void) > return 0; > } > > -int buspirate_spi_send_command(unsigned int writecnt, unsigned int readcnt, > +static int buspirate_spi_send_command(unsigned int writecnt, unsigned int readcnt, > const unsigned char *writearr, unsigned char *readarr) > { > static unsigned char *buf = NULL; > @@ -304,12 +306,20 @@ int buspirate_spi_send_command(unsigned int writecnt, unsigned int readcnt, > return ret; > } > > -int buspirate_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len) > +static int buspirate_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len) > { > return spi_read_chunked(flash, buf, start, len, 12); > } > > -int buspirate_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int len) > +static int buspirate_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int len) > { > return spi_write_chunked(flash, buf, start, len, 12); > } > + > +static const struct spi_programmer spi_programmer_buspirate = { > + .type = SPI_CONTROLLER_BUSPIRATE, > + .command = buspirate_spi_send_command, > + .multicommand = default_spi_send_multicommand, > + .read = buspirate_spi_read, > + .write_256 = buspirate_spi_write_256, > +}; > diff --git a/dediprog.c b/dediprog.c > index 0b92983..c21c801 100644 > --- a/dediprog.c > +++ b/dediprog.c > @@ -25,6 +25,7 @@ > > #define DEFAULT_TIMEOUT 3000 > static usb_dev_handle *dediprog_handle; > +static const struct spi_programmer spi_programmer_dediprog; > > #if 0 > /* Might be useful for other pieces of code as well. */ > @@ -145,14 +146,14 @@ static int dediprog_set_spi_speed(uint16_t speed) > } > #endif > > -int dediprog_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len) > +static int dediprog_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len) > { > msg_pspew("%s, start=0x%x, len=0x%x\n", __func__, start, len); > /* Chosen read length is 16 bytes for now. */ > return spi_read_chunked(flash, buf, start, len, 16); > } > > -int dediprog_spi_send_command(unsigned int writecnt, unsigned int readcnt, > +static int dediprog_spi_send_command(unsigned int writecnt, unsigned int readcnt, > const unsigned char *writearr, unsigned char *readarr) > { > int ret; > @@ -318,7 +319,7 @@ int dediprog_init(void) > return 1; > > buses_supported = CHIP_BUSTYPE_SPI; > - spi_controller = SPI_CONTROLLER_DEDIPROG; > + spi_programmer = &spi_programmer_dediprog; > Registration function. Same for all subsequent occurences. > > /* RE leftover, leave in until the driver is complete. */ > #if 0 > @@ -394,3 +395,11 @@ int dediprog_shutdown(void) > } > return 0; > } > + > +static const struct spi_programmer spi_programmer_dediprog = { > + .type = SPI_CONTROLLER_DEDIPROG, > + .command = dediprog_spi_send_command, > + .multicommand = default_spi_send_multicommand, > + .read = dediprog_spi_read, > + .write_256 = spi_chip_write_1_new, > +}; > diff --git a/dummyflasher.c b/dummyflasher.c > index 241dcee..b1bbcf2 100644 > --- a/dummyflasher.c > +++ b/dummyflasher.c > @@ -25,6 +25,8 @@ > #include "flash.h" > #include "chipdrivers.h" > > +static const struct spi_programmer spi_programmer_dummy; > + > static void tolower_string(char *str) > { > for (; *str != '\0'; str++) > @@ -59,7 +61,7 @@ int dummy_init(void) > } > if (strstr(bustext, "spi")) { > buses_supported |= CHIP_BUSTYPE_SPI; > - spi_controller = SPI_CONTROLLER_DUMMY; > + spi_programmer = &spi_programmer_dummy; > msg_pdbg("Enabling support for %s flash.\n", "SPI"); > } > if (buses_supported == CHIP_BUSTYPE_NONE) > @@ -140,7 +142,7 @@ void dummy_chip_readn(uint8_t *buf, const chipaddr addr, size_t len) > return; > } > > -int dummy_spi_send_command(unsigned int writecnt, unsigned int readcnt, > +static int dummy_spi_send_command(unsigned int writecnt, unsigned int readcnt, > const unsigned char *writearr, unsigned char *readarr) > { > int i; > @@ -161,7 +163,7 @@ int dummy_spi_send_command(unsigned int writecnt, unsigned int readcnt, > return 0; > } > > -int dummy_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len) > +static int dummy_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len) > { > /* Maximum read length is unlimited, use 64kB. */ > return spi_read_chunked(flash, buf, start, len, 64 * 1024); > @@ -171,7 +173,15 @@ int dummy_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len) > * never be successful, and the current frontend refuses to write in that case. > * Other frontends may allow writing even for non-detected chips, though. > */ > -int dummy_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int len) > +static int dummy_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int len) > { > return spi_write_chunked(flash, buf, start, len, 256); > } > + > +static const struct spi_programmer spi_programmer_dummy = { > + .type = SPI_CONTROLLER_DUMMY, > + .command = dummy_spi_send_command, > + .multicommand = default_spi_send_multicommand, > + .read = dummy_spi_read, > + .write_256 = dummy_spi_write_256, > +}; > diff --git a/flash.h b/flash.h > index 8ebea29..fb06207 100644 > --- a/flash.h > +++ b/flash.h > @@ -452,10 +452,6 @@ uint8_t dummy_chip_readb(const chipaddr addr); > uint16_t dummy_chip_readw(const chipaddr addr); > uint32_t dummy_chip_readl(const chipaddr addr); > void dummy_chip_readn(uint8_t *buf, const chipaddr addr, size_t len); > -int dummy_spi_send_command(unsigned int writecnt, unsigned int readcnt, > - const unsigned char *writearr, unsigned char *readarr); > -int dummy_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len); > -int dummy_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int len); > #endif > > /* nic3com.c */ > @@ -527,9 +523,6 @@ extern const struct pcidev_status ata_hpt[]; > #define FTDI_FT2232H 0x6010 > #define FTDI_FT4232H 0x6011 > int ft2232_spi_init(void); > -int ft2232_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); > -int ft2232_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len); > -int ft2232_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int len); > > /* bitbang_spi.c */ > int bitbang_spi_init(const struct bitbang_spi_master *master, int halfperiod); > @@ -544,15 +537,10 @@ struct buspirate_spispeeds { > }; > int buspirate_spi_init(void); > int buspirate_spi_shutdown(void); > -int buspirate_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); > -int buspirate_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len); > -int buspirate_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int len); > > /* dediprog.c */ > int dediprog_init(void); > int dediprog_shutdown(void); > -int dediprog_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); > -int dediprog_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len); > > /* flashrom.c */ > enum write_granularity { > @@ -627,32 +615,18 @@ int handle_romentries(uint8_t *buffer, struct flashchip *flash); > > /* spi.c */ > enum spi_controller { > - SPI_CONTROLLER_NONE, > -#if CONFIG_INTERNAL == 1 > -#if defined(__i386__) || defined(__x86_64__) > SPI_CONTROLLER_ICH7, > SPI_CONTROLLER_ICH9, > SPI_CONTROLLER_IT87XX, > SPI_CONTROLLER_SB600, > SPI_CONTROLLER_VIA, > SPI_CONTROLLER_WBSIO, > -#endif > -#endif > -#if CONFIG_FT2232_SPI == 1 > SPI_CONTROLLER_FT2232, > -#endif > -#if CONFIG_DUMMY == 1 > SPI_CONTROLLER_DUMMY, > -#endif > -#if CONFIG_BUSPIRATE_SPI == 1 > SPI_CONTROLLER_BUSPIRATE, > -#endif > -#if CONFIG_DEDIPROG == 1 > SPI_CONTROLLER_DEDIPROG, > -#endif > - SPI_CONTROLLER_INVALID /* This must always be the last entry. */ > Could you leave the #ifdefs in place for now? > }; > -extern const int spi_programmer_count; > + > struct spi_command { > unsigned int writecnt; > unsigned int readcnt; > @@ -660,6 +634,7 @@ struct spi_command { > unsigned char *readarr; > }; > struct spi_programmer { > + enum spi_controller type; > int (*command)(unsigned int writecnt, unsigned int readcnt, > const unsigned char *writearr, unsigned char *readarr); > int (*multicommand)(struct spi_command *cmds); > @@ -669,8 +644,8 @@ struct spi_programmer { > int (*write_256)(struct flashchip *flash, uint8_t *buf, int start, int len); > }; > > -extern enum spi_controller spi_controller; > -extern const struct spi_programmer spi_programmer[]; > +const struct spi_programmer *spi_programmer; > + > int spi_send_command(unsigned int writecnt, unsigned int readcnt, > const unsigned char *writearr, unsigned char *readarr); > int spi_send_multicommand(struct spi_command *cmds); > @@ -684,11 +659,6 @@ extern uint32_t ichspi_bbar; > void ich_init_spi(struct pci_dev *dev, uint32_t base, void * rcrb, > int ich_generation); > int via_init_spi(struct pci_dev * dev); > -int ich_spi_send_command(unsigned int writecnt, unsigned int readcnt, > - const unsigned char *writearr, unsigned char *readarr); > -int ich_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len); > -int ich_spi_write_256(struct flashchip *flash, uint8_t * buf, int start, int len); > -int ich_spi_send_multicommand(struct spi_command *cmds); > > /* it87spi.c */ > void enter_conf_mode_ite(uint16_t port); > @@ -696,23 +666,12 @@ void exit_conf_mode_ite(uint16_t port); > struct superio probe_superio_ite(void); > int init_superio_ite(void); > int it87spi_init(void); > -int it8716f_spi_send_command(unsigned int writecnt, unsigned int readcnt, > - const unsigned char *writearr, unsigned char *readarr); > -int it8716f_spi_chip_read(struct flashchip *flash, uint8_t *buf, int start, int len); > -int it8716f_spi_chip_write_256(struct flashchip *flash, uint8_t *buf, int start, int len); > > /* sb600spi.c */ > void sb600_probe_spi(struct pci_dev * dev); > -int sb600_spi_send_command(unsigned int writecnt, unsigned int readcnt, > - const unsigned char *writearr, unsigned char *readarr); > -int sb600_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len); > -int sb600_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int len); > > /* wbsio_spi.c */ > int wbsio_check_for_spi(void); > -int wbsio_spi_send_command(unsigned int writecnt, unsigned int readcnt, > - const unsigned char *writearr, unsigned char *readarr); > -int wbsio_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len); > > /* serprog.c */ > int serprog_init(void); > diff --git a/flashrom.c b/flashrom.c > index fe173a7..dc262d5 100644 > --- a/flashrom.c > +++ b/flashrom.c > @@ -1354,10 +1354,6 @@ int selfcheck(void) > msg_gerr("Programmer table miscompilation!\n"); > ret = 1; > } > - if (spi_programmer_count - 1 != SPI_CONTROLLER_INVALID) { > - msg_gerr("SPI programmer table miscompilation!\n"); > - ret = 1; > - } > for (flash = flashchips; flash && flash->name; flash++) > if (selfcheck_eraseblocks(flash)) > ret = 1; > diff --git a/ft2232_spi.c b/ft2232_spi.c > index c8711e9..b45ba42 100644 > --- a/ft2232_spi.c > +++ b/ft2232_spi.c > @@ -45,6 +45,7 @@ > #define BITMODE_BITBANG_NORMAL 1 > #define BITMODE_BITBANG_SPI 2 > > +static const struct spi_programmer spi_programmer_ft2232; > static struct ftdi_context ftdic_context; > > static int send_buf(struct ftdi_context *ftdic, const unsigned char *buf, int size) > @@ -192,7 +193,7 @@ int ft2232_spi_init(void) > // msg_pdbg("\nft2232 chosen\n"); > > buses_supported = CHIP_BUSTYPE_SPI; > - spi_controller = SPI_CONTROLLER_FT2232; > + spi_programmer = &spi_programmer_ft2232; > > return 0; > } > @@ -293,4 +294,12 @@ int ft2232_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int l > return spi_write_chunked(flash, buf, start, len, 256); > } > > +static const struct spi_programmer spi_programmer_ft2232 = { > + .type = SPI_CONTROLLER_FT2232, > + .command = ft2232_spi_send_command, > + .multicommand = default_spi_send_multicommand, > + .read = ft2232_spi_read, > + .write_256 = ft2232_spi_write_256, > +}; > + > #endif > diff --git a/ichspi.c b/ichspi.c > index 246f3ae..ae9a5f4 100644 > --- a/ichspi.c > +++ b/ichspi.c > @@ -106,6 +106,9 @@ static int ichspi_lock = 0; > uint32_t ichspi_bbar = 0; > > static void *ich_spibar = NULL; > +static const struct spi_programmer spi_programmer_ich7; > +static const struct spi_programmer spi_programmer_ich9; > +static const struct spi_programmer spi_programmer_via; > > typedef struct _OPCODE { > uint8_t opcode; //This commands spi opcode > @@ -234,7 +237,7 @@ static int generate_opcodes(OPCODES * op) > return -1; > } > > - switch (spi_controller) { > + switch (spi_programmer->type) { > We need to decide whether we want to access spi_programmer directly. It works in your patch, but if we go the route towards multiple SPI programmers on one board, we have to be sure to access the correct spi_programmer (maybe array member, maybe something else). If you have any neat ideas, please come forward. Otherwise I'd say your code is a good solution for now, and once we add support for registering multiple programmers, we'll notice this location because compilation will fail. > case SPI_CONTROLLER_ICH7: > case SPI_CONTROLLER_VIA: > preop = REGREAD16(ICH7_REG_PREOP); > @@ -309,7 +312,7 @@ int program_opcodes(OPCODES * op) > } > > msg_pdbg("\n%s: preop=%04x optype=%04x opmenu=%08x%08x\n", __func__, preop, optype, opmenu[0], opmenu[1]); > - switch (spi_controller) { > + switch (spi_programmer->type) { > case SPI_CONTROLLER_ICH7: > case SPI_CONTROLLER_VIA: > REGWRITE16(ICH7_REG_PREOP, preop); > @@ -337,7 +340,7 @@ int program_opcodes(OPCODES * op) > */ > void ich_set_bbar(uint32_t minaddr) > { > - switch (spi_controller) { > + switch (spi_programmer->type) { > case SPI_CONTROLLER_ICH7: > mmio_writel(minaddr, ich_spibar + 0x50); > ichspi_bbar = mmio_readl(ich_spibar + 0x50); > @@ -448,19 +451,19 @@ void ich_init_spi(struct pci_dev *dev, uint32_t base, void * rcrb, > switch (ich_generation) { > case 7: > buses_supported = CHIP_BUSTYPE_SPI; > - spi_controller = SPI_CONTROLLER_ICH7; > + spi_programmer = &spi_programmer_ich7; > spibar_offset = 0x3020; > break; > case 8: > buses_supported = CHIP_BUSTYPE_FWH | CHIP_BUSTYPE_SPI; > - spi_controller = SPI_CONTROLLER_ICH9; > + spi_programmer = &spi_programmer_ich9; > spibar_offset = 0x3020; > break; > case 9: > case 10: > default: /* Future version might behave the same */ > buses_supported = CHIP_BUSTYPE_FWH | CHIP_BUSTYPE_SPI; > - spi_controller = SPI_CONTROLLER_ICH9; > + spi_programmer = &spi_programmer_ich9; > spibar_offset = 0x3800; > break; > } > @@ -471,7 +474,7 @@ void ich_init_spi(struct pci_dev *dev, uint32_t base, void * rcrb, > /* Assign Virtual Address */ > ich_spibar = rcrb + spibar_offset; > > - switch (spi_controller) { > + switch (spi_programmer->type) { > case SPI_CONTROLLER_ICH7: > msg_pdbg("0x00: 0x%04x (SPIS)\n", > mmio_readw(ich_spibar + 0)); > @@ -600,7 +603,7 @@ int via_init_spi(struct pci_dev * dev) > > /* Not sure if it speaks all these bus protocols. */ > buses_supported = CHIP_BUSTYPE_LPC | CHIP_BUSTYPE_FWH | CHIP_BUSTYPE_SPI; > - spi_controller = SPI_CONTROLLER_VIA; > + spi_programmer = &spi_programmer_via; > ich_init_opcodes(); > > return 0; > @@ -848,7 +851,7 @@ static int ich9_run_opcode(OPCODE op, uint32_t offset, > static int run_opcode(OPCODE op, uint32_t offset, > uint8_t datalength, uint8_t * data) > { > - switch (spi_controller) { > + switch (spi_programmer->type) { > case SPI_CONTROLLER_VIA: > if (datalength > 16) { > msg_perr("%s: Internal command size error for " > @@ -881,27 +884,27 @@ static int run_opcode(OPCODE op, uint32_t offset, > return -1; > } > > -int ich_spi_read(struct flashchip *flash, uint8_t * buf, int start, int len) > +static int ich_spi_read(struct flashchip *flash, uint8_t * buf, int start, int len) > { > int maxdata = 64; > > - if (spi_controller == SPI_CONTROLLER_VIA) > + if (spi_programmer->type == SPI_CONTROLLER_VIA) > maxdata = 16; > > return spi_read_chunked(flash, buf, start, len, maxdata); > } > > -int ich_spi_write_256(struct flashchip *flash, uint8_t * buf, int start, int len) > +static int ich_spi_write_256(struct flashchip *flash, uint8_t * buf, int start, int len) > { > int maxdata = 64; > > - if (spi_controller == SPI_CONTROLLER_VIA) > + if (spi_programmer->type == SPI_CONTROLLER_VIA) > maxdata = 16; > > return spi_write_chunked(flash, buf, start, len, maxdata); > } > > -int ich_spi_send_command(unsigned int writecnt, unsigned int readcnt, > +static int ich_spi_send_command(unsigned int writecnt, unsigned int readcnt, > const unsigned char *writearr, unsigned char *readarr) > { > int result; > @@ -966,7 +969,7 @@ int ich_spi_send_command(unsigned int writecnt, unsigned int readcnt, > opcode->spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS) { > addr = (writearr[1] << 16) | > (writearr[2] << 8) | (writearr[3] << 0); > - switch (spi_controller) { > + switch (spi_programmer->type) { > case SPI_CONTROLLER_ICH7: > case SPI_CONTROLLER_ICH9: > if (addr < ichspi_bbar) { > @@ -1001,7 +1004,7 @@ int ich_spi_send_command(unsigned int writecnt, unsigned int readcnt, > return result; > } > > -int ich_spi_send_multicommand(struct spi_command *cmds) > +static int ich_spi_send_multicommand(struct spi_command *cmds) > { > int ret = 0; > int i; > @@ -1071,4 +1074,28 @@ int ich_spi_send_multicommand(struct spi_command *cmds) > return ret; > } > > +static const struct spi_programmer spi_programmer_ich7 = { > + .type = SPI_CONTROLLER_ICH7, > + .command = ich_spi_send_command, > + .multicommand = ich_spi_send_multicommand, > + .read = ich_spi_read, > + .write_256 = ich_spi_write_256, > +}; > + > +static const struct spi_programmer spi_programmer_ich9 = { > + .type = SPI_CONTROLLER_ICH9, > + .command = ich_spi_send_command, > + .multicommand = ich_spi_send_multicommand, > + .read = ich_spi_read, > + .write_256 = ich_spi_write_256, > +}; > + > +static const struct spi_programmer spi_programmer_via = { > + .type = SPI_CONTROLLER_VIA, > + .command = ich_spi_send_command, > + .multicommand = ich_spi_send_multicommand, > + .read = ich_spi_read, > + .write_256 = ich_spi_write_256, > +}; > + > #endif > diff --git a/it87spi.c b/it87spi.c > index cf3d3b9..dddb5a9 100644 > --- a/it87spi.c > +++ b/it87spi.c > @@ -34,6 +34,8 @@ > #define ITE_SUPERIO_PORT1 0x2e > #define ITE_SUPERIO_PORT2 0x4e > > +static const struct spi_programmer spi_programmer_it87xx; > + > uint16_t it8716f_flashport = 0; > /* use fast 33MHz SPI (<>0) or slow 16MHz (0) */ > static int fast_spi = 1; > @@ -175,7 +177,7 @@ static uint16_t it87spi_probe(uint16_t port) > it8716f_flashport = flashport; > if (buses_supported & CHIP_BUSTYPE_SPI) > msg_pdbg("Overriding chipset SPI with IT87 SPI.\n"); > - spi_controller = SPI_CONTROLLER_IT87XX; > + spi_programmer = &spi_programmer_it87xx; > buses_supported |= CHIP_BUSTYPE_SPI; > return 0; > } > @@ -227,7 +229,7 @@ int it87spi_init(void) > * commands with the address in inverse wire order. That's why the register > * ordering in case 4 and 5 may seem strange. > */ > -int it8716f_spi_send_command(unsigned int writecnt, unsigned int readcnt, > +static int it8716f_spi_send_command(unsigned int writecnt, unsigned int readcnt, > const unsigned char *writearr, unsigned char *readarr) > { > uint8_t busy, writeenc; > @@ -320,7 +322,7 @@ static int it8716f_spi_page_program(struct flashchip *flash, uint8_t *buf, int s > * IT8716F only allows maximum of 512 kb SPI mapped to LPC memory cycles > * Need to read this big flash using firmware cycles 3 byte at a time. > */ > -int it8716f_spi_chip_read(struct flashchip *flash, uint8_t *buf, int start, int len) > +static int it8716f_spi_chip_read(struct flashchip *flash, uint8_t *buf, int start, int len) > { > int total_size = 1024 * flash->total_size; > fast_spi = 0; > @@ -334,7 +336,7 @@ int it8716f_spi_chip_read(struct flashchip *flash, uint8_t *buf, int start, int > return 0; > } > > -int it8716f_spi_chip_write_256(struct flashchip *flash, uint8_t *buf, int start, int len) > +static int it8716f_spi_chip_write_256(struct flashchip *flash, uint8_t *buf, int start, int len) > { > /* > * IT8716F only allows maximum of 512 kb SPI chip size for memory > @@ -371,4 +373,12 @@ int it8716f_spi_chip_write_256(struct flashchip *flash, uint8_t *buf, int start, > return 0; > } > > +static const struct spi_programmer spi_programmer_it87xx = { > + .type = SPI_CONTROLLER_IT87XX, > + .command = it8716f_spi_send_command, > + .multicommand = default_spi_send_multicommand, > + .read = it8716f_spi_chip_read, > + .write_256 = it8716f_spi_chip_write_256, > +}; > + > #endif > diff --git a/sb600spi.c b/sb600spi.c > index e42b20b..866e309 100644 > --- a/sb600spi.c > +++ b/sb600spi.c > @@ -41,6 +41,7 @@ > */ > > static uint8_t *sb600_spibar = NULL; > +static const struct spi_programmer spi_programmer_sb600; > > void sb600_probe_spi(struct pci_dev * dev) > { > @@ -114,16 +115,16 @@ void sb600_probe_spi(struct pci_dev * dev) > return; > > buses_supported |= CHIP_BUSTYPE_SPI; > - spi_controller = SPI_CONTROLLER_SB600; > + spi_programmer = &spi_programmer_sb600; > } > > -int sb600_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len) > +static int sb600_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len) > { > /* Maximum read length is 8 bytes. */ > return spi_read_chunked(flash, buf, start, len, 8); > } > > -int sb600_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int len) > +static int sb600_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int len) > { > return spi_write_chunked(flash, buf, start, len, 5); > } > @@ -144,7 +145,7 @@ static void execute_command(void) > ; > } > > -int sb600_spi_send_command(unsigned int writecnt, unsigned int readcnt, > +static int sb600_spi_send_command(unsigned int writecnt, unsigned int readcnt, > const unsigned char *writearr, unsigned char *readarr) > { > int count; > @@ -227,4 +228,12 @@ int sb600_spi_send_command(unsigned int writecnt, unsigned int readcnt, > return 0; > } > > +static const struct spi_programmer spi_programmer_sb600 = { > + .type = SPI_CONTROLLER_SB600, > + .command = sb600_spi_send_command, > + .multicommand = default_spi_send_multicommand, > + .read = sb600_spi_read, > + .write_256 = sb600_spi_write_256, > +}; > + > #endif > diff --git a/spi.c b/spi.c > index 2b64463..dc4da9f 100644 > --- a/spi.c > +++ b/spi.c > @@ -27,129 +27,34 @@ > #include "chipdrivers.h" > #include "spi.h" > > -enum spi_controller spi_controller = SPI_CONTROLLER_NONE; > - > void spi_prettyprint_status_register(struct flashchip *flash); > > -const struct spi_programmer spi_programmer[] = { > - { /* SPI_CONTROLLER_NONE */ > - .command = NULL, > - .multicommand = NULL, > - .read = NULL, > - .write_256 = NULL, > - }, > - > -#if CONFIG_INTERNAL == 1 > -#if defined(__i386__) || defined(__x86_64__) > - { /* SPI_CONTROLLER_ICH7 */ > - .command = ich_spi_send_command, > - .multicommand = ich_spi_send_multicommand, > - .read = ich_spi_read, > - .write_256 = ich_spi_write_256, > - }, > - > - { /* SPI_CONTROLLER_ICH9 */ > - .command = ich_spi_send_command, > - .multicommand = ich_spi_send_multicommand, > - .read = ich_spi_read, > - .write_256 = ich_spi_write_256, > - }, > - > - { /* SPI_CONTROLLER_IT87XX */ > - .command = it8716f_spi_send_command, > - .multicommand = default_spi_send_multicommand, > - .read = it8716f_spi_chip_read, > - .write_256 = it8716f_spi_chip_write_256, > - }, > - > - { /* SPI_CONTROLLER_SB600 */ > - .command = sb600_spi_send_command, > - .multicommand = default_spi_send_multicommand, > - .read = sb600_spi_read, > - .write_256 = sb600_spi_write_256, > - }, > - > - { /* SPI_CONTROLLER_VIA */ > - .command = ich_spi_send_command, > - .multicommand = ich_spi_send_multicommand, > - .read = ich_spi_read, > - .write_256 = ich_spi_write_256, > - }, > - > - { /* SPI_CONTROLLER_WBSIO */ > - .command = wbsio_spi_send_command, > - .multicommand = default_spi_send_multicommand, > - .read = wbsio_spi_read, > - .write_256 = spi_chip_write_1_new, > - }, > -#endif > -#endif > - > -#if CONFIG_FT2232_SPI == 1 > - { /* SPI_CONTROLLER_FT2232 */ > - .command = ft2232_spi_send_command, > - .multicommand = default_spi_send_multicommand, > - .read = ft2232_spi_read, > - .write_256 = ft2232_spi_write_256, > - }, > -#endif > - > -#if CONFIG_DUMMY == 1 > - { /* SPI_CONTROLLER_DUMMY */ > - .command = dummy_spi_send_command, > - .multicommand = default_spi_send_multicommand, > - .read = dummy_spi_read, > - .write_256 = dummy_spi_write_256, > - }, > -#endif > - > -#if CONFIG_BUSPIRATE_SPI == 1 > - { /* SPI_CONTROLLER_BUSPIRATE */ > - .command = buspirate_spi_send_command, > - .multicommand = default_spi_send_multicommand, > - .read = buspirate_spi_read, > - .write_256 = buspirate_spi_write_256, > - }, > -#endif > - > -#if CONFIG_DEDIPROG == 1 > - { /* SPI_CONTROLLER_DEDIPROG */ > - .command = dediprog_spi_send_command, > - .multicommand = default_spi_send_multicommand, > - .read = dediprog_spi_read, > - .write_256 = spi_chip_write_1_new, > - }, > -#endif > - > - {}, /* This entry corresponds to SPI_CONTROLLER_INVALID. */ > -}; > - > -const int spi_programmer_count = ARRAY_SIZE(spi_programmer); > +const struct spi_programmer *spi_programmer; > If someone forces a SPI access on a programmer which does not support SPI, this will explode AFAICS because it means following an uninitialized pointer to check for NULL in a struct member which does not exist. > > int spi_send_command(unsigned int writecnt, unsigned int readcnt, > const unsigned char *writearr, unsigned char *readarr) > { > - if (!spi_programmer[spi_controller].command) { > + if (!spi_programmer->command) { > msg_perr("%s called, but SPI is unsupported on this " > "hardware. Please report a bug at " > "flashrom(a)flashrom.org\n", __func__); > return 1; > } > > - return spi_programmer[spi_controller].command(writecnt, readcnt, > + return spi_programmer->command(writecnt, readcnt, > writearr, readarr); > } > > int spi_send_multicommand(struct spi_command *cmds) > { > - if (!spi_programmer[spi_controller].multicommand) { > + if (!spi_programmer->multicommand) { > msg_perr("%s called, but SPI is unsupported on this " > "hardware. Please report a bug at " > "flashrom(a)flashrom.org\n", __func__); > return 1; > } > > - return spi_programmer[spi_controller].multicommand(cmds); > + return spi_programmer->multicommand(cmds); > } > > int default_spi_send_command(unsigned int writecnt, unsigned int readcnt, > @@ -183,14 +88,14 @@ int default_spi_send_multicommand(struct spi_command *cmds) > > int spi_chip_read(struct flashchip *flash, uint8_t *buf, int start, int len) > { > - if (!spi_programmer[spi_controller].read) { > + if (!spi_programmer->read) { > msg_perr("%s called, but SPI read is unsupported on this " > "hardware. Please report a bug at " > "flashrom(a)flashrom.org\n", __func__); > return 1; > } > > - return spi_programmer[spi_controller].read(flash, buf, start, len); > + return spi_programmer->read(flash, buf, start, len); > } > > /* > @@ -202,14 +107,14 @@ int spi_chip_read(struct flashchip *flash, uint8_t *buf, int start, int len) > /* real chunksize is up to 256, logical chunksize is 256 */ > int spi_chip_write_256_new(struct flashchip *flash, uint8_t *buf, int start, int len) > { > - if (!spi_programmer[spi_controller].write_256) { > + if (!spi_programmer->write_256) { > msg_perr("%s called, but SPI page write is unsupported on this " > "hardware. Please report a bug at " > "flashrom(a)flashrom.org\n", __func__); > return 1; > } > > - return spi_programmer[spi_controller].write_256(flash, buf, start, len); > + return spi_programmer->write_256(flash, buf, start, len); > } > > /* Wrapper function until the generic code is converted to partial writes. */ > @@ -239,7 +144,7 @@ int spi_chip_write_256(struct flashchip *flash, uint8_t *buf) > */ > uint32_t spi_get_valid_read_addr(void) > { > - switch (spi_controller) { > + switch (spi_programmer->type) { > #if CONFIG_INTERNAL == 1 > #if defined(__i386__) || defined(__x86_64__) > case SPI_CONTROLLER_ICH7: > diff --git a/spi25.c b/spi25.c > index 32bb73c..d9dae35 100644 > --- a/spi25.c > +++ b/spi25.c > @@ -177,7 +177,7 @@ int probe_spi_rdid4(struct flashchip *flash) > /* Some SPI controllers do not support commands with writecnt=1 and > * readcnt=4. > */ > - switch (spi_controller) { > + switch (spi_programmer->type) { > #if CONFIG_INTERNAL == 1 > #if defined(__i386__) || defined(__x86_64__) > case SPI_CONTROLLER_IT87XX: > @@ -1019,7 +1019,7 @@ int spi_aai_write(struct flashchip *flash, uint8_t *buf, int start, int len) > .readarr = NULL, > }}; > > - switch (spi_controller) { > + switch (spi_programmer->type) { > #if CONFIG_INTERNAL == 1 > #if defined(__i386__) || defined(__x86_64__) > case SPI_CONTROLLER_IT87XX: > diff --git a/wbsio_spi.c b/wbsio_spi.c > index b8f8b38..6288340 100644 > --- a/wbsio_spi.c > +++ b/wbsio_spi.c > @@ -28,6 +28,7 @@ > #define WBSIO_PORT2 0x4e > > static uint16_t wbsio_spibase = 0; > +static const struct spi_programmer spi_programmer_wbsio; > > static uint16_t wbsio_get_spibase(uint16_t port) > { > @@ -68,7 +69,7 @@ int wbsio_check_for_spi(void) > msg_pspew("\nwbsio_spibase = 0x%x\n", wbsio_spibase); > > buses_supported |= CHIP_BUSTYPE_SPI; > - spi_controller = SPI_CONTROLLER_WBSIO; > + spi_programmer = &spi_programmer_wbsio; > msg_pdbg("%s: Winbond saved on 4 register bits so max chip size is " > "1024 KB!\n", __func__); > max_rom_decode.spi = 1024 * 1024; > @@ -96,7 +97,7 @@ int wbsio_check_for_spi(void) > * Would one more byte of RAM in the chip (to get all 24 bits) really make > * such a big difference? > */ > -int wbsio_spi_send_command(unsigned int writecnt, unsigned int readcnt, > +static int wbsio_spi_send_command(unsigned int writecnt, unsigned int readcnt, > const unsigned char *writearr, unsigned char *readarr) > { > int i; > @@ -180,9 +181,18 @@ int wbsio_spi_send_command(unsigned int writecnt, unsigned int readcnt, > return 0; > } > > -int wbsio_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len) > +static int wbsio_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len) > { > return read_memmapped(flash, buf, start, len); > } > > +static const struct spi_programmer spi_programmer_wbsio = { > + .type = SPI_CONTROLLER_WBSIO, > + .command = wbsio_spi_send_command, > + .multicommand = default_spi_send_multicommand, > + .read = wbsio_spi_read, > + .write_256 = spi_chip_write_1_new, > +}; > + > + > #endif > Looks good otherwise. Regards, Carl-Daniel -- http://www.hailfinger.org/

1 0

SUCCESS: Gigabyte GA-M61P-S3
by Simon Elsbrock 05 Mar '11

05 Mar '11

http://paste.flashrom.org/view.php?id=384 http://paste.flashrom.org/view.php?id=385 http://paste.flashrom.org/view.php?id=386

1 0

[PATCH] Add mainboards to print.c and mark writing as tested on Winbond W25x80
by Yul Rottmann 05 Mar '11

05 Mar '11

Hello List, I successfully tested flashrom on my MSI MS-7596 (785GM-E51). Here is the patch to add it to the list of supported mainboards. Also I marked writing as tested on the flashchip that belongs to it. Earlier I reported the success of flashing my GIGABYTE GA-MA78G-DS3H. This patch makes clear that it is about the revision 1.0. I also tested flashing an ASRock 890GX Extreme3, which worked. I also added it to print.c. If you have questions, please contact me on my private e-mail adress since I haven't subscribed to the mailinglist. Thanks! Signed-off-by: Yul Rottmann <yulrottmann(a)bitel.net>

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