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Re: [flashrom] [PATCH 1/4] ichspi.c: refactor filling and reading the fdata/spid registers
by Stefan Tauner 09 Aug '11

09 Aug '11

On Thu, 21 Jul 2011 01:24:22 +0200 Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> wrote: > - add ich_fill_data to fill the chipset registers from an array > - add ich_read_data to copy the data from the chipset register into an array > - replace the existing code with calls to those functions > - minor cosmetic changes > > Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> > Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> tested by david hendrix and finally committed in r1409 \o/ -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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[commit] r1409 - trunk
by repository service 09 Aug '11

09 Aug '11

Author: stefanct Date: Tue Aug 9 03:49:34 2011 New Revision: 1409 URL: http://flashrom.org/trac/flashrom/changeset/1409 Log: ichspi.c: refactor filling and reading the fdata/spid registers - add ich_fill_data to fill the chipset registers from an array - add ich_read_data to copy the data from the chipset register into an array - replace the existing code with calls to those functions - minor cosmetic changes Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: trunk/ichspi.c Modified: trunk/ichspi.c ============================================================================== --- trunk/ichspi.c Sun Aug 7 15:17:20 2011 (r1408) +++ trunk/ichspi.c Tue Aug 9 03:49:34 2011 (r1409) @@ -6,6 +6,7 @@ * Copyright (C) 2008 Dominik Geyer <dominik.geyer(a)kontron.com> * Copyright (C) 2008 coresystems GmbH <info(a)coresystems.de> * Copyright (C) 2009, 2010 Carl-Daniel Hailfinger + * Copyright (C) 2011 Stefan Tauner * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -22,18 +23,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -/* - * This module is designed for supporting the devices - * ST M25P40 - * ST M25P80 - * ST M25P16 - * ST M25P32 already tested - * ST M25P64 - * AT 25DF321 already tested - * ... and many more SPI flash devices - * - */ - #if defined(__i386__) || defined(__x86_64__) #include <string.h> @@ -293,7 +282,7 @@ static OPCODES O_EXISTING = {}; /* pretty printing functions */ -static void pretty_print_opcodes(OPCODES *ops) +static void prettyprint_opcodes(OPCODES *ops) { if(ops == NULL) return; @@ -592,6 +581,51 @@ msg_perr("Setting BBAR failed!\n"); } +/* Read len bytes from the fdata/spid register into the data array. + * + * Note that using len > spi_programmer->max_data_read will return garbage or + * may even crash. + */ + static void ich_read_data(uint8_t *data, int len, int reg0_off) + { + int i; + uint32_t temp32 = 0; + + for (i = 0; i < len; i++) { + if ((i % 4) == 0) + temp32 = REGREAD32(reg0_off + i); + + data[i] = (temp32 >> ((i % 4) * 8)) & 0xff; + } +} + +/* Fill len bytes from the data array into the fdata/spid registers. + * + * Note that using len > spi_programmer->max_data_write will trash the registers + * following the data registers. + */ +static void ich_fill_data(const uint8_t *data, int len, int reg0_off) +{ + uint32_t temp32 = 0; + int i; + + if (len <= 0) + return; + + for (i = 0; i < len; i++) { + if ((i % 4) == 0) + temp32 = 0; + + temp32 |= ((uint32_t) data[i]) << ((i % 4) * 8); + + if ((i % 4) == 3) /* 32 bits are full, write them to regs. */ + REGWRITE32(reg0_off + (i - (i % 4)), temp32); + } + i--; + if ((i % 4) != 3) /* Write remaining data to regs. */ + REGWRITE32(reg0_off + (i - (i % 4)), temp32); +} + /* This function generates OPCODES from or programs OPCODES to ICH according to * the chipset's SPI configuration lock. * @@ -627,7 +661,7 @@ } else { curopcodes = curopcodes_done; msg_pdbg("done\n"); - pretty_print_opcodes(curopcodes); + prettyprint_opcodes(curopcodes); msg_pdbg("\n"); return 0; } @@ -638,9 +672,8 @@ { int write_cmd = 0; int timeout; - uint32_t temp32 = 0; + uint32_t temp32; uint16_t temp16; - uint32_t a; uint64_t opmenu; int opcode_index; @@ -664,26 +697,8 @@ REGWRITE32(ICH7_REG_SPIA, (offset & 0x00FFFFFF) | temp32); /* Program data into SPID0 to N */ - if (write_cmd && (datalength != 0)) { - temp32 = 0; - for (a = 0; a < datalength; a++) { - if ((a % 4) == 0) { - temp32 = 0; - } - - temp32 |= ((uint32_t) data[a]) << ((a % 4) * 8); - - if ((a % 4) == 3) { - REGWRITE32(ICH7_REG_SPID0 + (a - (a % 4)), - temp32); - } - } - if (((a - 1) % 4) != 3) { - REGWRITE32(ICH7_REG_SPID0 + - ((a - 1) - ((a - 1) % 4)), temp32); - } - - } + if (write_cmd && (datalength != 0)) + ich_fill_data(data, datalength, ICH7_REG_SPID0); /* Assemble SPIS */ temp16 = REGREAD16(ICH7_REG_SPIS); @@ -764,17 +779,8 @@ return 1; } - if ((!write_cmd) && (datalength != 0)) { - for (a = 0; a < datalength; a++) { - if ((a % 4) == 0) { - temp32 = REGREAD32(ICH7_REG_SPID0 + (a)); - } - - data[a] = - (temp32 & (((uint32_t) 0xff) << ((a % 4) * 8))) - >> ((a % 4) * 8); - } - } + if ((!write_cmd) && (datalength != 0)) + ich_read_data(data, datalength, ICH7_REG_SPID0); return 0; } @@ -785,7 +791,6 @@ int write_cmd = 0; int timeout; uint32_t temp32; - uint32_t a; uint64_t opmenu; int opcode_index; @@ -810,25 +815,8 @@ REGWRITE32(ICH9_REG_FADDR, (offset & 0x00FFFFFF) | temp32); /* Program data into FDATA0 to N */ - if (write_cmd && (datalength != 0)) { - temp32 = 0; - for (a = 0; a < datalength; a++) { - if ((a % 4) == 0) { - temp32 = 0; - } - - temp32 |= ((uint32_t) data[a]) << ((a % 4) * 8); - - if ((a % 4) == 3) { - REGWRITE32(ICH9_REG_FDATA0 + (a - (a % 4)), - temp32); - } - } - if (((a - 1) % 4) != 3) { - REGWRITE32(ICH9_REG_FDATA0 + - ((a - 1) - ((a - 1) % 4)), temp32); - } - } + if (write_cmd && (datalength != 0)) + ich_fill_data(data, datalength, ICH9_REG_FDATA0); /* Assemble SSFS + SSFC */ temp32 = REGREAD32(ICH9_REG_SSFS); @@ -916,17 +904,8 @@ return 1; } - if ((!write_cmd) && (datalength != 0)) { - for (a = 0; a < datalength; a++) { - if ((a % 4) == 0) { - temp32 = REGREAD32(ICH9_REG_FDATA0 + (a)); - } - - data[a] = - (temp32 & (((uint32_t) 0xff) << ((a % 4) * 8))) - >> ((a % 4) * 8); - } - } + if ((!write_cmd) && (datalength != 0)) + ich_read_data(data, datalength, ICH9_REG_FDATA0); return 0; }

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Re: [flashrom] [PATCH 8/8] Added (N) to the name of MX29F002B/T devices.
by Idwer Vollering 07 Aug '11

07 Aug '11

2011/3/15 Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at>: > Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Acked-by: Idwer Vollering <vidwer(a)gmail.com> But *only* if the probe/read/erase/write status is not affected. > --- > flashchips.c | 4 ++-- > flashchips.h | 4 ++-- > 2 files changed, 4 insertions(+), 4 deletions(-) > > diff --git a/flashchips.c b/flashchips.c > index 7cb7d39..97aafef 100644 > --- a/flashchips.c > +++ b/flashchips.c > @@ -4209,7 +4209,7 @@ struct flashchip flashchips[] = { > > { > .vendor = "Macronix", > - .name = "MX29F002B", > + .name = "MX29F002(N)B", > .bustype = CHIP_BUSTYPE_PARALLEL, > .manufacture_id = MACRONIX_ID, > .model_id = MACRONIX_MX29F002B, > @@ -4240,7 +4240,7 @@ struct flashchip flashchips[] = { > > { > .vendor = "Macronix", > - .name = "MX29F002T", > + .name = "MX29F002(N)T", > .bustype = CHIP_BUSTYPE_PARALLEL, > .manufacture_id = MACRONIX_ID, > .model_id = MACRONIX_MX29F002T, > diff --git a/flashchips.h b/flashchips.h > index 9b08d25..9782188 100644 > --- a/flashchips.h > +++ b/flashchips.h > @@ -361,8 +361,8 @@ > #define MACRONIX_MX25L3235D 0x5E16 /* MX25L3225D/MX25L3235D/MX25L3237D */ > #define MACRONIX_MX29F001B 0x19 > #define MACRONIX_MX29F001T 0x18 > -#define MACRONIX_MX29F002B 0x34 /* Same as MX29F002NB */ > -#define MACRONIX_MX29F002T 0xB0 /* Same as MX29F002NT */ > +#define MACRONIX_MX29F002B 0x34 /* Same as MX29F002NB; N has reset pin n/c. */ > +#define MACRONIX_MX29F002T 0xB0 /* Same as MX29F002NT; N has reset pin n/c. */ > #define MACRONIX_MX29F004B 0x46 > #define MACRONIX_MX29F004T 0x45 > #define MACRONIX_MX29F022T 0x36 /* Same as MX29F022NT */ > -- > 1.7.1 > > > _______________________________________________ > flashrom mailing list > flashrom(a)flashrom.org > http://www.flashrom.org/mailman/listinfo/flashrom >

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A8M2N-LA fail
by Márton Miklós 07 Aug '11

07 Aug '11

Hello all, I have just tried to flash my BIOS using the flashrom, and I have ran into the following situation: lucifer@lucifer-desktop:~/Letöltések/flashrom-0.9.4$ sudo ./flashrom -w /tmp/sp35111/3.10 flashrom v0.9.4-r1395 on Linux 2.6.35-28-generic (i686), built with libpci 3.1.7, GCC 4.4.5, little endian flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OK. Found chipset "NVIDIA MCP51". This chipset is marked as untested. If you are using an up-to-date version of flashrom please email a report to flashrom(a)flashrom.org including a verbose (-V) log. Thank you! Enabling flash write... OK. This chipset supports the following protocols: Non-SPI. Found PMC flash chip "Pm49FL004" (512 kB, LPC, FWH) at physical address 0xfff80000. Flash image seems to be a legacy BIOS. Disabling coreboot-related checks. Reading old flash chip contents... done. Erasing and writing flash chip... ERASE FAILED at 0x00000000! Expected=0xff, Read=0x23, failed byte count from 0x00000000-0x00000fff: 0xfec ERASE FAILED! Reading current flash chip contents... done. ERASE FAILED at 0x00000000! Expected=0xff, Read=0x23, failed byte count from 0x00000000-0x0000ffff: 0xfef9 ERASE FAILED! Reading current flash chip contents... done. ERASE FAILED at 0x00000000! Expected=0xff, Read=0x23, failed byte count from 0x00000000-0x0007ffff: 0x6494b ERASE FAILED! FAILED! Uh oh. Erase/write failed. Checking if anything changed. Good. It seems nothing was changed. Writing to the flash chip apparently didn't do anything. This means we have to add special support for your board, programmer or flash chip. Please report this on IRC at irc.freenode.net (channel #flashrom) or mail flashrom(a)flashrom.org! ------------------------------------------------------------------------------- You may now reboot or simply leave the machine running. Flashrom info: lucifer@lucifer-desktop:~/Letöltések/flashrom-0.9.4$ sudo ./flashrom flashrom v0.9.4-r1395 on Linux 2.6.35-28-generic (i686), built with libpci 3.1.7, GCC 4.4.5, little endian flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OK. Found chipset "NVIDIA MCP51". This chipset is marked as untested. If you are using an up-to-date version of flashrom please email a report to flashrom(a)flashrom.org including a verbose (-V) log. Thank you! Enabling flash write... OK. This chipset supports the following protocols: Non-SPI. Found PMC flash chip "Pm49FL004" (512 kB, LPC, FWH) at physical address 0xfff80000. No operations were specified. I have tried the latest revision (1402) but it did not works too. Let me know if I should provide any additional information. Regards, Miklós Márton

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[commit] r1408 - trunk
by repository service 07 Aug '11

07 Aug '11

Author: stefanct Date: Sun Aug 7 15:17:20 2011 New Revision: 1408 URL: http://flashrom.org/trac/flashrom/changeset/1408 Log: Add a board enable for ASUS A8M2N-LA (HP OEM "NodusM3-GL8E") It is based on Joshua Roys' RE. http://www.flashrom.org/pipermail/flashrom/2011-August/007504.html Tested-by: Márton Miklós Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Modified: trunk/board_enable.c trunk/chipset_enable.c trunk/print.c Modified: trunk/board_enable.c ============================================================================== --- trunk/board_enable.c Sat Aug 6 18:16:45 2011 (r1407) +++ trunk/board_enable.c Sun Aug 7 15:17:20 2011 (r1408) @@ -921,6 +921,7 @@ /* * Suited for: + * - ASUS A8M2N-LA (HP OEM "NodusM3-GL8E"): NVIDIA MCP51 * - ASUS A8N-LA (HP OEM "Nagami-GL8E"): NVIDIA MCP51 * - ASUS M2NBP-VM CSM: NVIDIA MCP51 */ @@ -2000,6 +2001,7 @@ {0x1106, 0x3189, 0x1043, 0x807F, 0x1106, 0x3177, 0x1043, 0x80A1, NULL, NULL, NULL, P3, "ASUS", "A7V8X-X", 0, OK, it8712f_gpio3_1_raise}, {0x1002, 0x4372, 0x103c, 0x2a26, 0x1002, 0x4377, 0x103c, 0x2a26, NULL, NULL, NULL, P3, "ASUS", "A8AE-LE", 0, OK, amd_sbxxx_gpio9_raise}, {0x8086, 0x27A0, 0x1043, 0x1287, 0x8086, 0x27DF, 0x1043, 0x1287, "^A8J", NULL, NULL, P3, "ASUS", "A8Jm", 0, NT, intel_ich_gpio34_raise}, + {0x10DE, 0x0260, 0x103C, 0x2A34, 0x10DE, 0x0264, 0x103C, 0x2A34, "NODUSM3", NULL, NULL, P3, "ASUS", "A8M2N-LA (NodusM3-GL8E)", 0, OK, nvidia_mcp_gpio0_raise}, {0x10DE, 0x0260, 0x103c, 0x2a3e, 0x10DE, 0x0264, 0x103c, 0x2a3e, "NAGAMI2L", NULL, NULL, P3, "ASUS", "A8N-LA (Nagami-GL8E)", 0, OK, nvidia_mcp_gpio0_raise}, {0x10DE, 0x005E, 0x1043, 0x815A, 0x10DE, 0x0054, 0x1043, 0x815A, "^A8N-SLI DELUXE", NULL, NULL, P3, "ASUS", "A8N-SLI Deluxe", 0, NT, board_shuttle_fn25}, {0x10de, 0x0264, 0x1043, 0x81bc, 0x10de, 0x02f0, 0x1043, 0x81cd, NULL, NULL, NULL, P3, "ASUS", "A8N-VM CSM", 0, OK, w83627ehf_gpio22_raise_2e}, Modified: trunk/chipset_enable.c ============================================================================== --- trunk/chipset_enable.c Sat Aug 6 18:16:45 2011 (r1407) +++ trunk/chipset_enable.c Sun Aug 7 15:17:20 2011 (r1408) @@ -1096,7 +1096,7 @@ {0x10de, 0x00e0, OK, "NVIDIA", "NForce3", enable_flash_nvidia_nforce2}, /* Slave, should not be here, to fix known bug for A01. */ {0x10de, 0x00d3, OK, "NVIDIA", "CK804", enable_flash_ck804}, - {0x10de, 0x0260, NT, "NVIDIA", "MCP51", enable_flash_ck804}, + {0x10de, 0x0260, OK, "NVIDIA", "MCP51", enable_flash_ck804}, {0x10de, 0x0261, NT, "NVIDIA", "MCP51", enable_flash_ck804}, {0x10de, 0x0262, NT, "NVIDIA", "MCP51", enable_flash_ck804}, {0x10de, 0x0263, NT, "NVIDIA", "MCP51", enable_flash_ck804}, Modified: trunk/print.c ============================================================================== --- trunk/print.c Sat Aug 6 18:16:45 2011 (r1407) +++ trunk/print.c Sun Aug 7 15:17:20 2011 (r1408) @@ -420,6 +420,7 @@ B("ASUS", "A7V8X-MX SE", 1, "http://www.asus.com/product.aspx?P_ID=1guVBT1qV5oqhHyZ", NULL), B("ASUS", "A7V8X-X", 1, "http://www.asus.com/product.aspx?P_ID=YcXfRrWHZ9RKoVmw", NULL), B("ASUS", "A8Jm", 1, "http://www.asus.com/product.aspx?P_ID=VztICtOgiU6drx4m", NULL), + B("ASUS", "A8M2N-LA (NodusM3-GL8E)", 1, "http://h10010.www1.hp.com/ewfrf/wc/document?docname=c00757531&cc=us&dlc=en&…", "This is an OEM board from HP, the HP name is NodusM3-GL8E."), B("ASUS", "A8N-E", 1, "http://www.asus.com/product.aspx?P_ID=DzbA8hgqchMBOVRz", NULL), B("ASUS", "A8N-LA (Nagami-GL8E)", 1, "http://h10025.www1.hp.com/ewfrf/wc/document?lc=en&cc=us&docname=c00647121&d…", "This is an OEM board from HP, the HP name is Nagami-GL8E."), B("ASUS", "A8N-SLI", 1, "http://www.asus.com/product.aspx?P_ID=J9FKa8z2xVId3pDK", NULL),

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flashrom support for EP-9NPA7I
by Stefan Tauner 07 Aug '11

07 Aug '11

hello clr! you have missed carl-daniel or vice-versa one time and you never came back after that. i have dug up some info about the predecessor of your board i.e. 8NPA7I. the board enable that was executed on your machine by mistake is not complete (not even for the 8NPA7I) so it is expected to not work for you. i have not reverse engineered your bios (update tool), so i am not sure at all that the attached patch would help and not reboot/ruin/ignite your machine. but if you are brave you can try it. PS: this patch is not for merge, because we have no idea what 0x92 really does imho. but we could incorporate this into a board enable function, if it really works or do you (fellow flashrom dev) think it is ok to just merge it as is? PPS: this is just a port of http://patchwork.coreboot.org/patch/2125/ -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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[PATCH 2/2] Nvidia chipset enables: refactor setting bit 0 in 0x6d
by Stefan Tauner 07 Aug '11

07 Aug '11

This also changes semantics: previously failing to set this was interpreted as error by enable_flash_ck804 and enable_flash_mcp55 although the output indicates otherwise. Also, in enable_flash_nvidia_nforce2 there was no check if settings the bit succeeds. Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> --- chipset_enable.c | 49 ++++++++++++++++++++----------------------------- 1 files changed, 20 insertions(+), 29 deletions(-) diff --git a/chipset_enable.c b/chipset_enable.c index 294007d..03ccaa2 100644 --- a/chipset_enable.c +++ b/chipset_enable.c @@ -784,16 +784,27 @@ static int enable_flash_sb600(struct pci_dev *dev, const char *name) return ret; } -static int enable_flash_nvidia_nforce2(struct pci_dev *dev, const char *name) +/* sets bit 0 in 0x6d */ +static void enable_flash_nvidia_common(struct pci_dev *dev, const char *name) { - uint8_t tmp; + uint8_t old, new; - rpci_write_byte(dev, 0x92, 0); + old = pci_read_byte(dev, 0x6d); + new = old | 0x01; + if (new == old) + return; + rpci_write_byte(dev, 0x6d, new); - tmp = pci_read_byte(dev, 0x6d); - tmp |= 0x01; - rpci_write_byte(dev, 0x6d, tmp); + if (pci_read_byte(dev, 0x6d) != new) { + msg_pinfo("Setting register 0x%x to 0x%x on %s failed " + "(WARNING ONLY).\n", 0x6d, new, name); + } +} +static int enable_flash_nvidia_nforce2(struct pci_dev *dev, const char *name) +{ + rpci_write_byte(dev, 0x92, 0); + enable_flash_nvidia_common(dev, name); return 0; } @@ -859,17 +870,7 @@ ck804_lockbits_done: } } - old = pci_read_byte(dev, 0x6d); - new = old | 0x01; - if (new == old) - return 0; - rpci_write_byte(dev, 0x6d, new); - - if (pci_read_byte(dev, 0x6d) != new) { - msg_pinfo("Setting register 0x%x to 0x%x on %s failed " - "(WARNING ONLY).\n", 0x6d, new, name); - return -1; - } + enable_flash_nvidia_common(dev, name); return 0; } @@ -929,7 +930,7 @@ static int enable_flash_sb400(struct pci_dev *dev, const char *name) static int enable_flash_mcp55(struct pci_dev *dev, const char *name) { - uint8_t old, new, val; + uint8_t val; uint16_t wordval; /* Set the 0-16 MB enable bits. */ @@ -943,17 +944,7 @@ static int enable_flash_mcp55(struct pci_dev *dev, const char *name) wordval |= 0x7fff; /* 16M */ rpci_write_word(dev, 0x90, wordval); - old = pci_read_byte(dev, 0x6d); - new = old | 0x01; - if (new == old) - return 0; - rpci_write_byte(dev, 0x6d, new); - - if (pci_read_byte(dev, 0x6d) != new) { - msg_pinfo("Setting register 0x%x to 0x%x on %s failed " - "(WARNING ONLY).\n", 0x6d, new, name); - return -1; - } + enable_flash_nvidia_common(dev, name); return 0; } -- 1.7.1

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ck804 enable improvement
by Jonathan A. Kollasch 07 Aug '11

07 Aug '11

Hi, Attached is a proposed patch for improving the ck804 chipset enable. Comments? Jonathan Kollasch

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Re: [flashrom] FAILED update new bios but OK to flash OLD bios - P5N-E SLI
by Stefan Tauner 06 Aug '11

06 Aug '11

On Fri, 22 Jul 2011 10:38:45 +0200 Joël Obrecht <joel.obrecht(a)gmail.com> wrote: > Hi Joshua, > I'm sorry I looked a bit around but I guess I need some more explanations > for using / installing that patch. May I have to replace the data in source > files ? Where ? > Anyway, I tried again with last svn, failed again, I joined the verbose > output. > Joël hello joël! i am not entirely sure how your building process works, but you basically need to apply joshua's patch on top of a current source snapshot before compiling it. lets say you have the source in your current working directory. you can then fetch and apply the patch by: wget http://patchwork.coreboot.org/patch/2125/raw/ -O p5ne.patch patch < p5ne.patch after that you have to recompile it. it should print something like "Disabling flash write protection for P5N-E" when run then. it is possible that it does not work yet. please dont reboot if flashrom tells you that and report back (you can get even faster reponses on IRC, if that's an issue btw). -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

1 1

[PATCH] typo
by Sylvain 'ythier' Hitier 06 Aug '11

06 Aug '11

Typo after r1389. Signed-off-by: Sylvain "ythier" Hitier <sylvain.hitier(a)gmail.com> Index: chipset_enable.c =================================================================== --- chipset_enable.c (revision 1405) +++ chipset_enable.c (working copy) @@ -326,7 +326,7 @@ } if (fwh_idsel & 0xffff000000000000ULL) { msg_perr("Error: fwh_idsel= specified, but value had " - "unusued bits set.\n"); + "unused bits set.\n"); goto idsel_garbage_out; } fwh_idsel_old = pci_read_long(dev, 0xd0); Regards, Sylvain "ythier" Hitier -- Business is about being busy, not being rich... Living in a Debian package => http://en.wikipedia.org/wiki/Apt,_Vaucluse

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