flashrom

flashrom@flashrom.org

5 participants
9161 discussions

[PATCH] ft2232_spi: add support for the Dangerous Prototypes Bus Blaster
by Steve Markgraf 12 Aug '11

12 Aug '11

Add support for the Dangerous Prototypes Bus Blaster (v1/v2). The new type is called "busblaster". So far only v2 has been tested, but since both v1 and v2 emulate a Amontec JTAGKEY in the default configuration, it is assumed that v1 should work fine as well. Information about the Busblaster can be found at: http://dangerousprototypes.com/docs/Bus_Blaster Signed-off-by: Steve Markgraf <steve(a)steve-m.de> --- ft2232_spi.c | 8 +++++++- 1 files changed, 7 insertions(+), 1 deletions(-) diff --git a/ft2232_spi.c b/ft2232_spi.c index 689f276..9d35d27 100644 --- a/ft2232_spi.c +++ b/ft2232_spi.c @@ -47,6 +47,7 @@ const struct usbdev_status devs_ft2232spi[] = { {FTDI_VID, FTDI_FT2232H_PID, OK, "FTDI", "FT2232H"}, {FTDI_VID, FTDI_FT4232H_PID, OK, "FTDI", "FT4232H"}, + {FTDI_VID, FTDI_FT2232H_PID, OK, "FTDI", "Dual RS232-HS"}, {FTDI_VID, AMONTEC_JTAGKEY_PID, OK, "Amontec", "JTAGkey"}, {FIC_VID, OPENMOKO_DBGBOARD_PID, OK, "FIC", "OpenMoko Neo1973 Debug board (V2+)"}, @@ -168,7 +169,12 @@ int ft2232_spi_init(void) ft2232_type = FTDI_FT2232H_PID; else if (!strcasecmp(arg, "4232H")) ft2232_type = FTDI_FT4232H_PID; - else if (!strcasecmp(arg, "jtagkey")) { + else if (!strcasecmp(arg, "busblaster")) { + ft2232_type = FTDI_FT2232H_PID; + ft2232_interface = INTERFACE_A; + cs_bits = 0x18; /* is a jtagkey clone in its */ + pindir = 0x1b; /* default configuration */ + } else if (!strcasecmp(arg, "jtagkey")) { ft2232_type = AMONTEC_JTAGKEY_PID; ft2232_interface = INTERFACE_A; cs_bits = 0x18; -- 1.7.4.1

2 2

[commit] r1412 - trunk
by repository service 12 Aug '11

12 Aug '11

Author: stefanct Date: Fri Aug 12 03:19:32 2011 New Revision: 1412 URL: http://flashrom.org/trac/flashrom/changeset/1412 Log: ft2232_spi: add support for the Dangerous Prototypes Bus Blaster Add support for the Dangerous Prototypes Bus Blaster (v1/v2). The new model is called "busblaster". So far only v2 has been tested, but since both v1 and v2 emulate a Amontec JTAGKEY in the default configuration, it is assumed that v1 should work fine as well. Information about the Busblaster can be found at: http://dangerousprototypes.com/docs/Bus_Blaster Signed-off-by: Steve Markgraf <steve(a)steve-m.de> Acked-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Modified: trunk/flashrom.8 trunk/ft2232_spi.c Modified: trunk/flashrom.8 ============================================================================== --- trunk/flashrom.8 Thu Aug 11 07:47:32 2011 (r1411) +++ trunk/flashrom.8 Fri Aug 12 03:19:32 2011 (r1412) @@ -198,8 +198,8 @@ .BR "* ft2232_spi" " (for SPI flash ROMs attached to an FT2232/FT4232H family \ based USB SPI programmer), including the DLP Design DLP-USB1232H, \ FTDI FT2232H Mini-Module, FTDI FT4232H Mini-Module, openbiosprog-spi, Amontec \ -JTAGkey/JTAGkey-tiny/JTAGkey-2, Olimex ARM-USB-TINY/-H, and Olimex \ -ARM-USB-OCD/-H." +JTAGkey/JTAGkey-tiny/JTAGkey-2, Dangerous Prototypes Bus Blaster, \ +Olimex ARM-USB-TINY/-H, and Olimex ARM-USB-OCD/-H." .sp .BR "* serprog" " (for flash ROMs attached to a programmer speaking serprog), \ including AVR flasher by Urja Rannikko, AVR flasher by eightdot, \ @@ -440,8 +440,8 @@ syntax where .B model can be -.BR 2232H ", " 4232H ", " jtagkey ", " openmoko ", " arm-usb-tiny ", " \ -arm-usb-tiny-h ", " arm-usb-ocd " or " arm-usb-ocd-h +.BR 2232H ", " 4232H ", " jtagkey ", " busblaster ", " openmoko ", " \ +arm-usb-tiny ", " arm-usb-tiny-h ", " arm-usb-ocd " or " arm-usb-ocd-h and .B interface can be Modified: trunk/ft2232_spi.c ============================================================================== --- trunk/ft2232_spi.c Thu Aug 11 07:47:32 2011 (r1411) +++ trunk/ft2232_spi.c Fri Aug 12 03:19:32 2011 (r1412) @@ -173,6 +173,12 @@ ft2232_interface = INTERFACE_A; cs_bits = 0x18; pindir = 0x1b; + } else if (!strcasecmp(arg, "busblaster")) { + /* In its default configuration it is a jtagkey clone */ + ft2232_type = FTDI_FT2232H_PID; + ft2232_interface = INTERFACE_A; + cs_bits = 0x18; + pindir = 0x1b; } else if (!strcasecmp(arg, "openmoko")) { ft2232_vid = FIC_VID; ft2232_type = OPENMOKO_DBGBOARD_PID;

1 0

Problems with flashrom
by Benjamin Z. Gregorian 11 Aug '11

11 Aug '11

Hi Guys I run into trouble using flashrom. first I downloaded the ROM to flash then I downloaded flashrom and run the following command ---------- sudo flashrom ---------- Result: flashrom v0.9.1-r946 No coreboot table found. Found chipset "Intel ICH7/ICH7R", enabling flash write... OK. This chipset supports the following protocols: FWH. Calibrating delay loop... OK. Found chip "SST SST49LF004A/B" (512 KB, FWH) at physical address 0xfff80000. No operations were specified. --------- I assumed that flashrom can burn my BIOS (since there was no warning given) Then I tried --------- sudo flashrom -wv Desktop/Downloads/P5LD2-2002.ROM --------- Result was that two opperations are not permittet or so After studying the man page I ran the following command --------- sudo flashrom -w Desktop/Downloads/P5LD2-2002.ROM --------- and got panic!!!!!!! -------- flashrom v0.9.1-r946 No coreboot table found. Found chipset "Intel ICH7/ICH7R", enabling flash write... OK. This chipset supports the following protocols: FWH. Calibrating delay loop... OK. Found chip "SST SST49LF004A/B" (512 KB, FWH) at physical address 0xfff80000. Flash image seems to be a legacy BIOS. Disabling checks. Writing flash chip... Erasing flash chip... ERASE FAILED at 0x000002c8! Expected=0xff, Read=0x4c, failed byte count from 0x00000000-0x00000fff: 0xd12 ERASE FAILED! ERASE FAILED at 0x000002c8! Expected=0xff, Read=0x4c, failed byte count from 0x00000000-0x0000ffff: 0xfc2b ERASE FAILED! FAILED! ERASE FAILED! FAILED! Your flash chip is in an unknown state. Get help on IRC at irc.freenode.net (channel #flashrom) or mail flashrom(a)flashrom.org! ------------------------------------------------------------------------------- DO NOT REBOOT OR POWEROFF! ----------------------------------- PLEASE ADVICE what to do next. LOOKING EAGERLY FORWARD to YOUR REPLY Regards Benjamin -- Neu: GMX De-Mail - Einfach wie E-Mail, sicher wie ein Brief! Jetzt De-Mail-Adresse reservieren: http://portal.gmx.net/de/go/demail

5 6

Re: [flashrom] flashrom -V
by Melchior FRANZ 11 Aug '11

11 Aug '11

* Daniel Housar -- Wednesday 10 August 2011: > MainBoard: MSI K9N Neo V2 (K9N Neo-F V2) > flashrom v0.9.4-r1395 I have the same board, and I flashed it successfully with v0.9.3-r1370 about a month ago (-> BIOS v2.9). After booting it first seemed to have gone wrong: early in the boot phase the BIOS rebooted, and I was in an endless loop. I couldn't go into the setup, and I couldn't even read the error message. So I recorded a film with my mobile's cam, and wanted to watch it in slow motion to decipher the message. But in the meantime the BIOS had stopped rebooting and showed a prompt. Unfortunately I didn't note down the text, but after confirming everything went fine. I guess I should have: - reset my BIOS to factory default/"optimal" settings before flashing (Maybe some of the custom settings didn't work well with the new BIOS? Though one would assume that they get reset anyway.) - gone into single-user mode for flashing, with as few apps running as possible (some of them froze, and KDE decided to forget some of my settings) But again, apart from this little adventure everything worked fine. m.

1 0

[commit] r1411 - trunk
by repository service 11 Aug '11

11 Aug '11

Author: stefanct Date: Thu Aug 11 07:47:32 2011 New Revision: 1411 URL: http://flashrom.org/trac/flashrom/changeset/1411 Log: Add board enable for ASUS P5GD2 Premium This is based on Joshua's patch, but with a DMI pattern, contrary to http://www.flashrom.org/pipermail/flashrom/2010-September/004745.html Rationale: although it looks like all P5GD2/C* might use the same board enable (intel_ich_gpio21_raise), we need to add the variants individually as long as we don't have enough reports to make a better guess. This also guarantees correct output of flashrom -L and -z and on activation of the board enable - not like this: http://www.flashrom.org/pipermail/flashrom/attachments/20100930/2286e5d1/at… Success report: http://www.flashrom.org/pipermail/flashrom/2010-August/004555.html Also, fix last commit by adding a missing comma. Tested-by: Roberto Malinverni Signed-off-by: Joshua Roys <roysjosh(a)gmail.com> Acked-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Modified: trunk/board_enable.c trunk/print.c Modified: trunk/board_enable.c ============================================================================== --- trunk/board_enable.c Thu Aug 11 06:21:34 2011 (r1410) +++ trunk/board_enable.c Thu Aug 11 07:47:32 2011 (r1411) @@ -1494,6 +1494,7 @@ * - ASUS P4P800-E Deluxe: Intel socket478 + 865PE + ICH5R * - ASUS P4P800-VM: Intel socket478 + 865PE + ICH5R * - ASUS P5GD1 Pro: Intel LGA 775 + 915P + ICH6R + * - ASUS P5GD2 Premium: Intel LGA775 + 915G + ICH6R * - ASUS P5GDC Deluxe: Intel socket775 + 915P + ICH6R * - ASUS P5PE-VM: Intel LGA775 + 865G + ICH5 * - Samsung Polaris 32: socket478 + 865P + ICH5 @@ -2022,8 +2023,9 @@ {0x1039, 0x0661, 0x1043, 0x8113, 0x1039, 0x5513, 0x1043, 0x8087, NULL, NULL, NULL, P3, "ASUS", "P4S800-MX", 512, OK, w836xx_memw_enable_2e}, {0x10B9, 0x1541, 0, 0, 0x10B9, 0x1533, 0, 0, "^P5A$", "asus", "p5a", P3, "ASUS", "P5A", 0, OK, board_asus_p5a}, {0x8086, 0x266a, 0x1043, 0x80a6, 0x8086, 0x2668, 0x1043, 0x814e, NULL, NULL, NULL, P3, "ASUS", "P5GD1 Pro", 0, OK, intel_ich_gpio21_raise}, + {0x8086, 0x266a, 0x1043, 0x80a6, 0x8086, 0x2668, 0x1043, 0x813d, "^P5GD2-Premium$", NULL, NULL, P3, "ASUS", "P5GD2 Premium", 0, OK, intel_ich_gpio21_raise}, {0x8086, 0x266a, 0x1043, 0x80a6, 0x8086, 0x2668, 0x1043, 0x813d, NULL, NULL, NULL, P3, "ASUS", "P5GDC Deluxe", 0, OK, intel_ich_gpio21_raise}, - {0x8086, 0x27da, 0x1043, 0x8179, 0x8086, 0x27b8 0x1043, 0x8179, "^P5LD2$", NULL, NULL, P3, "ASUS", "P5LD2", 0, NT, intel_ich_gpio16_raise}, + {0x8086, 0x27da, 0x1043, 0x8179, 0x8086, 0x27b8, 0x1043, 0x8179, "^P5LD2$", NULL, NULL, P3, "ASUS", "P5LD2", 0, NT, intel_ich_gpio16_raise}, {0x10DE, 0x0030, 0x1043, 0x818a, 0x8086, 0x100E, 0x1043, 0x80EE, NULL, NULL, NULL, P3, "ASUS", "P5ND2-SLI Deluxe", 0, OK, nvidia_mcp_gpio10_raise}, {0x8086, 0x24dd, 0x1043, 0x80a6, 0x8086, 0x2570, 0x1043, 0x8157, NULL, NULL, NULL, P3, "ASUS", "P5PE-VM", 0, OK, intel_ich_gpio21_raise}, {0x10b7, 0x9055, 0x1028, 0x0082, 0x8086, 0x7190, 0, 0, NULL, NULL, NULL, P3, "Dell", "OptiPlex GX1", 0, OK, intel_piix4_gpo30_lower}, Modified: trunk/print.c ============================================================================== --- trunk/print.c Thu Aug 11 06:21:34 2011 (r1410) +++ trunk/print.c Thu Aug 11 07:47:32 2011 (r1411) @@ -479,6 +479,7 @@ B("ASUS", "P5B-Deluxe", 1, "http://www.asus.com/product.aspx?P_ID=bswT66IBSb2rEWNa", NULL), B("ASUS", "P5BV-M", 0, "ftp://ftp.asus.com.tw/pub/ASUS/mb/socket775/P5B-VM/", "Reported by Bernhard M. Wiedemann <bernhard(a)uml12d.zq1.de> to flashrom(a)coreboot.org, no public archive. Missing board enable and/or SST49LF008A unlocking. May work now."), B("ASUS", "P5GC-MX/1333", 1, "http://www.asus.com/product.aspx?P_ID=PYvbfOokwxUzJky3", NULL), + B("ASUS", "P5GD2 Premium", 1, "http://www.asus.it/product.aspx?P_ID=lRKaz1Rb6Xb0OFM7", NULL), B("ASUS", "P5GDC Deluxe", 1, "http://www.asus.com/product.aspx?P_ID=AbeoopyNpI2TZixg", NULL), B("ASUS", "P5KC", 1, "http://www.asus.com/product.aspx?P_ID=fFZ8oUIGmLpwNMjj", NULL), B("ASUS", "P5L-MX", 1, "http://www.asus.com/product.aspx?P_ID=X70d3NCzH2DE9vWH", NULL),

1 0

[commit] r1410 - trunk
by repository service 11 Aug '11

11 Aug '11

Author: stefanct Date: Thu Aug 11 06:21:34 2011 New Revision: 1410 URL: http://flashrom.org/trac/flashrom/changeset/1410 Log: Add (untested) board enable for Asus P5LD2 There are numerous other variants of the P5LD2 which vary wildly not only in PCB layout but also in northbridges used, number of PCI, PCI-E and DIMM slots etc. This one is for the plain P5LD2 without any suffixes. This patch is essentially a rebased version of Joshua's patch, which was never tested (user did not reply). I have added additional PCI IDs and the DMI pattern and also changed the status to NT. An entry in the print.c table was also added. http://www.flashrom.org/pipermail/flashrom/2010-October/005080.html Signed-off-by: Joshua Roys <roysjosh(a)gmail.com> Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Modified: trunk/board_enable.c trunk/print.c Modified: trunk/board_enable.c ============================================================================== --- trunk/board_enable.c Tue Aug 9 03:49:34 2011 (r1409) +++ trunk/board_enable.c Thu Aug 11 06:21:34 2011 (r1410) @@ -1461,6 +1461,7 @@ * Suited for: * - abit IP35: Intel P35 + ICH9R * - abit IP35 Pro: Intel P35 + ICH9R + * - ASUS P5LD2 */ static int intel_ich_gpio16_raise(void) { @@ -2022,6 +2023,7 @@ {0x10B9, 0x1541, 0, 0, 0x10B9, 0x1533, 0, 0, "^P5A$", "asus", "p5a", P3, "ASUS", "P5A", 0, OK, board_asus_p5a}, {0x8086, 0x266a, 0x1043, 0x80a6, 0x8086, 0x2668, 0x1043, 0x814e, NULL, NULL, NULL, P3, "ASUS", "P5GD1 Pro", 0, OK, intel_ich_gpio21_raise}, {0x8086, 0x266a, 0x1043, 0x80a6, 0x8086, 0x2668, 0x1043, 0x813d, NULL, NULL, NULL, P3, "ASUS", "P5GDC Deluxe", 0, OK, intel_ich_gpio21_raise}, + {0x8086, 0x27da, 0x1043, 0x8179, 0x8086, 0x27b8 0x1043, 0x8179, "^P5LD2$", NULL, NULL, P3, "ASUS", "P5LD2", 0, NT, intel_ich_gpio16_raise}, {0x10DE, 0x0030, 0x1043, 0x818a, 0x8086, 0x100E, 0x1043, 0x80EE, NULL, NULL, NULL, P3, "ASUS", "P5ND2-SLI Deluxe", 0, OK, nvidia_mcp_gpio10_raise}, {0x8086, 0x24dd, 0x1043, 0x80a6, 0x8086, 0x2570, 0x1043, 0x8157, NULL, NULL, NULL, P3, "ASUS", "P5PE-VM", 0, OK, intel_ich_gpio21_raise}, {0x10b7, 0x9055, 0x1028, 0x0082, 0x8086, 0x7190, 0, 0, NULL, NULL, NULL, P3, "Dell", "OptiPlex GX1", 0, OK, intel_piix4_gpo30_lower}, Modified: trunk/print.c ============================================================================== --- trunk/print.c Tue Aug 9 03:49:34 2011 (r1409) +++ trunk/print.c Thu Aug 11 06:21:34 2011 (r1410) @@ -482,6 +482,7 @@ B("ASUS", "P5GDC Deluxe", 1, "http://www.asus.com/product.aspx?P_ID=AbeoopyNpI2TZixg", NULL), B("ASUS", "P5KC", 1, "http://www.asus.com/product.aspx?P_ID=fFZ8oUIGmLpwNMjj", NULL), B("ASUS", "P5L-MX", 1, "http://www.asus.com/product.aspx?P_ID=X70d3NCzH2DE9vWH", NULL), + B("ASUS", "P5LD2", 0, NULL, "Untested board enable."), B("ASUS", "P5GD1 Pro", 1, "http://www.asus.com/product.aspx?P_ID=50M49xQh71EZOeM1", NULL), B("ASUS", "P5N-E SLI", 0, "http://www.asus.com/product.aspx?P_ID=KyHOsOKWujC2QguJ", "Needs a board enable (http://patchwork.coreboot.org/patch/3298/)."), B("ASUS", "P5N32-E SLI", 1, "http://www.asus.com/product.aspx?P_ID=vBZLIBtPzYB2bLcb", NULL),

1 0

[PATCH] add support for AT49F040
by David Borg 11 Aug '11

11 Aug '11

Hi, I was adding support for the AT49F040 parallel flash chip, but have some questions. This chip has a boot block which once locked cannot be erased / rewritten. Should I add erase functions for both cases? Currently the erase function handles unlocked chips only. In addition, the datasheet specifies no command timings, is the timing something I can infer from the read / program cycle characteristics tables? Regards, David Signed-off-by: David Borg <borg.db(a)gmail.com> datasheet: http://pdf1.alldatasheet.com/datasheet-pdf/view/56184/ATMEL/AT49F040.html Index: flashchips.c =================================================================== --- flashchips.c (revision 1145) +++ flashchips.c (working copy) @@ -1985,6 +1985,29 @@ }, { + .vendor = "Atmel", + .name = "AT49F040", + .bustype = CHIP_BUSTYPE_PARALLEL, + .manufacture_id = ATMEL_ID, + .model_id = AT_49F040, + .total_size = 512, + .page_size = 512, + .feature_bits = FEATURE_EITHER_RESET | FEATURE_ADDR_FULL, + .tested = TEST_UNTESTED, + .probe = probe_jedec, + .probe_timing = TIMING_ZERO, /* Datasheet has no timing info specified */ + .block_erasers = + { + { + .eraseblocks = { {512 * 1024, 1} }, + .block_erase = erase_chip_block_jedec, + } + }, + .write = write_jedec_1, + .read = read_memmapped, + }, + + { .vendor = "EMST", .name = "F49B002UA", .bustype = CHIP_BUSTYPE_PARALLEL, Index: flashchips.h =================================================================== --- flashchips.h (revision 1145) +++ flashchips.h (working copy) @@ -174,6 +174,7 @@ #define AT_49F020 0x0B #define AT_49F002N 0x07 /* for AT49F002(N) */ #define AT_49F002NT 0x08 /* for AT49F002(N)T */ +#define AT_49F040 0x13 #define CATALYST_ID 0x31 /* Catalyst */

3 2

flashrom -V
by Daniel Housar 10 Aug '11

10 Aug '11

MainBoard: MSI K9N Neo V2 (K9N Neo-F V2) NVIDIA nForce 520 (MCP65), socket AM2 (AMD Athlon64/X2) flashrom v0.9.4-r1395 on Linux 3.0.0+ (x86_64), built with libpci 3.1.7, GCC 4.6.1, little endian flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OS timer resolution is 1 usecs, 655M loops per second, 10 myus = 10 us, 100 myus = 99 us, 1000 myus = 990 us, 10000 myus = 10339 us, 4 myus = 4 us, OK. Initializing internal programmer No coreboot table found. DMI string system-manufacturer: "MSI" DMI string system-product-name: "MS-7369" DMI string system-version: "1.0" DMI string baseboard-manufacturer: "MSI" DMI string baseboard-product-name: "MS-7369" DMI string baseboard-version: "1.0" DMI string chassis-type: "Desktop" Found chipset "NVIDIA MCP65" with PCI ID 10de:0441. This chipset is marked as untested. If you are using an up-to-date version of flashrom please email a report to flashrom(a)flashrom.org including a verbose (-V) log. Thank you! Enabling flash write... This chipset is not really supported yet. Guesswork... ISA/LPC bridge reg 0x8a contents: 0x40, bit 6 is 1, bit 5 is 0 Flash bus type is SPI SPI on this chipset is WIP. Please report any success or failure by mailing us the verbose output to flashrom(a)flashrom.org, thanks! Found SMBus device 10de:0446 at 00:01:1 MCP SPI BAR is at 0xfec80000 Mapping NVIDIA MCP6x SPI at 0xfec80000, unaligned size 0x544. SPI control is 0x0002, req=0, gnt=0 Please send the output of "flashrom -V" to flashrom(a)flashrom.org with your board name: flashrom -V as the subject to help us finish support for your chipset. Thanks. OK. This chipset supports the following protocols: SPI. Probing for AMIC A25L05PT, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L05PU, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L10PT, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L10PU, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L20PT, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L20PU, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L40PT, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L40PU, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L80P, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L16PT, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L16PU, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L512, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L010, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L020, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L040, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L080, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L016, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L032, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25LQ032, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT25DF021, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT25DF041A, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT25DF081, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT25DF081A, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT25DF161, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT25DF321, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT25DF321A, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT25DF641, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT25DQ161, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT25F512B, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT25FS010, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT25FS040, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT26DF041, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT26DF081A, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT26DF161, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT26DF161A, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT26F004, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT45CS1282, 16896 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT45DB011D, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT45DB021D, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT45DB041D, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT45DB081D, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT45DB161D, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT45DB321C, 4224 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT45DB321D, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT45DB642D, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for EMST F25L008A, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B05, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B05T, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B10, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B10T, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B20, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B20T, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B40, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B40T, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B80, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B80T, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B16T, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B32, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B32T, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B64, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B64T, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25F05, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25F10, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25F20, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25F40, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25F80, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25F16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25F32, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25Q40, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25Q80(A), 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25Q16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25Q32(A/B), 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25Q64, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25Q128, 16384 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25QH16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Macronix MX25L512, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Macronix MX25L1005, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Macronix MX25L2005, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Macronix MX25L4005, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Macronix MX25L8005, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Chip status register is 00 Chip status register: Status Register Write Disable (SRWD) is not set Chip status register: Bit 6 is not set Chip status register: Bit 5 / Block Protect 3 (BP3) is not set Chip status register: Bit 4 / Block Protect 2 (BP2) is not set Chip status register: Bit 3 / Block Protect 1 (BP1) is not set Chip status register: Bit 2 / Block Protect 0 (BP0) is not set Chip status register: Write Enable Latch (WEL) is not set Chip status register: Write In Progress (WIP/BUSY) is not set Found Macronix flash chip "MX25L8005" (1024 kB, SPI) at physical address 0xfff00000. Probing for Macronix MX25L1605, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Macronix MX25L1635D, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Macronix MX25L1635E, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Macronix MX25L3205, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Macronix MX25L3235D, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Macronix MX25L6405, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Macronix MX25L12805, 16384 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Numonyx M25PE10, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Numonyx M25PE20, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Numonyx M25PE40, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Numonyx M25PE80, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Numonyx M25PE16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for PMC Pm25LV010, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for PMC Pm25LV016B, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for PMC Pm25LV020, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for PMC Pm25LV040, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for PMC Pm25LV080B, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for PMC Pm25LV512, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Sanyo LF25FW203A, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Spansion S25FL004A, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Spansion S25FL008A, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Spansion S25FL016A, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Spansion S25FL032A, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Spansion S25FL064A, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for SST SST25VF010.REMS, 128 kB: probe_spi_rems: id1 0xc2, id2 0x13 Probing for SST SST25VF016B, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for SST SST25VF032B, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for SST SST25VF064C, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for SST SST25VF040.REMS, 512 kB: probe_spi_rems: id1 0xc2, id2 0x13 Probing for SST SST25VF040B, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for SST SST25LF040A.RES, 512 kB: probe_spi_res2: id1 0x13, id2 0x13 Probing for SST SST25VF040B.REMS, 512 kB: probe_spi_rems: id1 0xc2, id2 0x13 Probing for SST SST25VF080B, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for ST M25P05-A, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for ST M25P05.RES, 64 kB: Ignoring RES in favour of RDID. Probing for ST M25P10-A, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for ST M25P10.RES, 128 kB: Ignoring RES in favour of RDID. Probing for ST M25P20, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for ST M25P40, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for ST M25P40-old, 512 kB: Ignoring RES in favour of RDID. Probing for ST M25P80, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for ST M25P16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for ST M25P32, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for ST M25P64, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for ST M25P128, 16384 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for ST M25PX16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for ST M25PX32, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for ST M25PX64, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Winbond W25Q80, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Winbond W25Q16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Winbond W25Q32, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Winbond W25Q64, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Winbond W25Q128, 16384 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Winbond W25X10, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Winbond W25X20, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Winbond W25X40, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Winbond W25X80, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Winbond W25X16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Winbond W25X32, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Winbond W25X64, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC unknown AMIC SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel unknown Atmel SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon unknown Eon SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Macronix unknown Macronix SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for PMC unknown PMC SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for SST unknown SST SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for ST unknown ST SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Sanyo unknown Sanyo SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Generic unknown SPI chip (RDID), 0 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Generic unknown SPI chip (REMS), 0 kB: probe_spi_rems: id1 0xc2, id2 0x13 No operations were specified.

1 0

Re: [flashrom] [PATCH 2/4] add ICH/PCH flash descriptor decoding via FDOC/FDOD
by Carl-Daniel Hailfinger 09 Aug '11

09 Aug '11

Am 21.07.2011 01:24 schrieb Stefan Tauner: > based on the work of Matthias 'mazzoo' Wenzel this patch adds pretty > printing of those ICH/PCH flash descriptors that are cached/mapped > by the chipset (and which are therefore reachable via FDOC/FDOD > registers). > > this includes the following: > - content descriptor: > describes the image and some generic properties (number of regions, > offset of regions, offset of which regions, or something else? How does this relate to region descriptor(s)? > PCH/ICH and MCH/PROC strap offsets and lengths) > - component descriptor: > identify the different SPI Flash Components and their capabilities. > components==chips? If yes, please say so in the changelog (and maybe code comments). > - region descriptor > similarly to a partition table this describes the different regions > One common descriptor for all regions or one descriptor per region? > - master descriptor > defines access rights of the individual regions > > this is only a part of the data included in the descriptor. other > information can be retreived retrieved > from a complete binary dump of the descriptor image only. > What's a descriptor image? > this patch also adds macros and pretty printing for "Vendor Specific > Component Capabilities" registers: > there are two of them: lower and upper. they describe the properties > of the address space divided by FPBA We really need some place (maybe as comment in ich_decriptor.h?) where all Intel acronyms are expanded and explained. > (which allows to use multiple > flash chips or partitions with different properties). the properties > of flash chips supported by the ME are stored in the same format in > a descriptor table. "a descriptor table" implies there is more than one. Which one is it? > a later patch will uses them outside of ichspi.c > which is also the reason why the prettyprinting function and the > register bit macros are not defined in ichspi.c but ich_descriptors.h. > > TODO: > - file naming and partitioning was not discussed. we may want a ichspi.h. > and/or rename ichspi.c to ich_spi.c or similar... > I'd say naming of the files is the least of our worries. We'll reorganize all flashrom code in a directory structure anyway, and that's when we can rename files if needed. > - straps of ich8 (only) Why not ICH7 (no descriptors?) or ICH9 and later (no datasheets?) > could be printed at runtime via FDOC/FDOD. > worth it? no, imo. Agreed. > but reading out the descriptor region manually and > parsing it with the following patch may be useful? > following patch == 3/4? Once we support true partial reads with the help of layout files, this should be possible. > Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> > Please note that I didn't check the code for correctness against the datasheets nor did I check the code flow. The comments below are what I noticed from reading the patch alone. The message levels of most messages really need to be discussed... a flood of msg_dbg is not necessarily a good idea, downgrading a lot of them to dbg2 may improve said flood. That said, msg_[cpg]dbg2 is now in the tree, so the dbg1 hack can go away. Looking again at your messagelevels, maybe dbg1->dbg2 and dbg2->spew would be in order. All ich specific structs should have an ich_ prefix in the struct name to avoid polluting the global namespace. > --- > Makefile | 3 +- > ich_descriptors.c | 247 +++++++++++++++++++++++++++++++++++++++++++++++++ > ich_descriptors.h | 264 +++++++++++++++++++++++++++++++++++++++++++++++++++++ > ichspi.c | 39 ++++++-- > 4 files changed, 544 insertions(+), 9 deletions(-) > create mode 100644 ich_descriptors.c > create mode 100644 ich_descriptors.h > > diff --git a/Makefile b/Makefile > index a35df06..7f73452 100644 > --- a/Makefile > +++ b/Makefile > @@ -308,7 +308,8 @@ ifeq ($(CONFIG_INTERNAL), yes) > FEATURE_CFLAGS += -D'CONFIG_INTERNAL=1' > PROGRAMMER_OBJS += processor_enable.o chipset_enable.o board_enable.o cbtable.o dmi.o internal.o > ifeq ($(ARCH),"x86") > -PROGRAMMER_OBJS += it87spi.o it85spi.o ichspi.o sb600spi.o wbsio_spi.o mcp6x_spi.o > +PROGRAMMER_OBJS += it87spi.o it85spi.o sb600spi.o wbsio_spi.o mcp6x_spi.o > +PROGRAMMER_OBJS += ichspi.o ich_descriptors.o > else > endif > NEED_PCI := yes > diff --git a/ich_descriptors.c b/ich_descriptors.c > new file mode 100644 > index 0000000..cf77601 > --- /dev/null > +++ b/ich_descriptors.c > @@ -0,0 +1,247 @@ > +/* > + * This file is part of the flashrom project. > + * > + * Copyright (c) 2010 Matthias Wenzel <bios at mazzoo dot de> > + * Copyright (c) 2011 Stefan Tauner > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License as published by > + * the Free Software Foundation; either version 2 of the License, or > + * (at your option) any later version. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + * You should have received a copy of the GNU General Public License > + * along with this program; if not, write to the Free Software > + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA > + */ > + > +#if defined(__i386__) || defined(__x86_64__) > + > +#include "ich_descriptors.h" > +#include "flash.h" /* for msg_* */ > + > +#define getFCBA(cont) (((cont)->FLMAP0 << 4) & 0x00000ff0) > +#define getFRBA(cont) (((cont)->FLMAP0 >> 12) & 0x00000ff0) > +#define getFMBA(cont) (((cont)->FLMAP1 << 4) & 0x00000ff0) > +#define getFISBA(cont) (((cont)->FLMAP1 >> 12) & 0x00000ff0) > +#define getFMSBA(cont) (((cont)->FLMAP2 << 4) & 0x00000ff0) > + > +void prettyprint_ich_descriptors(enum chipset cs, const struct flash_descriptors *desc) > (enum ich_chipset cs, const struct ich_flash_descriptors *desc) > +{ > Please try to handle cs at least somewhat. Check if it has the expected value, and skip descriptor decoding (with a dbg/dbg2 message telling the user about it) if the result would be wrong (i.e. for the wrong ICH family). > + prettyprint_ich_descriptor_content(&desc->content); > + prettyprint_ich_descriptor_component(desc); > + prettyprint_ich_descriptor_region(&desc->region); > + prettyprint_ich_descriptor_master(&desc->master); > +} > + > +void prettyprint_ich_descriptor_content(const struct flash_content *cont) > ich_flash_content Does this work on all chipsets? > +{ > + msg_pdbg1("=== Content Section ===\n"); > + msg_pdbg1("FLVALSIG 0x%08x\n", cont->FLVALSIG); > + msg_pdbg1("FLMAP0 0x%08x\n", cont->FLMAP0); > + msg_pdbg1("FLMAP1 0x%08x\n", cont->FLMAP1); > + msg_pdbg1("FLMAP2 0x%08x\n", cont->FLMAP2); > + msg_pdbg1("\n"); > dbg1->dbg, or maybe ->dbg2 to reduce output. The message level discussion should not hold back this patch. > + > + msg_pdbg2("--- Details ---\n"); > + msg_pdbg2("NR (Number of Regions): %5d\n", > + cont->NR + 1); > + msg_pdbg2("FRBA (Flash Region Base Address): 0x%03x\n", > + getFRBA(cont)); > + msg_pdbg2("NC (Number of Components): %5d\n", > + cont->NC + 1); > + msg_pdbg2("FCBA (Flash Component Base Address): 0x%03x\n", > + getFCBA(cont)); > + msg_pdbg2("ISL (ICH/PCH Strap Length): %5d\n", > + cont->ISL); > + msg_pdbg2("FISBA/FPSBA (Flash ICH/PCH Strap Base Address): 0x%03x\n", > + getFISBA(cont)); > + msg_pdbg2("NM (Number of Masters): %5d\n", > + cont->NM + 1); > + msg_pdbg2("FMBA (Flash Master Base Address): 0x%03x\n", > + getFMBA(cont)); > + msg_pdbg2("MSL/PSL (MCH/PROC Strap Length): %5d\n", > + cont->MSL); > + msg_pdbg2("FMSBA (Flash MCH/PROC Strap Base Address): 0x%03x\n", > + getFMSBA(cont)); > + msg_pdbg2("\n"); > +} > + > +void prettyprint_ich_descriptor_component(const struct flash_descriptors *desc) > ich_flash_descriptors Which chipset is handled by this function? > +{ > + const char * const str_freq[8] = { > static? Or is that useless here? > + "20 MHz", /* 000 */ > + "33 MHz", /* 001 */ > + "reserved", /* 010 */ > + "reserved", /* 011 */ > + "50 MHz", /* 100 */ > Mh. Is 50 MHz available on all descriptor capable chipsets? > + "reserved", /* 101 */ > + "reserved", /* 110 */ > + "reserved" /* 111 */ > + }; > + const char * const str_mem[8] = { > static? > + "512 kB", /* 000 */ > + " 1 MB", /* 001 */ > + " 2 MB", /* 010 */ > + " 4 MB", /* 011 */ > + " 8 MB", /* 100 */ > + " 16 MB", /* 101 */ > + "reserved", /* 110 */ > + "reserved", /* 111 */ > + }; > + > + msg_pdbg1("=== Component Section ===\n"); > + msg_pdbg1("FLCOMP 0x%08x\n", desc->component.FLCOMP); > + msg_pdbg1("FLILL 0x%08x\n", desc->component.FLILL ); > + msg_pdbg1("\n"); > + > + msg_pdbg2("--- Details ---\n"); > + msg_pdbg2("Component 1 density: %s\n", > + str_mem[desc->component.comp1_density]); > + if (desc->content.NC) > + msg_pdbg2("Component 2 density: %s\n", > + str_mem[desc->component.comp2_density]); > + else > + msg_pdbg2("Component 2 is not used.\n"); > + msg_pdbg2("Read Clock Frequency: %s\n", > + str_freq[desc->component.freq_read]); > + msg_pdbg2("Read ID and Status Clock Freq.: %s\n", > + str_freq[desc->component.freq_read_id]); > + msg_pdbg2("Write and Erase Clock Freq.: %s\n", > + str_freq[desc->component.freq_write]); > + msg_pdbg2("Fast Read is %ssupported.\n", > + desc->component.fastread ? "" : "not "); > + if (desc->component.fastread) > + msg_pdbg2("Fast Read Clock Frequency: %s\n", > + str_freq[desc->component.freq_fastread]); > + if (desc->component.FLILL == 0) > + msg_pdbg2("No forbidden opcodes.\n"); > + else { > + msg_pdbg2("Invalid instruction 0: 0x%02x\n", > + desc->component.invalid_instr0); > + msg_pdbg2("Invalid instruction 1: 0x%02x\n", > + desc->component.invalid_instr1); > + msg_pdbg2("Invalid instruction 2: 0x%02x\n", > + desc->component.invalid_instr2); > + msg_pdbg2("Invalid instruction 3: 0x%02x\n", > + desc->component.invalid_instr3); > + } > + msg_pdbg2("\n"); > +} > + > +static void pprint_freg(const struct flash_region *reg, uint32_t i) > ich_flash_region Which chipset? Or is the code generic? > +{ > + const char *const region_names[5] = { > + "Descr.", "BIOS", "ME", "GbE", "Platf." > + }; > + uint32_t base = ICH_FREG_BASE(reg->FLREGs[i]); > + uint32_t limit = ICH_FREG_LIMIT(reg->FLREGs[i]); > + msg_pdbg2("Region %d (%-6s) ", i, region_names[i]); > + if (base > limit) > + msg_pdbg2("is unused.\n"); > + else > + msg_pdbg2("0x%08x - 0x%08x\n", base, limit | 0x0fff); > +} > + > +void prettyprint_ich_descriptor_region(const struct flash_region *reg) > ich_flash_region Chipset specific or generic? > +{ > + uint8_t i; > + msg_pdbg1("=== Region Section ===\n"); > + for (i = 0; i < 5; i++) > + msg_pdbg1("FLREG%d 0x%08x\n", i, reg->FLREGs[i]); > + msg_pdbg1("\n"); > + > + msg_pdbg2("--- Details ---\n"); > + for (i = 0; i < 5; i++) > + pprint_freg(reg, i); > + msg_pdbg2("\n"); > +} > + > +void prettyprint_ich_descriptor_master(const struct flash_master *mstr) > ich_flash_master > +{ > + msg_pdbg1("=== Master Section ===\n"); > + msg_pdbg1("FLMSTR1 0x%08x\n", mstr->FLMSTR1); > + msg_pdbg1("FLMSTR2 0x%08x\n", mstr->FLMSTR2); > + msg_pdbg1("FLMSTR3 0x%08x\n", mstr->FLMSTR3); > + msg_pdbg1("\n"); > + > + msg_pdbg2("--- Details ---\n"); > + msg_pdbg2(" Descr. BIOS ME GbE Platf.\n"); > + msg_pdbg2("BIOS %c%c %c%c %c%c %c%c %c%c\n", > + (mstr->BIOS_descr_r) ?'r':' ', (mstr->BIOS_descr_w) ?'w':' ', > + (mstr->BIOS_BIOS_r) ?'r':' ', (mstr->BIOS_BIOS_w) ?'w':' ', > + (mstr->BIOS_ME_r) ?'r':' ', (mstr->BIOS_ME_w) ?'w':' ', > + (mstr->BIOS_GbE_r) ?'r':' ', (mstr->BIOS_GbE_w) ?'w':' ', > + (mstr->BIOS_plat_r) ?'r':' ', (mstr->BIOS_plat_w) ?'w':' '); > + msg_pdbg2("ME %c%c %c%c %c%c %c%c %c%c\n", > + (mstr->ME_descr_r) ?'r':' ', (mstr->ME_descr_w) ?'w':' ', > + (mstr->ME_BIOS_r) ?'r':' ', (mstr->ME_BIOS_w) ?'w':' ', > + (mstr->ME_ME_r) ?'r':' ', (mstr->ME_ME_w) ?'w':' ', > + (mstr->ME_GbE_r) ?'r':' ', (mstr->ME_GbE_w) ?'w':' ', > + (mstr->ME_plat_r) ?'r':' ', (mstr->ME_plat_w) ?'w':' '); > + msg_pdbg2("GbE %c%c %c%c %c%c %c%c %c%c\n", > + (mstr->GbE_descr_r) ?'r':' ', (mstr->GbE_descr_w) ?'w':' ', > + (mstr->GbE_BIOS_r) ?'r':' ', (mstr->GbE_BIOS_w) ?'w':' ', > + (mstr->GbE_ME_r) ?'r':' ', (mstr->GbE_ME_w) ?'w':' ', > + (mstr->GbE_GbE_r) ?'r':' ', (mstr->GbE_GbE_w) ?'w':' ', > + (mstr->GbE_plat_r) ?'r':' ', (mstr->GbE_plat_w) ?'w':' '); > + msg_pdbg2("\n"); > +} > + > +void prettyprint_ich9_reg_vscc(uint32_t reg_val) > +{ > + pprint_reg_hex(VSCC, BES, reg_val, ", "); > + pprint_reg(VSCC, WG, reg_val, ", "); > + pprint_reg(VSCC, WSR, reg_val, ", "); > + pprint_reg(VSCC, WEWS, reg_val, ", "); > + pprint_reg_hex(VSCC, EO, reg_val, ", "); > + pprint_reg(VSCC, VCL, reg_val, "\n"); > +} > + > +static uint32_t read_descriptor_reg(uint8_t section, uint16_t offset, void *spibar) > +{ > + uint32_t control = 0; > + control |= (section << FDOC_FDSS_OFF) & FDOC_FDSS; > + control |= (offset << FDOC_FDSI_OFF) & FDOC_FDSI; > + *(volatile uint32_t *) (spibar + ICH9_REG_FDOC) = control; > volatile is absolutely no-go outside hwaccess.c. Use mmio_write[bwl] or the littleendian variant of mmio_write[bwl] instead. > + return *(volatile uint32_t *)(spibar + ICH9_REG_FDOD); > Same here. Use mmio_read[bwl] instead. > +} > + > +void read_ich_descriptors_via_fdo(void *spibar, struct flash_descriptors *desc) > +{ > + msg_pdbg1("Reading flash descriptors " > + "mapped by the chipset via FDOC/FDOD..."); > + /* content section */ > + desc->content.FLVALSIG = read_descriptor_reg(0, 0, spibar); > + desc->content.FLMAP0 = read_descriptor_reg(0, 1, spibar); > + desc->content.FLMAP1 = read_descriptor_reg(0, 2, spibar); > + desc->content.FLMAP2 = read_descriptor_reg(0, 3, spibar); > + > + /* component section */ > + desc->component.FLCOMP = read_descriptor_reg(1, 0, spibar); > + desc->component.FLILL = read_descriptor_reg(1, 1, spibar); > + desc->component.FLPB = read_descriptor_reg(1, 2, spibar); > + > + /* region section */ > + desc->region.FLREGs[0] = read_descriptor_reg(2, 0, spibar); > + desc->region.FLREGs[1] = read_descriptor_reg(2, 1, spibar); > + desc->region.FLREGs[2] = read_descriptor_reg(2, 2, spibar); > + desc->region.FLREGs[3] = read_descriptor_reg(2, 3, spibar); > + desc->region.FLREGs[4] = read_descriptor_reg(2, 4, spibar); > + > + /* master section */ > + desc->master.FLMSTR1 = read_descriptor_reg(3, 0, spibar); > + desc->master.FLMSTR2 = read_descriptor_reg(3, 1, spibar); > + desc->master.FLMSTR3 = read_descriptor_reg(3, 2, spibar); > + > + /* Accessing the strap section via FDOC/D is only possible on ICH8 and > + * reading the upper map is impossible on all chipsets, so don't bother. > + */ > + > + msg_pdbg1(" done\n"); > This seems to be a true flood of output. dbg2 for all callees maybe? > +} > +#endif // defined(__i386__) || defined(__x86_64__) > diff --git a/ich_descriptors.h b/ich_descriptors.h > new file mode 100644 > index 0000000..f248394 > --- /dev/null > +++ b/ich_descriptors.h > @@ -0,0 +1,264 @@ > +/* > + * This file is part of the flashrom project. > + * > + * Copyright (c) 2010 Matthias Wenzel <bios at mazzoo dot de> > + * Copyright (c) 2011 Stefan Tauner > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License as published by > + * the Free Software Foundation; either version 2 of the License, or > + * (at your option) any later version. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + * You should have received a copy of the GNU General Public License > + * along with this program; if not, write to the Free Software > + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA > + */ > + > +#if defined(__i386__) || defined(__x86_64__) > +#ifndef __ICH_DESCRIPTORS_H__ > +#define __ICH_DESCRIPTORS_H__ 1 > + > +#include <stdint.h> > + > +/* most of the following should probably be in a new file named ichspi.h */ > +#define msg_pdbg1 msg_pdbg > +#define msg_pdbg2 msg_pspew > + > +#define ICH9_REG_FDOC 0xB0 /* 32 Bits Flash Descriptor Observability Control */ > + /* 0-1: reserved */ > +#define FDOC_FDSI_OFF 2 /* 2-11: Flash Descriptor Section Index */ > +#define FDOC_FDSI (0x3f << FDOC_FDSI_OFF) > +#define FDOC_FDSS_OFF 12 /* 12-14: Flash Descriptor Section Select */ > +#define FDOC_FDSS (0x3 << FDOC_FDSS_OFF) > + /* 15-31: reserved */ > + > +#define ICH9_REG_FDOD 0xB4 /* 32 Bits Flash Descriptor Observability Data */ > + > +/* Field locations and semantics for LVSCC, UVSCC and related words in the flash > + * descriptor are equal therefore they all share the same macros below. */ > +#define VSCC_BES_OFF 0 /* 0-1: Block/Sector Erase Size */ > +#define VSCC_BES (0x3 << VSCC_BES_OFF) > +#define VSCC_WG_OFF 2 /* 2: Write Granularity */ > +#define VSCC_WG (0x1 << VSCC_WG_OFF) > Whitespace damage or is this caused by the leading + in the patch? > +#define VSCC_WSR_OFF 3 /* 3: Write Status Required */ > +#define VSCC_WSR (0x1 << VSCC_WSR_OFF) > +#define VSCC_WEWS_OFF 4 /* 4: Write Enable on Write Status */ > +#define VSCC_WEWS (0x1 << VSCC_WEWS_OFF) > + /* 5-7: reserved */ > +#define VSCC_EO_OFF 8 /* 8-15: Erase Opcode */ > +#define VSCC_EO (0xff << VSCC_EO_OFF) > + /* 16-22: reserved */ > Whitespace damage? > +#define VSCC_VCL_OFF 23 /* 23: Vendor Component Lock */ > +#define VSCC_VCL (0x1 << VSCC_VCL_OFF) > + /* 24-31: reserved */ > + > +#define pprint_reg(reg, bit, val, sep) msg_pdbg("%s=%d" sep, #bit, (val & reg##_##bit)>>reg##_##bit##_OFF) > +#define pprint_reg_hex(reg, bit, val, sep) msg_pdbg("%s=0x%x" sep, #bit, (val & reg##_##bit)>>reg##_##bit##_OFF) > Please add () around val at the right hand side. > +void prettyprint_ich9_reg_vscc(uint32_t reg_val); > + > +#define ICH_FREG_BASE(flreg) ((flreg << 12) & 0x01fff000) > +#define ICH_FREG_LIMIT(flreg) ((flreg >> 4) & 0x01fff000) > Please add () around flreg at the right hand side. > + > +/* Used to select the right descriptor printing function. > + * Currently only ICH8 and Ibex Peak are supported. > + */ > +enum chipset { > ich_chipset > + CHIPSET_UNKNOWN, > CHIPSET_ICH_UNKNOWN We may need a CHIPSET_UNKNOWN elsewhere... > + CHIPSET_ICH7 = 7, > + CHIPSET_ICH8, > + CHIPSET_ICH9, > + CHIPSET_ICH10, > + CHIPSET_5_SERIES_IBEX_PEAK, > + CHIPSET_6_SERIES_COUGAR_POINT, > + CHIPSET_7_SERIES_PANTHER_POINT > +}; > + > All structs below probably need __attribute__((packed)). > +struct flash_content { > ich_flash_content > + uint32_t FLVALSIG; /* 0x00 */ > + union { /* 0x04 */ > + uint32_t FLMAP0; > + struct { > + uint32_t FCBA :8; > + uint32_t NC :2; > + uint32_t :6; > + uint32_t FRBA :8; > + uint32_t NR :3; > + uint32_t :5; > + }; > + }; > + union { /* 0x08 */ > + uint32_t FLMAP1; > + struct { > + uint32_t FMBA :8; > + uint32_t NM :3; > + uint32_t :5; > + uint32_t FISBA :8; > + uint32_t ISL :8; > + }; > + }; > + union { /* 0x0c */ > + uint32_t FLMAP2; > + struct { > + uint32_t FMSBA :8; > + uint32_t MSL :8; > + uint32_t :16; > + }; > + }; > +}; > + > +struct flash_component { > ich_flash_component > + union { /* 0x00 */ > + uint32_t FLCOMP; > + struct { > + uint32_t comp1_density :3; > + uint32_t comp2_density :3; > + uint32_t :11; > + uint32_t freq_read :3; > + uint32_t fastread :1; > + uint32_t freq_fastread :3; > + uint32_t freq_write :3; > + uint32_t freq_read_id :3; > + uint32_t :2; > + }; > + }; > + union { /* 0x04 */ > + uint32_t FLILL; > + struct { > + uint32_t invalid_instr0; > Really uint32_t? If FLILL is 32 bits, but all invalid_instr are 32 bits as well, the union members have inconsistent sizes. uint8_t invalid_instr0 maybe? > + uint32_t invalid_instr1; > + uint32_t invalid_instr2; > + uint32_t invalid_instr3; > Dito for the other invalid_instr above. > + }; > + }; > + union { /* 0x08 */ > + uint32_t FLPB; > + struct { > + uint32_t FPBA :13; > + uint32_t :19; > + }; > + }; > All code accessing FLPB/FPBA was broken due to the wrong FLILL union size, so if it worked anyway, you have another bug hidden somewhere. > +}; > + > +struct flash_region { > ich_flash_region > + union { > + uint32_t FLREGs[5]; > + struct { > + /* FLREG0 Flash Descriptor */ > + struct { > + uint32_t reg0_base :13; > Are uint32_t bitfields allowed? I thought bitfields were either signed int or unsigned int, but never uint32_t. > + uint32_t :3; > Are anonymous bitfields allowed? > + uint32_t reg0_limit :13; > + uint32_t :3; > + }; > + /* FLREG1 BIOS */ > + struct { > + uint32_t reg1_base :13; > + uint32_t :3; > + uint32_t reg1_limit :13; > + uint32_t :3; > + }; > + /* FLREG2 ME */ > + struct { > + uint32_t reg2_base :13; > + uint32_t :3; > + uint32_t reg2_limit :13; > + uint32_t :3; > + }; > + /* FLREG3 GbE */ > + struct { > + uint32_t reg3_base :13; > + uint32_t :3; > + uint32_t reg3_limit :13; > + uint32_t :3; > + }; > + /* FLREG4 Platform */ > + struct { > + uint32_t reg4_base :13; > + uint32_t :3; > + uint32_t reg4_limit :13; > + uint32_t :3; > + }; > + }; > + }; > +}; > + > +struct flash_master { > ich_flash_master > + union { > + uint32_t FLMSTR1; > + struct { > + uint32_t BIOS_req_ID :16; > + uint32_t BIOS_descr_r :1; > + uint32_t BIOS_BIOS_r :1; > + uint32_t BIOS_ME_r :1; > + uint32_t BIOS_GbE_r :1; > + uint32_t BIOS_plat_r :1; > + uint32_t :3; > + uint32_t BIOS_descr_w :1; > + uint32_t BIOS_BIOS_w :1; > + uint32_t BIOS_ME_w :1; > + uint32_t BIOS_GbE_w :1; > + uint32_t BIOS_plat_w :1; > + uint32_t :3; > + }; > + }; > + union { > + uint32_t FLMSTR2; > + struct { > + uint32_t ME_req_ID :16; > + uint32_t ME_descr_r :1; > + uint32_t ME_BIOS_r :1; > + uint32_t ME_ME_r :1; > + uint32_t ME_GbE_r :1; > + uint32_t ME_plat_r :1; > + uint32_t :3; > + uint32_t ME_descr_w :1; > + uint32_t ME_BIOS_w :1; > + uint32_t ME_ME_w :1; > + uint32_t ME_GbE_w :1; > + uint32_t ME_plat_w :1; > + uint32_t :3; > + }; > + }; > + union { > + uint32_t FLMSTR3; > + struct { > + uint32_t GbE_req_ID :16; > + uint32_t GbE_descr_r :1; > + uint32_t GbE_BIOS_r :1; > + uint32_t GbE_ME_r :1; > + uint32_t GbE_GbE_r :1; > + uint32_t GbE_plat_r :1; > + uint32_t :3; > + uint32_t GbE_descr_w :1; > + uint32_t GbE_BIOS_w :1; > + uint32_t GbE_ME_w :1; > + uint32_t GbE_GbE_w :1; > + uint32_t GbE_plat_w :1; > + uint32_t :3; > + }; > + }; > +}; > + > +struct flash_descriptors { > ich_flash_descriptors > + struct flash_content content; > ich_flash_content > + struct flash_component component; > ich_flash_component > + struct flash_region region; > ich_flash_region > + struct flash_master master; > ich_flash_master > +}; > + > +void prettyprint_ich_descriptors(enum chipset, const struct flash_descriptors *desc); > Missing parameter name for first parameter, and of course ich_chipset ... ich_flash_descriptors. > + > +void prettyprint_ich_descriptor_content(const struct flash_content *content); > +void prettyprint_ich_descriptor_component(const struct flash_descriptors *desc); > +void prettyprint_ich_descriptor_region(const struct flash_region *region); > +void prettyprint_ich_descriptor_master(const struct flash_master *master); > ich_ for all struct names (not for the variable names) > + > +void read_ich_descriptors_via_fdo(void *spibar, struct flash_descriptors *desc); > ich_flash_descriptors > + > +#endif // __ICH_DESCRIPTORS_H__ > +#endif // defined(__i386__) || defined(__x86_64__) > diff --git a/ichspi.c b/ichspi.c > index 2480fa5..b5ee23a 100644 > --- a/ichspi.c > +++ b/ichspi.c > @@ -30,6 +30,7 @@ > #include "chipdrivers.h" > #include "programmer.h" > #include "spi.h" > +#include "ich_descriptors.h" > > /* ICH9 controller register definition */ > #define ICH9_REG_HSFS 0x04 /* 16 Bits Hardware Sequencing Flash Status */ > @@ -120,6 +121,14 @@ > #define ICH9_REG_BBAR 0xA0 /* 32 Bits BIOS Base Address Configuration */ > #define BBAR_MASK 0x00ffff00 /* 8-23: Bottom of System Flash */ > > +#define ICH9_REG_LVSCC 0xC4 /* 32 Bits Host Lower Vendor Specific Component Capabilities */ > +#define ICH9_REG_UVSCC 0xC8 /* 32 Bits Host Upper Vendor Specific Component Capabilities */ > +/* The individual fields of the VSCC registers are defined in the file > + * ich_descriptors.h. The reason is that the same fields are also used in the > + * flash descriptors to define the properties of the different flash chips > + * supported by the BIOS image. These descriptors are also the source for the > + * registers above. */ > This comment is a bit unclear to me. > + > #define ICH9_REG_FPB 0xD0 /* 32 Bits Flash Partition Boundary */ > #define FPB_FPBA_OFF 0 /* 0-12: Block/Sector Erase Size */ > #define FPB_FPBA (0x1FFF << FPB_FPBA_OFF) > @@ -302,8 +311,6 @@ static void prettyprint_opcodes(OPCODES *ops) > } > } > > -#define pprint_reg(reg, bit, val, sep) msg_pdbg("%s=%d" sep, #bit, (val & reg##_##bit)>>reg##_##bit##_OFF) > - > static void prettyprint_ich9_reg_hsfs(uint16_t reg_val) > { > msg_pdbg("HSFS: "); > @@ -1130,9 +1137,6 @@ static int ich_spi_send_multicommand(struct spi_command *cmds) > #define ICH_BRWA(x) ((x >> 8) & 0xff) > #define ICH_BRRA(x) ((x >> 0) & 0xff) > > -#define ICH_FREG_BASE(x) ((x >> 0) & 0x1fff) > -#define ICH_FREG_LIMIT(x) ((x >> 16) & 0x1fff) > - > static void do_ich9_spi_frap(uint32_t frap, int i) > { > static const char *const access_names[4] = { > @@ -1159,9 +1163,8 @@ static void do_ich9_spi_frap(uint32_t frap, int i) > return; > } > > - msg_pdbg("0x%08x-0x%08x is %s\n", > - (base << 12), (limit << 12) | 0x0fff, > - access_names[rwperms]); > + msg_pdbg("0x%08x-0x%08x is %s\n", base, (limit | 0x0fff), > + access_names[rwperms]); > } > > static const struct spi_programmer spi_programmer_ich7 = { > @@ -1191,6 +1194,7 @@ int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, > uint8_t old, new; > uint16_t spibar_offset, tmp2; > uint32_t tmp; > + int ichspi_desc = 0; > > switch (ich_generation) { > case 7: > @@ -1262,6 +1266,8 @@ int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, > msg_pinfo("WARNING: SPI Configuration Lockdown activated.\n"); > ichspi_lock = 1; > } > + if (tmp2 & HSFS_FDV) > + ichspi_desc = 1; > > tmp2 = mmio_readw(ich_spibar + ICH9_REG_HSFC); > msg_pdbg("0x06: 0x%04x (HSFC)\n", tmp2); > @@ -1312,9 +1318,26 @@ int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, > ichspi_bbar = mmio_readl(ich_spibar + ICH9_REG_BBAR); > msg_pdbg("0xA0: 0x%08x (BBAR)\n", > ichspi_bbar); > + > + tmp = mmio_readl(ich_spibar + ICH9_REG_LVSCC); > + msg_pdbg("0xC4: 0x%08x (LVSCC)\n", tmp); > + msg_pdbg("LVSCC: "); > + prettyprint_ich9_reg_vscc(tmp); > Does the block above work correctly for all ICH8 and later chipsets? > + > + tmp = mmio_readl(ich_spibar + ICH9_REG_UVSCC); > + msg_pdbg("0xC8: 0x%08x (UVSCC)\n", tmp); > + msg_pdbg("UVSCC: "); > + prettyprint_ich9_reg_vscc(tmp); > Ditto. > + > tmp = mmio_readl(ich_spibar + ICH9_REG_FPB); > msg_pdbg("0xD0: 0x%08x (FPB)\n", tmp); > > + msg_pdbg("\n"); > + if (ichspi_desc) { > + struct flash_descriptors desc = {{ 0 }}; > + read_ich_descriptors_via_fdo(ich_spibar, &desc); > Odd code structure, but I see what you're trying to do. Makes sense. > + prettyprint_ich_descriptors(CHIPSET_UNKNOWN, &desc); > Hmmm... I really would like to see this fixed, but it's OK if you want to do that in a followup patch. > + } > ich_init_opcodes(); > break; > default: > Regards, Carl-Daniel -- http://www.hailfinger.org/

2 2

[PATCH] Be optionally seriously pedantic
by Stefan Tauner 09 Aug '11

09 Aug '11

This allows to easily test flashrom with numerous compiler warnings enabled. A new variable "PEDANTIC" is introduced which disables the feature by default, but can be overriden on the CLI. Additionally a new phony target "pedantic" is introduced which disables -Werror, enables the pedantic warnings and calls the default target recursively. It also has 'clean' as prerequisite to create consistent output. --- TODO: - make it possible to execute other targets with make pedantic(?) (something like "make pedantic target=djgpp-dos") - refine warnings used Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> --- Makefile | 21 +++++++++++++++++++-- 1 files changed, 19 insertions(+), 2 deletions(-) diff --git a/Makefile b/Makefile index c72d10a..7289bed 100644 --- a/Makefile +++ b/Makefile @@ -32,11 +32,22 @@ AR ?= ar RANLIB ?= ranlib WARNERROR ?= yes +PEDANTIC ?= no ifeq ($(WARNERROR), yes) CFLAGS += -Werror endif +ifeq ($(PEDANTIC), yes) +CFLAGS += -std=c99 --pedantic -Wextra -fstrict-aliasing\ + -Wmissing-include-dirs -Winit-self -Wswitch-enum \ + -Wundef -Wbad-function-cast -Wcast-qual -Wcast-align -Wconversion \ + -Wstrict-prototypes -Wmissing-declarations -Wredundant-decls\ + \ + -Wno-unused-parameter + # -Wno-missing-field-initializers -Wno-sign-conversion +endif + # Determine the destination processor architecture override ARCH = $(strip $(shell LC_ALL=C $(CC) -E arch.h|grep -v '^\#')) @@ -248,6 +259,7 @@ CLI_OBJS = flashrom.o cli_classic.o cli_output.o print.o PROGRAMMER_OBJS = udelay.o programmer.o all: pciutils features $(PROGRAM)$(EXEC_SUFFIX) + @echo $(CFLAGS) # Set the flashrom version string from the highest revision number # of the checked out flashrom files. @@ -643,8 +655,13 @@ tarball: export @echo Created $(EXPORTDIR)/flashrom-$(RELEASENAME).tar.bz2 djgpp-dos: clean - make CC=i586-pc-msdosdjgpp-gcc STRIP=i586-pc-msdosdjgpp-strip WARNERROR=no OS_ARCH=DOS + $(MAKE) CC=i586-pc-msdosdjgpp-gcc STRIP=i586-pc-msdosdjgpp-strip WARNERROR=no OS_ARCH=DOS + +pedantic: export WARNERROR=no +pedantic: export PEDANTIC=yes +pedantic: clean + $(MAKE) -.PHONY: all clean distclean compiler pciutils features export tarball dos featuresavailable +.PHONY: all clean distclean compiler pciutils features export tarball dos featuresavailable pedantic -include $(OBJS:.o=.d) -- 1.7.1

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

2012

2011

2010

2009

flashrom