flashrom

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9164 discussions

Asus P8P67 LE works, successfully wrote and verified
by artemis3 30 May '13

30 May '13

Hello, I checked your wiki matrix, and I'm not sure i quite understand where it says "NO (42)" what exactly means. I have this motherboard, which is a B2. there is a B3 next to it in your hardware table with a green "OK" (P8P67 PRO). I went ahead and tried flashing anyway and it worked!, It could write and verify back an old bios (1104) downloaded from Asus page. This board was nearly bricked by the writing of a B3 bios which made all sort of trouble to it, after several attempts (wouldn't post) i managed to boot linux and went with flashrom. Note 42 has this written: "Probing works (Winbond W25Q32, 4096 kB, SPI), but parts of the flash are problematic: descriptor is r/o (conforming to ICH reqs), ME region is locked." But this is wrong, flashrom identified chip MX25L3205 like the other 2 previous models. I have no idea what this ME and ICH business is to deserve a red NO, but it worked with mine. Asus page happily mentions "Pre-B3 revision motherboard users can also download and use the new B3 revision BIOS, drivers and utilities." http://event.asus.com/2011/mb/Identify_B3_Motherboards/ That is absolutely wrong!, Pre B3 users can't use any B3 BIOS image!. In my case, the bios got all sensor values wrong, and it wanted to shutdown as it thought the processor was over/under temp, voltage etc, i managed to turn off all power setting things i could to be able to post, and the bios would often freeze requiring moving the clear jumper before even wanting to turn the power on again many times. I also learned something about Asus: while their BIOS EZ Flash tool happily allows upgrading to this dangerous B3 bios in a B2 board, it won't let you flash back to the older working version, genius move... I used flashrom 0.9.5.2+r1517-1 from the Ubuntu repository. flashrom v0.9.5.2-r1517 on Linux 3.5.0-28-generic (x86_64), built with libpci 3.1.8, GCC 4.6.3, little endian flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OK. Found chipset "Intel P67". Enabling flash write... OK. Found Macronix flash chip "MX25L3205" (4096 kB, SPI) at physical address 0xffc00000.

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Re: [flashrom] New board for list
by Stefan Tauner 30 May '13

30 May '13

On Sat, 18 May 2013 15:48:56 -0400 Aurelius R <maxrowsell(a)gmail.com> wrote: > The board from the HP Pavilion a6200n which has the NVIDIA nForce 430 > Chipset works great -- I tested it multiple times reading, writing and > erasing the BIOS chip, no flaws, no errors at all. I'm also going to try > and write the VESA chip (nVidia MCP61-80) which seems to be a separate > chip, because that is the chip that seems to be causing all the trouble on > this board. > > Anyway, just thought you'd like to add that info to your list. I can also > provide the dump from flashrom -V that the program says to email to you, as > support isn't quite complete for my board/chip if you want. Hello Alexander, yes please send a verbose log (probing for the chip is good enough for now, no need to read/write). Can you confirm that this is the board in question? http://h10025.www1.hp.com/ewfrf/wc/document?docname=c01077676&tmp_task=prod… You seem to be under the impression that the graphics core uses a separate flash chip for its firmware. This is probably not the case. Instead it shares it with the "BIOS" chip that flashrom accesses. -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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Fwd: Re: Added chipsets
by Steven Zakulec 28 May '13

28 May '13

---------- Forwarded message ---------- From: "Николай Николаев" <evrinoma(a)gmail.com> Date: May 28, 2013 1:28 AM Subject: Re: [flashrom] Added chipsets To: "Steven Zakulec" <spzakulec(a)gmail.com> Cc: Hi Steven, Other people can provide more details on the general case, but in this > instance, with only a WREN instruction, the FEATURE line should be: > I've been informed by others that your original idea of dropping the > FEATURE line is actually correct, so you should do that instead of what I > proposed. > i dropped this line because this line for chips fetch Numonyx N25Q00AA13- >>> I'll admit I don't really know how this chip works, but it seems there >>> should be a 3rd eraseblock from the description of the memory organization >>> (datasheet is Rev E, 2/12): >>> >>> Memory Configuration and Block Diagram >>> The memory is a stacked device comprised of four 256Mb chips. Each chip >>> is internally >>> partitioned into two 128Mb segments. Each page of memory can be >>> individually pro- >>> grammed. Bits are programmed from one through zero. The device is >>> subsector, sector, >>> or single 256Mb chip erasable, but not page-erasable. Bits are erased >>> from zero through >>> one. The memory is configured as 134,217,728 bytes (8 bits each); 2048 >>> sectors (64KB >>> each); 32,768 subsectors (4KB each); and 524,288 pages (256 bytes each); >>> and 64 OTP >>> bytes are located outside the main memory array. >>> >>> You've got: >>> + .eraseblocks = { {4 * 1024, 32768 } }, >>> + .block_erase = spi_block_erase_20, >>> + }, { >>> + .eraseblocks = { {64 * 1024, 2048 } }, >>> + .block_erase = spi_block_erase_d8, >>> >>> There's a die erase opcode, which I am unfamiliar with- maybe it handles >>> erasing a single 256Mb chip at a time? >>> >> >> You right this chip used a four 256 Mb chips. And 256 Mb chip has a three >> instruction subsector 20(hex) sector D8(hex) bulk C7(hex) erase commands. >> But chip N25Q00AA13 has a other op-code to initiate die erase command >> C4 (hex) >> >> So, how do you do a single-chip erase for this chip? > I think this function is feature, because use "not general" op-code C4 for die erase command. Also first we need to write a special function feature extended addressing for chips more than 128 mb, after that we will think about how to initiate die erase instruction. What data sheets do you have for those chips? The ones below list the > small sector erase op-code as D7. > LE25FW418A: 61709 SY 20090428-S00004 No.A1432 > LE25FW808: 61009 SY IM 20090319-S00003 No.A0839 > LE25FW806: 70208 SY IM 20070628-S00004 No.A0838 > I have a equivalence data sheets. LE25FW808 has a general op-code 20(hex) to initiate small sector erase. Other chips use a feature op-code as D7. -- With best regards Nikolay Nikolaev

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Please help
by Aaron Brown 28 May '13

28 May '13

Hi . I installed flashrom 9.6.1 but cant find any button that says "write flashrom" please tell me, how exactly I can write the bios ? ------------------------------------------------------------------------------ with big honor. Aaron

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Re: [flashrom] Added chipsets
by Николай Николаев 27 May '13

27 May '13

---------- Forwarded message ---------- From: Николай Николаев <evrinoma(a)gmail.com> Date: 2013/5/28 Subject: Re: [flashrom] Added chipsets To: Steven Zakulec <spzakulec(a)gmail.com> Hi Steven, Other people can provide more details on the general case, but in this > instance, with only a WREN instruction, the FEATURE line should be: > I've been informed by others that your original idea of dropping the > FEATURE line is actually correct, so you should do that instead of what I > proposed. > i dropped this line because this line for chips fetch Numonyx N25Q00AA13- >>> I'll admit I don't really know how this chip works, but it seems there >>> should be a 3rd eraseblock from the description of the memory organization >>> (datasheet is Rev E, 2/12): >>> >>> Memory Configuration and Block Diagram >>> The memory is a stacked device comprised of four 256Mb chips. Each chip >>> is internally >>> partitioned into two 128Mb segments. Each page of memory can be >>> individually pro- >>> grammed. Bits are programmed from one through zero. The device is >>> subsector, sector, >>> or single 256Mb chip erasable, but not page-erasable. Bits are erased >>> from zero through >>> one. The memory is configured as 134,217,728 bytes (8 bits each); 2048 >>> sectors (64KB >>> each); 32,768 subsectors (4KB each); and 524,288 pages (256 bytes each); >>> and 64 OTP >>> bytes are located outside the main memory array. >>> >>> You've got: >>> + .eraseblocks = { {4 * 1024, 32768 } }, >>> + .block_erase = spi_block_erase_20, >>> + }, { >>> + .eraseblocks = { {64 * 1024, 2048 } }, >>> + .block_erase = spi_block_erase_d8, >>> >>> There's a die erase opcode, which I am unfamiliar with- maybe it handles >>> erasing a single 256Mb chip at a time? >>> >> >> You right this chip used a four 256 Mb chips. And 256 Mb chip has a three >> instruction subsector 20(hex) sector D8(hex) bulk C7(hex) erase commands. >> But chip N25Q00AA13 has a other op-code to initiate die erase command >> C4 (hex) >> >> So, how do you do a single-chip erase for this chip? > I think this function is feature, because use "not general" op-code C4 for die erase command. Also first we need to write a special function feature extended addressing for chips more than 128 mb, after that we will think about how to initiate die erase instruction. What data sheets do you have for those chips? The ones below list the > small sector erase op-code as D7. > LE25FW418A: 61709 SY 20090428-S00004 No.A1432 > LE25FW808: 61009 SY IM 20090319-S00003 No.A0839 > LE25FW806: 70208 SY IM 20070628-S00004 No.A0838 > I have a equivalence data sheets. LE25FW808 has a general op-code 20(hex) to initiate small sector erase. Other chips use a feature op-code as D7. -- With best regards Nikolay Nikolaev -- With best regards Nikolay Nikolaev С Уважением Николаев Николай

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Re: [flashrom] Added chipsets
by Николай Николаев 27 May '13

27 May '13

---------- Forwarded message ---------- From: Николай Николаев <evrinoma(a)gmail.com> Date: 2013/5/27 Subject: Re: [flashrom] Added chipsets To: Steven Zakulec <spzakulec(a)gmail.com> Hi steven, 2013/5/27 Steven Zakulec <spzakulec(a)gmail.com> > Before I get started on the review, just a general comment or two. > If you plan to contribute in the future (which I certainly hope you will), > please break submissions down into blocks of 5-10 chips. This makes it so > much easier for me, and any other reviewers, to quickly check the patch and > provide feedback in a timely manner. > Sorry, this is my first patch. My next patch i wrote with you wish. ( http://patchwork.coreboot.org/patch/3896/) 8) > In the last review, I mentioned the Numonyx M45PE series (10, 20, 40, 80, > 16), should only have > + .feature_bits = FEATURE_WRSR_WREN, > set when the command is there. It appears I may have been unclear there, > because instead of removing just the WREN flag, you removed the whole line > (the chips do have a Write Status Register- WRSR). > > Continuing the review from Numonyx M45PE16. > Sorry i don't know which flag must be used. You right these chips have a only WREN instruction, and i think if these chips doesn't have a feature that i exclude feature_bits. Maybe we will be able to specify the details. > Numonyx M25PX80- > + .voltage = {2700, 3600}, > The datasheets I've seen have it as 2.3-3.6V (rev 4 Dec 2008 and Rev B > 3/2013) > > + .tested = TEST_OK_PREW, > Unless I'm reading it wrong, it looks like you're adding this chip as a > fully tested one- would you mind supplying some logs showing that it > successfully does these operations? (write logs shouldn't contain all :S > (for skipped blocks) next to the addresses). > You right this is my typos, and i fixed them. > Numonyx N25Q00AA13- > I'll admit I don't really know how this chip works, but it seems there > should be a 3rd eraseblock from the description of the memory organization > (datasheet is Rev E, 2/12): > > Memory Configuration and Block Diagram > The memory is a stacked device comprised of four 256Mb chips. Each chip is > internally > partitioned into two 128Mb segments. Each page of memory can be > individually pro- > grammed. Bits are programmed from one through zero. The device is > subsector, sector, > or single 256Mb chip erasable, but not page-erasable. Bits are erased from > zero through > one. The memory is configured as 134,217,728 bytes (8 bits each); 2048 > sectors (64KB > each); 32,768 subsectors (4KB each); and 524,288 pages (256 bytes each); > and 64 OTP > bytes are located outside the main memory array. > > You've got: > + .eraseblocks = { {4 * 1024, 32768 } }, > + .block_erase = spi_block_erase_20, > + }, { > + .eraseblocks = { {64 * 1024, 2048 } }, > + .block_erase = spi_block_erase_d8, > > There's a die erase opcode, which I am unfamiliar with- maybe it handles > erasing a single 256Mb chip at a time? > You right this chip used a four 256 Mb chips. And 256 Mb chip has a three instruction subsector 20(hex) sector D8(hex) bulk C7(hex) erase commands. But chip N25Q00AA13 has a other op-code to initiate die erase command C4 (hex) > Sanyo LF25FW203A / LE25FW203A- > Thanks so much for getting to the bottom of this chip, and figuring out > which chip it actually is. > > .probe = probe_spi_rdid, > Maybe I'm reading the patch wrong, but you appear to be missing the > .probe_timing line for this chip. > You reading patch wrong. The probe_timing line for this chip is present below in source code. > LE25FW418A, LE25FW808 and LE25FW806 - > For the LE25FW806A you included the small sector erase, but left it out > for the rest of the chips- any particular reason for this? > Because only LE25FW806A has a small sector erase op-code instruction, other chips didn't have it. > > I'll cover from Spansion S25FL128S to the end tomorrow. > Excellent how to delete all versions of the patch and leave only comments in one thread? I send a new version patch -- With best regards Nikolay Nikolaev С Уважением Николаев Николай -- With best regards Nikolay Nikolaev С Уважением Николаев Николай

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Failing to write flash to Abit AN-M2HD motherboard
by Jon Wickström 27 May '13

27 May '13

Hi, Here is some more info regarding my last email. Writing the new flash image failed. Before that I read the old and verified it with flashrom. //Jonte --8<--- $ sudo flashrom -v bios_old_2013-05-26.bin flashrom v0.9.5.2-r1517 on Linux 3.2.0-44-generic (x86_64), built with libpci 3.1.8, GCC 4.6.3, little endian flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OK. Found chipset "NVIDIA MCP67". Enabling flash write... This chipset is not really supported yet. Guesswork... Please send the output of "flashrom -V" to flashrom(a)flashrom.org with your board name: flashrom -V as the subject to help us finish support for your chipset. Thanks. OK. Found PMC flash chip "Pm49FL004" (512 kB, LPC, FWH) at physical address 0xfff80000. Flash image seems to be a legacy BIOS. Disabling coreboot-related checks. Reading old flash chip contents... done. Verifying flash... VERIFIED. jonte@wintermute:/home/jonte$ sudo flashrom -w /mnt/floppy/abit/ ABITFAE.BAT AWDFLASH.EXE M628A_20.BIN M628A_20.TXT RUNME.BAT jonte@wintermute:/home/jonte$ sudo flashrom -w /mnt/floppy/abit/M628A_20.BIN flashrom v0.9.5.2-r1517 on Linux 3.2.0-44-generic (x86_64), built with libpci 3.1.8, GCC 4.6.3, little endian flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OK. Found chipset "NVIDIA MCP67". Enabling flash write... This chipset is not really supported yet. Guesswork... Please send the output of "flashrom -V" to flashrom(a)flashrom.org with your board name: flashrom -V as the subject to help us finish support for your chipset. Thanks. OK. Found PMC flash chip "Pm49FL004" (512 kB, LPC, FWH) at physical address 0xfff80000. Flash image seems to be a legacy BIOS. Disabling coreboot-related checks. Reading old flash chip contents... done. Erasing and writing flash chip... ERASE FAILED at 0x00000000! Expected=0xff, Read=0x49, failed byte count from 0x00000000-0x00000fff: 0x6ee ERASE FAILED! Reading current flash chip contents... done. ERASE FAILED at 0x00000000! Expected=0xff, Read=0x49, failed byte count from 0x00000000-0x0000ffff: 0x6ee ERASE FAILED! Reading current flash chip contents... done. ERASE FAILED at 0x00000000! Expected=0xff, Read=0x49, failed byte count from 0x00000000-0x0007ffff: 0x5f21f ERASE FAILED! FAILED! Uh oh. Erase/write failed. Checking if anything changed. Good. It seems nothing was changed. Writing to the flash chip apparently didn't do anything. This means we have to add special support for your board, programmer or flash chip. Please report this on IRC at irc.freenode.net (channel #flashrom) or mail flashrom(a)flashrom.org! ------------------------------------------------------------------------------- You may now reboot or simply leave the machine running. -- jonte(a)xn--wickstrm-t4a.fi

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Flashrom advised to email!
by Eamon M 27 May '13

27 May '13

Hi, Flashrom advised to email. Flashing 2048k bios rom file to a Lanner FW-8750 motherboard gave the following error as attached. Any help would be gratefully received. Regards, Eamon

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Re: [flashrom] Added chipsets
by Steven Zakulec 27 May '13

27 May '13

On Mon, May 27, 2013 at 12:02 PM, Steven Zakulec <spzakulec(a)gmail.com>wrote: > > > > On Mon, May 27, 2013 at 5:25 AM, Николай Николаев <evrinoma(a)gmail.com>wrote: > >> Hi steven, >> >> 2013/5/27 Steven Zakulec <spzakulec(a)gmail.com> >>> >>> In the last review, I mentioned the Numonyx M45PE series (10, 20, 40, >>> 80, 16), should only have >>> + .feature_bits = FEATURE_WRSR_WREN, >>> set when the command is there. It appears I may have been unclear >>> there, because instead of removing just the WREN flag, you removed the >>> whole line (the chips do have a Write Status Register- WRSR). >>> >> >>> Continuing the review from Numonyx M45PE16. >>> >> Sorry i don't know which flag must be used. You right these chips have a >> only WREN instruction, and i think if these chips doesn't have a feature >> that i exclude feature_bits. Maybe we will be able to specify the details. >> > Other people can provide more details on the general case, but in this > instance, with only a WREN instruction, the FEATURE line should be: > + .feature_bits = FEATURE_WRSR > > I've been informed by others that your original idea of dropping the FEATURE line is actually correct, so you should do that instead of what I proposed.

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Re: [flashrom] Added chipsets
by Steven Zakulec 27 May '13

27 May '13

On Mon, May 27, 2013 at 5:25 AM, Николай Николаев <evrinoma(a)gmail.com>wrote: > Hi steven, > > 2013/5/27 Steven Zakulec <spzakulec(a)gmail.com> > >> Before I get started on the review, just a general comment or two. >> If you plan to contribute in the future (which I certainly hope you >> will), please break submissions down into blocks of 5-10 chips. This makes >> it so much easier for me, and any other reviewers, to quickly check the >> patch and provide feedback in a timely manner. >> > Sorry, this is my first patch. My next patch i wrote with you wish. ( > http://patchwork.coreboot.org/patch/3896/) 8) > > > >> In the last review, I mentioned the Numonyx M45PE series (10, 20, 40, 80, >> 16), should only have >> + .feature_bits = FEATURE_WRSR_WREN, >> set when the command is there. It appears I may have been unclear there, >> because instead of removing just the WREN flag, you removed the whole line >> (the chips do have a Write Status Register- WRSR). >> > >> Continuing the review from Numonyx M45PE16. >> > Sorry i don't know which flag must be used. You right these chips have a > only WREN instruction, and i think if these chips doesn't have a feature > that i exclude feature_bits. Maybe we will be able to specify the details. > Other people can provide more details on the general case, but in this instance, with only a WREN instruction, the FEATURE line should be: + .feature_bits = FEATURE_WRSR > > >> Numonyx M25PX80- >> + .voltage = {2700, 3600}, >> The datasheets I've seen have it as 2.3-3.6V (rev 4 Dec 2008 and Rev B >> 3/2013) >> >> + .tested = TEST_OK_PREW, >> Unless I'm reading it wrong, it looks like you're adding this chip as a >> fully tested one- would you mind supplying some logs showing that it >> successfully does these operations? (write logs shouldn't contain all :S >> (for skipped blocks) next to the addresses). >> > You right this is my typos, and i fixed them. > > >> Numonyx N25Q00AA13- >> I'll admit I don't really know how this chip works, but it seems there >> should be a 3rd eraseblock from the description of the memory organization >> (datasheet is Rev E, 2/12): >> >> Memory Configuration and Block Diagram >> The memory is a stacked device comprised of four 256Mb chips. Each chip >> is internally >> partitioned into two 128Mb segments. Each page of memory can be >> individually pro- >> grammed. Bits are programmed from one through zero. The device is >> subsector, sector, >> or single 256Mb chip erasable, but not page-erasable. Bits are erased >> from zero through >> one. The memory is configured as 134,217,728 bytes (8 bits each); 2048 >> sectors (64KB >> each); 32,768 subsectors (4KB each); and 524,288 pages (256 bytes each); >> and 64 OTP >> bytes are located outside the main memory array. >> >> You've got: >> + .eraseblocks = { {4 * 1024, 32768 } }, >> + .block_erase = spi_block_erase_20, >> + }, { >> + .eraseblocks = { {64 * 1024, 2048 } }, >> + .block_erase = spi_block_erase_d8, >> >> There's a die erase opcode, which I am unfamiliar with- maybe it handles >> erasing a single 256Mb chip at a time? >> > > You right this chip used a four 256 Mb chips. And 256 Mb chip has a three > instruction subsector 20(hex) sector D8(hex) bulk C7(hex) erase commands. > But chip N25Q00AA13 has a other op-code to initiate die erase command > C4 (hex) > > So, how do you do a single-chip erase for this chip? > > >> Sanyo LF25FW203A / LE25FW203A- >> Thanks so much for getting to the bottom of this chip, and figuring out >> which chip it actually is. >> >> .probe = probe_spi_rdid, >> Maybe I'm reading the patch wrong, but you appear to be missing the >> .probe_timing line for this chip. >> > You reading patch wrong. The probe_timing line for this chip is present > below in source code. > Okay- thanks for checking. > > >> LE25FW418A, LE25FW808 and LE25FW806 - >> For the LE25FW806A you included the small sector erase, but left it out >> for the rest of the chips- any particular reason for this? >> > Because only LE25FW806A has a small sector erase op-code instruction, > other chips didn't have it. > > What data sheets do you have for those chips? The ones below list the small sector erase op-code as D7. LE25FW418A: 61709 SY 20090428-S00004 No.A1432 LE25FW808: 61009 SY IM 20090319-S00003 No.A0839 LE25FW806: 70208 SY IM 20070628-S00004 No.A0838 >> >> I'll cover from Spansion S25FL128S to the end tomorrow. >> > Excellent > > > how to delete all versions of the patch and leave only comments in one > thread? > Don't change what you're doing for this patch. > > I send a new version patch > > -- > With best regards Nikolay Nikolaev > С Уважением Николаев Николай >

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