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[PATCH 07/12] Add support for more Eon EN25QH chips.
by Stefan Tauner 15 Jun '13

15 Jun '13

Add... - EN25QH64 - EN25QH128 - EN25QH256 (defunct due to addressing) Signed-off-by: Nikolay Nikolaev <evrinoma(a)gmail.com> Reviewed-by: Steven Zakulec <spzakulec(a)gmail.com> Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> --- flashchips.c | 126 +++++++++++++++++++++++++++++++++++++++++++++++++++++++--- flashchips.h | 3 ++ 2 files changed, 123 insertions(+), 6 deletions(-) diff --git a/flashchips.c b/flashchips.c index 2cd4274..84d8fe9 100644 --- a/flashchips.c +++ b/flashchips.c @@ -3856,7 +3856,8 @@ const struct flashchip flashchips[] = { .page_size = 256, /* supports SFDP */ /* OTP: 512B total; enter 0x3A */ - .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP, + /* QPI enable 0x38, disable 0xFF */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_QPI, .tested = TEST_OK_PR, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, @@ -3876,8 +3877,8 @@ const struct flashchip flashchips[] = { .block_erase = spi_block_erase_c7, } }, - .printlock = spi_prettyprint_status_register_plain, /* TODO: improve */ - .unlock = spi_disable_blockprotect, + .printlock = spi_prettyprint_status_register_default_bp3, /* bit6 is quad enable */ + .unlock = spi_disable_blockprotect_bp3_srwd, .write = spi_chip_write_256, .read = spi_chip_read, .voltage = {2700, 3600}, @@ -3893,7 +3894,8 @@ const struct flashchip flashchips[] = { .page_size = 256, /* supports SFDP */ /* OTP: 512B total; enter 0x3A */ - .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP, + /* QPI enable 0x38, disable 0xFF */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_QPI, .tested = TEST_UNTESTED, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, @@ -3913,8 +3915,120 @@ const struct flashchip flashchips[] = { .block_erase = spi_block_erase_c7, } }, - .printlock = spi_prettyprint_status_register_plain, /* TODO: improve */ - .unlock = spi_disable_blockprotect, + .printlock = spi_prettyprint_status_register_default_bp3, /* bit6 is quad enable */ + .unlock = spi_disable_blockprotect_bp3_srwd, + .write = spi_chip_write_256, + .read = spi_chip_read, + .voltage = {2700, 3600}, + }, + + { + .vendor = "Eon", + .name = "EN25QH64", + .bustype = BUS_SPI, + .manufacture_id = EON_ID_NOPREFIX, + .model_id = EON_EN25QH64, + .total_size = 8192, + .page_size = 256, + /* supports SFDP */ + /* OTP: 512B total; enter 0x3A */ + /* QPI enable 0x38, disable 0xFF */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_QPI, + .tested = TEST_UNTESTED, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = { + { + .eraseblocks = { {4 * 1024, 2048} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {64 * 1024, 128} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { { 8192 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { { 8192 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, + .printlock = spi_prettyprint_status_register_default_bp3, /* bit6 is quad enable */ + .unlock = spi_disable_blockprotect_bp3_srwd, + .write = spi_chip_write_256, + .read = spi_chip_read, + .voltage = {2700, 3600}, + }, + + { + .vendor = "Eon", + .name = "EN25QH128", + .bustype = BUS_SPI, + .manufacture_id = EON_ID_NOPREFIX, + .model_id = EON_EN25QH128, + .total_size = 16384, + .page_size = 256, + /* supports SFDP */ + /* OTP: 512B total; enter 0x3A */ + /* QPI enable 0x38, disable 0xFF */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_QPI, + .tested = TEST_UNTESTED, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = { + { + .eraseblocks = { {4 * 1024, 4096} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {64 * 1024, 256} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { { 16384 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { { 16384 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, + .printlock = spi_prettyprint_status_register_default_bp3, /* bit6 is quad enable */ + .unlock = spi_disable_blockprotect_bp3_srwd, + .write = spi_chip_write_256, + .read = spi_chip_read, + .voltage = {2700, 3600}, + }, + + { + .vendor = "Eon", + .name = "EN25QH256", + .bustype = BUS_SPI, + .manufacture_id = EON_ID_NOPREFIX, + .model_id = EON_EN25QH256, + .total_size = 32768, + .page_size = 256, + /* supports SFDP */ + /* OTP: 512B total; enter 0x3A */ + /* QPI enable 0x38, disable 0xFF */ + /* EN4B: 0xB7, EX4B: 0xE9 */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_QPI, + .tested = TEST_BAD_REW, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = { + { + .eraseblocks = { {4 * 1024, 8192} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {64 * 1024, 512} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { { 32768 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { { 32768 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, + .printlock = spi_prettyprint_status_register_default_bp3, /* bit6 is quad enable */ + .unlock = spi_disable_blockprotect_bp3_srwd, .write = spi_chip_write_256, .read = spi_chip_read, .voltage = {2700, 3600}, diff --git a/flashchips.h b/flashchips.h index 5fac8dc..2442c9e 100644 --- a/flashchips.h +++ b/flashchips.h @@ -257,6 +257,9 @@ #define EON_EN25Q128 0x3018 #define EON_EN25QH16 0x7015 #define EON_EN25QH32 0x7016 +#define EON_EN25QH64 0x7017 +#define EON_EN25QH128 0x7018 +#define EON_EN25QH256 0x7019 #define EON_EN25S10 0x3811 #define EON_EN25S20 0x3812 #define EON_EN25S40 0x3813 -- Kind regards, Stefan Tauner

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[PATCH 06/12] Add support for Eon EN25S series.
by Stefan Tauner 15 Jun '13

15 Jun '13

Add... - EN25S10 - EN25S20 - EN25S40 - EN25S80 - EN25S16 - EN25S32 - EN25S64 Signed-off-by: Nikolay Nikolaev <evrinoma(a)gmail.com> Reviewed-by: Steven Zakulec <spzakulec(a)gmail.com> Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> --- chipdrivers.h | 1 + flashchips.c | 251 +++++++++++++++++++++++++++++++++++++++++++++++++++++ flashchips.h | 7 ++ spi25_statusreg.c | 14 +++ 4 files changed, 273 insertions(+) diff --git a/chipdrivers.h b/chipdrivers.h index 4bb356a..fce3ed4 100644 --- a/chipdrivers.h +++ b/chipdrivers.h @@ -90,6 +90,7 @@ int spi_disable_blockprotect_at25f512a(struct flashctx *flash); int spi_disable_blockprotect_at25f512b(struct flashctx *flash); int spi_disable_blockprotect_at25fs010(struct flashctx *flash); int spi_disable_blockprotect_at25fs040(struct flashctx *flash); +int spi_prettyprint_status_register_en25s_wp(struct flashctx *flash); int spi_prettyprint_status_register_s33(struct flashctx *flash); int spi_disable_blockprotect_s33(struct flashctx *flash); int spi_prettyprint_status_register_sst25(struct flashctx *flash); diff --git a/flashchips.c b/flashchips.c index 6bd92a6..2cd4274 100644 --- a/flashchips.c +++ b/flashchips.c @@ -3922,6 +3922,257 @@ const struct flashchip flashchips[] = { { .vendor = "Eon", + .name = "EN25S10", + .bustype = BUS_SPI, + .manufacture_id = EON_ID_NOPREFIX, + .model_id = EON_EN25S10, + .total_size = 128, + .page_size = 256, + /* OTP: 256B total; enter 0x3A */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP, + .tested = TEST_UNTESTED, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = { + { + .eraseblocks = { {4 * 1024, 32} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {32 * 1024, 4} }, + .block_erase = spi_block_erase_52, + }, { + .eraseblocks = { {128 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {128 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, + .printlock = spi_prettyprint_status_register_default_bp2, + .unlock = spi_disable_blockprotect, + .write = spi_chip_write_256, + .read = spi_chip_read, + .voltage = {1650, 1950}, + }, + + { + .vendor = "Eon", + .name = "EN25S20", + .bustype = BUS_SPI, + .manufacture_id = EON_ID_NOPREFIX, + .model_id = EON_EN25S20, + .total_size = 256, + .page_size = 256, + /* OTP: 256B total; enter 0x3A */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP, + .tested = TEST_UNTESTED, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = { + { + .eraseblocks = { {4 * 1024, 64} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {64 * 1024, 4} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {256 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {256 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, + .printlock = spi_prettyprint_status_register_default_bp2, + .unlock = spi_disable_blockprotect, + .write = spi_chip_write_256, + .read = spi_chip_read, + .voltage = {1650, 1950}, + }, + + { + .vendor = "Eon", + .name = "EN25S40", + .bustype = BUS_SPI, + .manufacture_id = EON_ID_NOPREFIX, + .model_id = EON_EN25S40, + .total_size = 512, + .page_size = 256, + /* OTP: 256B total; enter 0x3A */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP, + .tested = TEST_UNTESTED, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = { + { + .eraseblocks = { {4 * 1024, 128} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {64 * 1024, 8} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {512 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {512 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, + .printlock = spi_prettyprint_status_register_default_bp2, + .unlock = spi_disable_blockprotect, + .write = spi_chip_write_256, + .read = spi_chip_read, + .voltage = {1650, 1950}, + }, + + { + .vendor = "Eon", + .name = "EN25S80", + .bustype = BUS_SPI, + .manufacture_id = EON_ID_NOPREFIX, + .model_id = EON_EN25S80, + .total_size = 1024, + .page_size = 256, + /* OTP: 256B total; enter 0x3A */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP, + .tested = TEST_UNTESTED, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = { + { + .eraseblocks = { {4 * 1024, 256} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {64 * 1024, 16} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {1024 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {1024 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, + .printlock = spi_prettyprint_status_register_default_bp2, + .unlock = spi_disable_blockprotect, + .write = spi_chip_write_256, + .read = spi_chip_read, + .voltage = {1650, 1950}, + }, + + { + .vendor = "Eon", + .name = "EN25S16", + .bustype = BUS_SPI, + .manufacture_id = EON_ID_NOPREFIX, + .model_id = EON_EN25S16, + .total_size = 2048, + .page_size = 256, + /* OTP: 512B total; enter 0x3A */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_QPI, + .tested = TEST_UNTESTED, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = { + { + .eraseblocks = { {4 * 1024, 512} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {64 * 1024, 32} }, + .block_erase = spi_block_erase_52, + }, { + .eraseblocks = { {32 * 1024, 64} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {2048 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {2048 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, + .printlock = spi_prettyprint_status_register_en25s_wp, + .unlock = spi_disable_blockprotect_bp3_srwd, + .write = spi_chip_write_256, + .read = spi_chip_read, + .voltage = {1650, 1950}, + }, + + { + .vendor = "Eon", + .name = "EN25S32", + .bustype = BUS_SPI, + .manufacture_id = EON_ID_NOPREFIX, + .model_id = EON_EN25S32, + .total_size = 4096, + .page_size = 256, + /* OTP: 512B total; enter 0x3A */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_QPI, + .tested = TEST_UNTESTED, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = { + { + .eraseblocks = { {4 * 1024, 1024} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {32 * 1024, 128} }, + .block_erase = spi_block_erase_52, + }, { + .eraseblocks = { {64 * 1024, 64} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {4096 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {4096 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, + .printlock = spi_prettyprint_status_register_en25s_wp, + .unlock = spi_disable_blockprotect_bp3_srwd, + .write = spi_chip_write_256, + .read = spi_chip_read, + .voltage = {1650, 1950}, + }, + + { + .vendor = "Eon", + .name = "EN25S64", + .bustype = BUS_SPI, + .manufacture_id = EON_ID_NOPREFIX, + .model_id = EON_EN25S64, + .total_size = 8192, + .page_size = 256, + /* OTP: 512B total; enter 0x3A */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_QPI, + .tested = TEST_UNTESTED, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = { + { + .eraseblocks = { {4 * 1024, 2048} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {64 * 1024, 128} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {8192 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {8192 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, + .printlock = spi_prettyprint_status_register_en25s_wp, + .unlock = spi_disable_blockprotect_bp3_srwd, + .write = spi_chip_write_256, + .read = spi_chip_read, + .voltage = {1650, 1950}, + }, + + { + .vendor = "Eon", .name = "EN29F010", .bustype = BUS_PARALLEL, .manufacture_id = EON_ID, diff --git a/flashchips.h b/flashchips.h index 6e0646e..5fac8dc 100644 --- a/flashchips.h +++ b/flashchips.h @@ -257,6 +257,13 @@ #define EON_EN25Q128 0x3018 #define EON_EN25QH16 0x7015 #define EON_EN25QH32 0x7016 +#define EON_EN25S10 0x3811 +#define EON_EN25S20 0x3812 +#define EON_EN25S40 0x3813 +#define EON_EN25S80 0x3814 +#define EON_EN25S16 0x3815 +#define EON_EN25S32 0x3816 +#define EON_EN25S64 0x3817 #define EON_EN29F512 0x7F21 #define EON_EN29F010 0x20 #define EON_EN29F040A 0x7F04 diff --git a/spi25_statusreg.c b/spi25_statusreg.c index 946e790..33dd780 100644 --- a/spi25_statusreg.c +++ b/spi25_statusreg.c @@ -570,6 +570,20 @@ int spi_disable_blockprotect_at25fs040(struct flashctx *flash) return spi_disable_blockprotect_generic(flash, 0x7C, 1 << 7, 0); } +/* === Eon === */ + +int spi_prettyprint_status_register_en25s_wp(struct flashctx *flash) +{ + uint8_t status = spi_read_status_register(flash); + spi_prettyprint_status_register_hex(status); + + spi_prettyprint_status_register_srwd(status); + msg_cdbg("Chip status register: WP# disable (WPDIS) is %sabled\n", (status & (1 << 6)) ? "en " : "dis"); + spi_prettyprint_status_register_bp(status, 3); + spi_prettyprint_status_register_welwip(status); + return 0; +} + /* === Intel === */ /* TODO: Clear P_FAIL and E_FAIL with Clear SR Fail Flags Command (30h) here? */ -- Kind regards, Stefan Tauner

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[PATCH 05/12] Add support for Numonyx M45PE series.
by Stefan Tauner 15 Jun '13

15 Jun '13

Add... - M45PE10 - M45PE20 - M45PE40 - M45PE80 - M45PE16 Signed-off-by: Nikolay Nikolaev <evrinoma(a)gmail.com> Reviewed-by: Steven Zakulec <spzakulec(a)gmail.com> Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> --- flashchips.c | 135 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ flashchips.h | 5 +++ 2 files changed, 140 insertions(+) diff --git a/flashchips.c b/flashchips.c index 9b9979a..6bd92a6 100644 --- a/flashchips.c +++ b/flashchips.c @@ -6504,6 +6504,141 @@ const struct flashchip flashchips[] = { { .vendor = "Numonyx", + .name = "M45PE10", + .bustype = BUS_SPI, + .manufacture_id = ST_ID, + .model_id = ST_M45PE10, + .total_size = 128, + .page_size = 256, + .tested = TEST_UNTESTED, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = { + { + .eraseblocks = { {256, 512} }, + .block_erase = spi_block_erase_db, + }, { + .eraseblocks = { {64 * 1024, 2} }, + .block_erase = spi_block_erase_d8, + } + }, + .printlock = spi_prettyprint_status_register_default_welwip, + .unlock = NULL, /* #WP pin write-protects lower 64kB. */ + .write = spi_chip_write_256, /* Page write (similar to PP but allows 0->1 changes) */ + .read = spi_chip_read, /* Fast read (0x0B) supported */ + .voltage = {2700, 3600}, + }, + + { + .vendor = "Numonyx", + .name = "M45PE20", + .bustype = BUS_SPI, + .manufacture_id = ST_ID, + .model_id = ST_M45PE20, + .total_size = 256, + .page_size = 256, + .tested = TEST_UNTESTED, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = { + { + .eraseblocks = { {256, 1024} }, + .block_erase = spi_block_erase_db, + }, { + .eraseblocks = { {64 * 1024, 4} }, + .block_erase = spi_block_erase_d8, + } + }, + .printlock = spi_prettyprint_status_register_default_welwip, + .unlock = NULL, /* #WP pin write-protects lower 64kB. */ + .write = spi_chip_write_256, /* Page write (similar to PP but allows 0->1 changes) */ + .read = spi_chip_read, /* Fast read (0x0B) supported */ + .voltage = {2700, 3600}, + }, + + { + .vendor = "Numonyx", + .name = "M45PE40", + .bustype = BUS_SPI, + .manufacture_id = ST_ID, + .model_id = ST_M45PE40, + .total_size = 512, + .page_size = 256, + .tested = TEST_UNTESTED, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = { + { + .eraseblocks = { {256, 2048} }, + .block_erase = spi_block_erase_db, + }, { + .eraseblocks = { {64 * 1024, 8} }, + .block_erase = spi_block_erase_d8, + } + }, + .printlock = spi_prettyprint_status_register_default_welwip, + .unlock = NULL, /* #WP pin write-protects lower 64kB. */ + .write = spi_chip_write_256, /* Page write (similar to PP but allows 0->1 changes) */ + .read = spi_chip_read, /* Fast read (0x0B) supported */ + .voltage = {2700, 3600}, + }, + + { + .vendor = "Numonyx", + .name = "M45PE80", + .bustype = BUS_SPI, + .manufacture_id = ST_ID, + .model_id = ST_M45PE80, + .total_size = 1024, + .page_size = 256, + .tested = TEST_UNTESTED, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = { + { + .eraseblocks = { {256, 4096} }, + .block_erase = spi_block_erase_db, + }, { + .eraseblocks = { {64 * 1024, 16} }, + .block_erase = spi_block_erase_d8, + } + }, + .printlock = spi_prettyprint_status_register_default_welwip, + .unlock = NULL, /* #WP pin write-protects lower 64kB. */ + .write = spi_chip_write_256, /* Page write (similar to PP but allows 0->1 changes) */ + .read = spi_chip_read, /* Fast read (0x0B) supported */ + .voltage = {2700, 3600}, + }, + + { + .vendor = "Numonyx", + .name = "M45PE16", + .bustype = BUS_SPI, + .manufacture_id = ST_ID, + .model_id = ST_M45PE16, + .total_size = 2048, + .page_size = 256, + .tested = TEST_UNTESTED, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = { + { + .eraseblocks = { {256, 8192} }, + .block_erase = spi_block_erase_db, + }, { + .eraseblocks = { {64 * 1024, 32} }, + .block_erase = spi_block_erase_d8, + } + }, + .printlock = spi_prettyprint_status_register_default_welwip, + .unlock = NULL, /* #WP pin write-protects lower 64kB. */ + .write = spi_chip_write_256, /* Page write (similar to PP but allows 0->1 changes) */ + .read = spi_chip_read, /* Fast read (0x0B) supported */ + .voltage = {2700, 3600}, + }, + + { + .vendor = "Numonyx", .name = "N25Q016", .bustype = BUS_SPI, .manufacture_id = ST_ID, diff --git a/flashchips.h b/flashchips.h index 768ba80..6e0646e 100644 --- a/flashchips.h +++ b/flashchips.h @@ -598,6 +598,11 @@ #define ST_M25P32 0x2016 #define ST_M25P64 0x2017 #define ST_M25P128 0x2018 +#define ST_M45PE10 0x4011 +#define ST_M45PE20 0x4012 +#define ST_M45PE40 0x4013 +#define ST_M45PE80 0x4014 +#define ST_M45PE16 0x4015 #define ST_M25PX16 0x7115 #define ST_M25PX32 0x7116 #define ST_M25PX64 0x7117 -- Kind regards, Stefan Tauner

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[PATCH 04/12] Add support for some GigaDevice GD25* chips.
by Stefan Tauner 15 Jun '13

15 Jun '13

- GigaDevice GD25T80 - GigaDevice GD25Q10 - GigaDevice GD25Q512 Also, improve some others. Signed-off-by: Nikolay Nikolaev <evrinoma(a)gmail.com> Reviewed-by: Steven Zakulec <spzakulec(a)gmail.com> Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> --- flashchips.c | 189 +++++++++++++++++++++++++++++++++++++++++++++------------- flashchips.h | 12 +++- 2 files changed, 159 insertions(+), 42 deletions(-) diff --git a/flashchips.c b/flashchips.c index fdf9ec5..9b9979a 100644 --- a/flashchips.c +++ b/flashchips.c @@ -4173,7 +4173,118 @@ const struct flashchip flashchips[] = { { .vendor = "GigaDevice", - .name = "GD25Q20", + .name = "GD25LQ32", + .bustype = BUS_SPI, + .manufacture_id = GIGADEVICE_ID, + .model_id = GIGADEVICE_GD25LQ32, + .total_size = 4096, + .page_size = 256, + /* OTP: 1024B total, 256B reserved; read 0x48; write 0x42, erase 0x44 */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP, + .tested = TEST_OK_PREW, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 1024} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {32 * 1024, 128} }, + .block_erase = spi_block_erase_52, + }, { + .eraseblocks = { {64 * 1024, 64} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {4 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {4 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, + .printlock = spi_prettyprint_status_register_default_bp4, + .unlock = spi_disable_blockprotect_bp4_srwd, /* TODO: 2nd status reg (read with 0x35) */ + .unlock = spi_disable_blockprotect, + .write = spi_chip_write_256, + .read = spi_chip_read, + .voltage = {1700, 1950}, + }, + + { + .vendor = "GigaDevice", + .name = "GD25Q512", + .bustype = BUS_SPI, + .manufacture_id = GIGADEVICE_ID, + .model_id = GIGADEVICE_GD25Q512, + .total_size = 64, + .page_size = 256, + .feature_bits = FEATURE_WRSR_WREN, + .tested = TEST_UNTESTED, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = { + { + .eraseblocks = { {4 * 1024, 16} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {32 * 1024, 2} }, + .block_erase = spi_block_erase_52, + }, { + .eraseblocks = { {64 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {64 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, + .printlock = spi_prettyprint_status_register_default_bp4, + .unlock = spi_disable_blockprotect_bp4_srwd, /* TODO: 2nd status reg (read with 0x35) */ + .write = spi_chip_write_256, + .read = spi_chip_read, /* Fast read (0x0B) and multi I/O supported */ + .voltage = {2700, 3600}, + }, + + { + .vendor = "GigaDevice", + .name = "GD25Q10", + .bustype = BUS_SPI, + .manufacture_id = GIGADEVICE_ID, + .model_id = GIGADEVICE_GD25Q10, + .total_size = 128, + .page_size = 256, + .feature_bits = FEATURE_WRSR_WREN, + .tested = TEST_UNTESTED, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = { + { + .eraseblocks = { {4 * 1024, 32} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {32 * 1024, 4} }, + .block_erase = spi_block_erase_52, + }, { + .eraseblocks = { {64 * 1024, 2} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {128 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {128 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, + .printlock = spi_prettyprint_status_register_default_bp4, + .unlock = spi_disable_blockprotect_bp4_srwd, /* TODO: 2nd status reg (read with 0x35) */ + .write = spi_chip_write_256, + .read = spi_chip_read, /* Fast read (0x0B) and multi I/O supported */ + .voltage = {2700, 3600}, + }, + + { + .vendor = "GigaDevice", + .name = "GD25Q20(B)", .bustype = BUS_SPI, .manufacture_id = GIGADEVICE_ID, .model_id = GIGADEVICE_GD25Q20, @@ -4202,16 +4313,16 @@ const struct flashchip flashchips[] = { .block_erase = spi_block_erase_c7, } }, - .printlock = spi_prettyprint_status_register_plain, /* TODO: improve */ - .unlock = spi_disable_blockprotect, + .printlock = spi_prettyprint_status_register_default_bp4, + .unlock = spi_disable_blockprotect_bp4_srwd, /* TODO: 2nd status reg (read with 0x35) */ .write = spi_chip_write_256, - .read = spi_chip_read, + .read = spi_chip_read, /* Fast read (0x0B) and multi I/O supported */ .voltage = {2700, 3600}, }, { .vendor = "GigaDevice", - .name = "GD25Q40", + .name = "GD25Q40(B)", .bustype = BUS_SPI, .manufacture_id = GIGADEVICE_ID, .model_id = GIGADEVICE_GD25Q40, @@ -4240,10 +4351,10 @@ const struct flashchip flashchips[] = { .block_erase = spi_block_erase_c7, } }, - .printlock = spi_prettyprint_status_register_plain, /* TODO: improve */ - .unlock = spi_disable_blockprotect, + .printlock = spi_prettyprint_status_register_default_bp4, + .unlock = spi_disable_blockprotect_bp4_srwd, /* TODO: 2nd status reg (read with 0x35) */ .write = spi_chip_write_256, - .read = spi_chip_read, + .read = spi_chip_read, /* Fast read (0x0B) and multi I/O supported */ .voltage = {2700, 3600}, }, @@ -4279,16 +4390,16 @@ const struct flashchip flashchips[] = { .block_erase = spi_block_erase_c7, } }, - .printlock = spi_prettyprint_status_register_plain, /* TODO: improve */ - .unlock = spi_disable_blockprotect, + .printlock = spi_prettyprint_status_register_default_bp4, + .unlock = spi_disable_blockprotect_bp4_srwd, /* TODO: 2nd status reg (read with 0x35) */ .write = spi_chip_write_256, - .read = spi_chip_read, + .read = spi_chip_read, /* Fast read (0x0B) and multi I/O supported */ .voltage = {2700, 3600}, }, { .vendor = "GigaDevice", - .name = "GD25Q16", + .name = "GD25Q16(B)", .bustype = BUS_SPI, .manufacture_id = GIGADEVICE_ID, .model_id = GIGADEVICE_GD25Q16, @@ -4318,10 +4429,10 @@ const struct flashchip flashchips[] = { .block_erase = spi_block_erase_c7, } }, - .printlock = spi_prettyprint_status_register_plain, /* TODO: improve */ - .unlock = spi_disable_blockprotect, + .printlock = spi_prettyprint_status_register_default_bp4, + .unlock = spi_disable_blockprotect_bp4_srwd, /* TODO: 2nd status reg (read with 0x35) */ .write = spi_chip_write_256, - .read = spi_chip_read, + .read = spi_chip_read, /* Fast read (0x0B) and multi I/O supported */ .voltage = {2700, 3600}, }, @@ -4357,10 +4468,10 @@ const struct flashchip flashchips[] = { .block_erase = spi_block_erase_c7, } }, - .printlock = spi_prettyprint_status_register_plain, /* TODO: improve */ - .unlock = spi_disable_blockprotect, + .printlock = spi_prettyprint_status_register_default_bp4, + .unlock = spi_disable_blockprotect_bp4_srwd, /* TODO: 2nd status reg (read with 0x35) */ .write = spi_chip_write_256, - .read = spi_chip_read, + .read = spi_chip_read, /* Fast read (0x0B) and multi I/O supported */ .voltage = {2700, 3600}, }, @@ -4396,10 +4507,10 @@ const struct flashchip flashchips[] = { .block_erase = spi_block_erase_c7, } }, - .printlock = spi_prettyprint_status_register_plain, /* TODO: improve */ - .unlock = spi_disable_blockprotect, + .printlock = spi_prettyprint_status_register_default_bp4, + .unlock = spi_disable_blockprotect_bp4_srwd, /* TODO: 2nd status reg (read with 0x35) */ .write = spi_chip_write_256, - .read = spi_chip_read, + .read = spi_chip_read, /* Fast read (0x0B) and multi I/O supported */ .voltage = {2700, 3600}, }, @@ -4435,53 +4546,51 @@ const struct flashchip flashchips[] = { .block_erase = spi_block_erase_c7, } }, - .printlock = spi_prettyprint_status_register_plain, /* TODO: improve */ - .unlock = spi_disable_blockprotect, + .printlock = spi_prettyprint_status_register_default_bp4, + .unlock = spi_disable_blockprotect_bp4_srwd, /* TODO: 2nd status reg (read with 0x35) */ .write = spi_chip_write_256, - .read = spi_chip_read, + .read = spi_chip_read, /* Fast read (0x0B) and multi I/O supported */ .voltage = {2700, 3600}, }, { .vendor = "GigaDevice", - .name = "GD25LQ32", + .name = "GD25T80", .bustype = BUS_SPI, .manufacture_id = GIGADEVICE_ID, - .model_id = GIGADEVICE_GD25LQ32, - .total_size = 4096, + .model_id = GIGADEVICE_GD25T80, + .total_size = 1024, .page_size = 256, - /* OTP: 1024B total, 256B reserved; read 0x48; write 0x42, erase 0x44 */ + /* OTP: 256B total; enter 0x3A */ .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP, - .tested = TEST_OK_PREW, + .tested = TEST_UNTESTED, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, - .block_erasers = - { + .block_erasers = { { - .eraseblocks = { {4 * 1024, 1024} }, + .eraseblocks = { {4 * 1024, 256} }, .block_erase = spi_block_erase_20, }, { - .eraseblocks = { {32 * 1024, 128} }, + .eraseblocks = { {64 * 1024, 16} }, .block_erase = spi_block_erase_52, }, { - .eraseblocks = { {64 * 1024, 64} }, + .eraseblocks = { {64 * 1024, 16} }, .block_erase = spi_block_erase_d8, }, { - .eraseblocks = { {4 * 1024 * 1024, 1} }, + .eraseblocks = { {1024 * 1024, 1} }, .block_erase = spi_block_erase_60, }, { - .eraseblocks = { {4 * 1024 * 1024, 1} }, + .eraseblocks = { {1024 * 1024, 1} }, .block_erase = spi_block_erase_c7, } }, - .printlock = spi_prettyprint_status_register_default_bp4, - .unlock = spi_disable_blockprotect_bp4_srwd, /* TODO: 2nd status reg (read with 0x35) */ + .printlock = spi_prettyprint_status_register_plain, /* TODO: improve */ .unlock = spi_disable_blockprotect, .write = spi_chip_write_256, .read = spi_chip_read, - .voltage = {1700, 1950}, + .voltage = {2700, 3600}, }, - + { .vendor = "Hyundai", .name = "HY29F002T", diff --git a/flashchips.h b/flashchips.h index 944aa4b..768ba80 100644 --- a/flashchips.h +++ b/flashchips.h @@ -307,14 +307,22 @@ #define FUJITSU_MBM29LV800TA 0xDA /* Same as MBM29LV800TE */ #define GIGADEVICE_ID 0xC8 /* GigaDevice */ -#define GIGADEVICE_GD25Q20 0x4012 -#define GIGADEVICE_GD25Q40 0x4013 +#define GIGADEVICE_GD25T80 0x3114 +#define GIGADEVICE_GD25Q512 0x4010 +#define GIGADEVICE_GD25Q10 0x4011 +#define GIGADEVICE_GD25Q20 0x4012 /* Same as GD25QB */ +#define GIGADEVICE_GD25Q40 0x4013 /* Same as GD25QB */ #define GIGADEVICE_GD25Q80 0x4014 /* Same as GD25Q80B (which has OTP) */ #define GIGADEVICE_GD25Q16 0x4015 /* Same as GD25Q16B (which has OTP) */ #define GIGADEVICE_GD25Q32 0x4016 /* Same as GD25Q32B */ #define GIGADEVICE_GD25Q64 0x4017 /* Same as GD25Q64B */ #define GIGADEVICE_GD25Q128 0x4018 /* GD25Q128B only? */ +#define GIGADEVICE_GD25LQ40 0x6013 +#define GIGADEVICE_GD25LQ80 0x6014 +#define GIGADEVICE_GD25LQ16 0x6015 #define GIGADEVICE_GD25LQ32 0x6016 +#define GIGADEVICE_GD25LQ64 0x6017 /* Same as GD25LQ64B (which is faster) */ +#define GIGADEVICE_GD25LQ128 0x6018 #define HYUNDAI_ID 0xAD /* Hyundai */ #define HYUNDAI_HY29F400T 0x23 /* Same as HY29F400AT */ -- Kind regards, Stefan Tauner

1 0

[PATCH 03/12] Add support for all Sanyo LE25FW chips.
by Stefan Tauner 15 Jun '13

15 Jun '13

Add... - Sanyo LE25FW403A - Sanyo LE25FW418A - Sanyo LE25FW806 - Sanyo LE25FW808 Also, fix wrong description of Sanyo LE25FW203A. Signed-off-by: Nikolay Nikolaev <evrinoma(a)gmail.com> Reviewed-by: Steven Zakulec <spzakulec(a)gmail.com> Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> --- flashchips.c | 142 +++++++++++++++++++++++++++++++++++++++++++++++++++++++--- flashchips.h | 5 +++ 2 files changed, 141 insertions(+), 6 deletions(-) diff --git a/flashchips.c b/flashchips.c index 4490491..fdf9ec5 100644 --- a/flashchips.c +++ b/flashchips.c @@ -7235,11 +7235,11 @@ const struct flashchip flashchips[] = { { .vendor = "Sanyo", - .name = "LF25FW203A", + .name = "LE25FW203A", .bustype = BUS_SPI, .manufacture_id = SANYO_ID, .model_id = SANYO_LE25FW203A, - .total_size = 2048, + .total_size = 256, .page_size = 256, .tested = TEST_UNTESTED, .probe = probe_spi_rdid, @@ -7247,17 +7247,147 @@ const struct flashchip flashchips[] = { .block_erasers = { { - .eraseblocks = { {64 * 1024, 32} }, + .eraseblocks = { {256, 1024} }, + .block_erase = spi_block_erase_db, + }, { + .eraseblocks = { {64 * 1024, 4} }, .block_erase = spi_block_erase_d8, }, { - .eraseblocks = { {2 * 1024 * 1024, 1} }, + .eraseblocks = { {256 * 1024, 1} }, .block_erase = spi_block_erase_c7, } }, - .printlock = spi_prettyprint_status_register_plain, /* TODO: improve */ - .unlock = spi_disable_blockprotect, + .printlock = spi_prettyprint_status_register_default_welwip, + .unlock = NULL, /* #WP pin write-protects lower 64kB. */ .write = spi_chip_write_256, .read = spi_chip_read, + .voltage = {2700, 3600}, + }, + + { + .vendor = "Sanyo", + .name = "LE25FW403A", + .bustype = BUS_SPI, + .manufacture_id = SANYO_ID, + .model_id = SANYO_LE25FW403A, + .total_size = 512, + .page_size = 256, + .tested = TEST_UNTESTED, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = { + { + .eraseblocks = { {256, 2 * 1024} }, + .block_erase = spi_block_erase_db, + }, { + .eraseblocks = { {64 * 1024, 8} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {512 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, + .printlock = spi_prettyprint_status_register_default_welwip, + .unlock = NULL, /* #WP pin write-protects lower 64kB. */ + .write = spi_chip_write_256, + .read = spi_chip_read, + .voltage = {2700, 3600}, + }, + + { + .vendor = "Sanyo", + .name = "LE25FW418A", + .bustype = BUS_SPI, + .manufacture_id = SANYO_ID, + .model_id = SANYO_LE25FW418A, + .total_size = 512, + .page_size = 256, + .feature_bits = FEATURE_WRSR_WREN, + .tested = TEST_UNTESTED, + .probe = probe_spi_res2, + .probe_timing = TIMING_ZERO, + .block_erasers = { + { + .eraseblocks = { {4 * 1024, 128} }, + .block_erase = spi_block_erase_d7, + }, { + .eraseblocks = { {64 * 1024, 8} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {512 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, + .printlock = spi_prettyprint_status_register_default_bp2, + .unlock = spi_disable_blockprotect, /* #WP pin write-protects SRWP bit. */ + .write = spi_chip_write_256, + .read = spi_chip_read, /* some quad-read supported ("HD_READ mode") */ + .voltage = {2700, 3600}, + }, + + { + .vendor = "Sanyo", + .name = "LE25FW806", + .bustype = BUS_SPI, + .manufacture_id = SANYO_ID, + .model_id = SANYO_LE25FW806, + .total_size = 1024, + .page_size = 256, + .feature_bits = FEATURE_WRSR_WREN, + .tested = TEST_UNTESTED, + .probe = probe_spi_res2, + .probe_timing = TIMING_ZERO, + .block_erasers = { + { + .eraseblocks = { {4 * 1024, 256} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {4 * 1024, 256} }, + .block_erase = spi_block_erase_d7, + }, { + .eraseblocks = { {64 * 1024, 16} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {1024 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, + .printlock = spi_prettyprint_status_register_default_bp2, + .unlock = spi_disable_blockprotect, /* #WP pin write-protects SRWP bit. */ + .write = spi_chip_write_256, + .read = spi_chip_read, + .voltage = {2700, 3600}, + }, + + { + .vendor = "Sanyo", + .name = "LE25FW808", + .bustype = BUS_SPI, + .manufacture_id = SANYO_ID, + .model_id = SANYO_LE25FW808, + .total_size = 1024, + .page_size = 256, + .feature_bits = FEATURE_WRSR_WREN, + .tested = TEST_UNTESTED, + .probe = probe_spi_res2, + .probe_timing = TIMING_ZERO, + .block_erasers = { + { + .eraseblocks = { {8 * 1024, 128} }, + .block_erase = spi_block_erase_d7, + }, { + .eraseblocks = { {64 * 1024, 16} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {1024 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, + .printlock = spi_prettyprint_status_register_default_bp2, + .unlock = spi_disable_blockprotect, /* #WP pin write-protects SRWP bit. */ + .write = spi_chip_write_256, + .read = spi_chip_read, /* some quad-read supported ("HD_READ mode") */ + .voltage = {2700, 3600}, }, { diff --git a/flashchips.h b/flashchips.h index 41903d2..944aa4b 100644 --- a/flashchips.h +++ b/flashchips.h @@ -482,6 +482,11 @@ */ #define SANYO_ID 0x62 #define SANYO_LE25FW203A 0x1600 +#define SANYO_LE25FW403A 0x1100 +#define SANYO_LE25FW406 0x07 /* RES2 */ +#define SANYO_LE25FW418A 0x10 /* RES2 and some weird 1 byte RDID variant */ +#define SANYO_LE25FW806 0x26 /* RES2 and some weird 1 byte RDID variant */ +#define SANYO_LE25FW808 0x20 /* RES2 and some weird 1 byte RDID variant */ #define SHARP_ID 0xB0 /* Sharp */ #define SHARP_LH28F008BJ__PT 0xEC -- Kind regards, Stefan Tauner

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[PATCH 02/12] Introduce spi_block_erase_db().
by Stefan Tauner 15 Jun '13

15 Jun '13

Used for page erase on some chips (e.g. Numonyx M45PE and Sanyo LF25FW series). Signed-off-by: Nikolay Nikolaev <evrinoma(a)gmail.com> Reviewed-by: Steven Zakulec <spzakulec(a)gmail.com> Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> --- chipdrivers.h | 1 + spi.h | 5 +++++ spi25.c | 43 +++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 49 insertions(+) diff --git a/chipdrivers.h b/chipdrivers.h index c64de79..4bb356a 100644 --- a/chipdrivers.h +++ b/chipdrivers.h @@ -51,6 +51,7 @@ int spi_block_erase_81(struct flashctx *flash, unsigned int addr, unsigned int b int spi_block_erase_c7(struct flashctx *flash, unsigned int addr, unsigned int blocklen); int spi_block_erase_d7(struct flashctx *flash, unsigned int addr, unsigned int blocklen); int spi_block_erase_d8(struct flashctx *flash, unsigned int addr, unsigned int blocklen); +int spi_block_erase_db(struct flashctx *flash, unsigned int addr, unsigned int blocklen); erasefunc_t *spi_get_erasefn_from_opcode(uint8_t opcode); int spi_chip_write_1(struct flashctx *flash, uint8_t *buf, unsigned int start, unsigned int len); int spi_byte_program(struct flashctx *flash, unsigned int addr, uint8_t databyte); diff --git a/spi.h b/spi.h index 297125e..9e38e74 100644 --- a/spi.h +++ b/spi.h @@ -106,6 +106,11 @@ #define JEDEC_SE_OUTSIZE 0x04 #define JEDEC_SE_INSIZE 0x00 +/* Page Erase 0xDB */ +#define JEDEC_PE 0xDB +#define JEDEC_PE_OUTSIZE 0x04 +#define JEDEC_PE_INSIZE 0x00 + /* Read Status Register */ #define JEDEC_RDSR 0x05 #define JEDEC_RDSR_OUTSIZE 0x01 diff --git a/spi25.c b/spi25.c index 4f1452e..26da13d 100644 --- a/spi25.c +++ b/spi25.c @@ -565,6 +565,47 @@ int spi_block_erase_d7(struct flashctx *flash, unsigned int addr, return 0; } +/* Page erase (usually 256B blocks) */ +int spi_block_erase_db(struct flashctx *flash, unsigned int addr, unsigned int blocklen) +{ + int result; + struct spi_command cmds[] = { + { + .writecnt = JEDEC_WREN_OUTSIZE, + .writearr = (const unsigned char[]){ JEDEC_WREN }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = JEDEC_PE_OUTSIZE, + .writearr = (const unsigned char[]){ + JEDEC_PE, + (addr >> 16) & 0xff, + (addr >> 8) & 0xff, + (addr & 0xff) + }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = 0, + .writearr = NULL, + .readcnt = 0, + .readarr = NULL, + } }; + + result = spi_send_multicommand(flash, cmds); + if (result) { + msg_cerr("%s failed during command execution at address 0x%x\n", __func__, addr); + return result; + } + + /* Wait until the Write-In-Progress bit is cleared. + * This takes up to 20 ms usually (on worn out devices up to the 0.5s range), so wait in 1 ms steps. */ + while (spi_read_status_register(flash) & SPI_SR_WIP) + programmer_delay(1 * 1000); + /* FIXME: Check the status register for errors. */ + return 0; +} + /* Sector size is usually 4k, though Macronix eliteflash has 64k */ int spi_block_erase_20(struct flashctx *flash, unsigned int addr, unsigned int blocklen) @@ -745,6 +786,8 @@ erasefunc_t *spi_get_erasefn_from_opcode(uint8_t opcode) return &spi_block_erase_d7; case 0xd8: return &spi_block_erase_d8; + case 0xdb: + return &spi_block_erase_db; default: msg_cinfo("%s: unknown erase opcode (0x%02x). Please report " "this at flashrom(a)flashrom.org\n", __func__, opcode); -- Kind regards, Stefan Tauner

1 0

[PATCH 01/12] Introduce additional SPI status register helpers.
by Stefan Tauner 15 Jun '13

15 Jun '13

- spi_prettyprint_status_register_default_welwip(): It just prettyprints the plain hex value and the welwip bits. - spi_prettyprint_status_register_default_bp4(): Prints the hex value, welwip, bp0-5 and srwd bits. - spi_disable_blockprotect_bp2_srwd(), - spi_disable_blockprotect_bp3_srwd() and spi_disable_blockprotect_bp4_srwd(): Three new common block unprotection functions for the frequent cases where there is a status register lock bit at bit #7 and some block protection bits at bits #2-#4, #2-#5 and #2-#6 respectively. Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> --- chipdrivers.h | 6 +++++- flashchips.c | 6 ++++-- spi25_statusreg.c | 49 +++++++++++++++++++++++++++++++++++++++++++------ 3 files changed, 52 insertions(+), 9 deletions(-) diff --git a/chipdrivers.h b/chipdrivers.h index dd20631..c64de79 100644 --- a/chipdrivers.h +++ b/chipdrivers.h @@ -63,10 +63,15 @@ int spi_write_chunked(struct flashctx *flash, uint8_t *buf, unsigned int start, uint8_t spi_read_status_register(struct flashctx *flash); int spi_write_status_register(struct flashctx *flash, int status); int spi_prettyprint_status_register_plain(struct flashctx *flash); +int spi_prettyprint_status_register_default_welwip(struct flashctx *flash); int spi_prettyprint_status_register_default_bp1(struct flashctx *flash); int spi_prettyprint_status_register_default_bp2(struct flashctx *flash); int spi_prettyprint_status_register_default_bp3(struct flashctx *flash); +int spi_prettyprint_status_register_default_bp4(struct flashctx *flash); int spi_disable_blockprotect(struct flashctx *flash); +int spi_disable_blockprotect_bp2_srwd(struct flashctx *flash); +int spi_disable_blockprotect_bp3_srwd(struct flashctx *flash); +int spi_disable_blockprotect_bp4_srwd(struct flashctx *flash); int spi_prettyprint_status_register_amic_a25l032(struct flashctx *flash); int spi_prettyprint_status_register_at25df(struct flashctx *flash); int spi_prettyprint_status_register_at25df_sec(struct flashctx *flash); @@ -82,7 +87,6 @@ int spi_disable_blockprotect_at25df_sec(struct flashctx *flash); int spi_disable_blockprotect_at25f(struct flashctx *flash); int spi_disable_blockprotect_at25f512a(struct flashctx *flash); int spi_disable_blockprotect_at25f512b(struct flashctx *flash); -int spi_disable_blockprotect_at25f4096(struct flashctx *flash); int spi_disable_blockprotect_at25fs010(struct flashctx *flash); int spi_disable_blockprotect_at25fs040(struct flashctx *flash); int spi_prettyprint_status_register_s33(struct flashctx *flash); diff --git a/flashchips.c b/flashchips.c index 6ec3749..4490491 100644 --- a/flashchips.c +++ b/flashchips.c @@ -1849,7 +1849,8 @@ const struct flashchip flashchips[] = { } }, .printlock = spi_prettyprint_status_register_at25f4096, - .unlock = spi_disable_blockprotect_at25f4096, + /* "Bits 5-6 are 0s when device is not in an internal write cycle." Better leave them alone: */ + .unlock = spi_disable_blockprotect_bp2_srwd, .write = spi_chip_write_256, .read = spi_chip_read, .voltage = {2700, 3600}, @@ -4473,7 +4474,8 @@ const struct flashchip flashchips[] = { .block_erase = spi_block_erase_c7, } }, - .printlock = spi_prettyprint_status_register_plain, /* TODO: improve */ + .printlock = spi_prettyprint_status_register_default_bp4, + .unlock = spi_disable_blockprotect_bp4_srwd, /* TODO: 2nd status reg (read with 0x35) */ .unlock = spi_disable_blockprotect, .write = spi_chip_write_256, .read = spi_chip_read, diff --git a/spi25_statusreg.c b/spi25_statusreg.c index 53952fe..946e790 100644 --- a/spi25_statusreg.c +++ b/spi25_statusreg.c @@ -177,6 +177,27 @@ int spi_disable_blockprotect(struct flashctx *flash) return spi_disable_blockprotect_generic(flash, 0x3C, 0, 0); } +/* A common block protection disable that tries to unset the status register bits masked by 0x1C (BP0-2) and + * protected/locked by bit #7. Useful when bit #5 is neither a protection bit nor reserved (and hence possibly + * non-0). */ +int spi_disable_blockprotect_bp2_srwd(struct flashctx *flash) +{ + return spi_disable_blockprotect_generic(flash, 0x1C, 1 << 7, 0); +} + +/* A common block protection disable that tries to unset the status register bits masked by 0x3C (BP0-3) and + * protected/locked by bit #7. */ +int spi_disable_blockprotect_bp3_srwd(struct flashctx *flash) +{ + return spi_disable_blockprotect_generic(flash, 0x3C, 1 << 7, 0); +} + +/* A common block protection disable that tries to unset the status register bits masked by 0x7C (BP0-4) and + * protected/locked by bit #7. */ +int spi_disable_blockprotect_bp4_srwd(struct flashctx *flash) +{ + return spi_disable_blockprotect_generic(flash, 0x7C, 1 << 7, 0); +} static void spi_prettyprint_status_register_hex(uint8_t status) { @@ -242,6 +263,16 @@ int spi_prettyprint_status_register_plain(struct flashctx *flash) return 0; } +/* Print the plain hex value and the welwip bits only. */ +int spi_prettyprint_status_register_default_welwip(struct flashctx *flash) +{ + uint8_t status = spi_read_status_register(flash); + spi_prettyprint_status_register_hex(status); + + spi_prettyprint_status_register_welwip(status); + return 0; +} + /* Works for many chips of the * AMIC A25L series * and MX MX25L512 @@ -293,6 +324,17 @@ int spi_prettyprint_status_register_default_bp3(struct flashctx *flash) return 0; } +int spi_prettyprint_status_register_default_bp4(struct flashctx *flash) +{ + uint8_t status = spi_read_status_register(flash); + spi_prettyprint_status_register_hex(status); + + spi_prettyprint_status_register_srwd(status); + spi_prettyprint_status_register_bp(status, 4); + spi_prettyprint_status_register_welwip(status); + return 0; +} + /* === Amic === * FIXME: spi_disable_blockprotect is incorrect but works fine for chips using * spi_prettyprint_status_register_default_bp1 or @@ -518,11 +560,6 @@ int spi_disable_blockprotect_at25f512b(struct flashctx *flash) return spi_disable_blockprotect_at25df(flash); } -int spi_disable_blockprotect_at25f4096(struct flashctx *flash) -{ - return spi_disable_blockprotect_generic(flash, 0x1C, 1 << 7, 0); -} - int spi_disable_blockprotect_at25fs010(struct flashctx *flash) { return spi_disable_blockprotect_generic(flash, 0x6C, 1 << 7, 0); @@ -538,7 +575,7 @@ int spi_disable_blockprotect_at25fs040(struct flashctx *flash) /* TODO: Clear P_FAIL and E_FAIL with Clear SR Fail Flags Command (30h) here? */ int spi_disable_blockprotect_s33(struct flashctx *flash) { - return spi_disable_blockprotect_generic(flash, 0x1C, 1 << 7, 0); + return spi_disable_blockprotect_bp2_srwd(flash); } int spi_prettyprint_status_register_s33(struct flashctx *flash) -- Kind regards, Stefan Tauner

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[PATCH 00/12] Flashchip galore
by Stefan Tauner 15 Jun '13

15 Jun '13

So... I took a closer look at the existing monster patch and found quite some mistakes which Steven did not catch (e.g. non-working probing methods), which is quite normal for such big patches. It is easy to overlook small bits in such a huge diff, hence my advice to never do it this way again (please). While reviewing and splitting the patch I also noticed that only most basic chip support was added with many of the small details missing (status register printing and proper unlocking, comments regarding OTP, SFDP, different I/O modes etc.). This is the result of my rework. I'd be happy to see someone looking through it and/or asking questions regarding anything that I have changed. I'll this set shortly before the release of 0.9.7 (which will be released tomorrow or next week). Thanks to everybody involved so far! Stefan Tauner (12): Introduce additional SPI status register helpers. Introduce spi_block_erase_db(). Add support for all Sanyo LE25FW chips. Add support for some GigaDevice GD25* chips. Add support for Numonyx M45PE series. Add support for Eon EN25S series. Add support for more Eon EN25QH chips. Add support for AMIC A25LQ16 and A25LQ64. Add support for Micron/Numonyx/ST M25PX80. Add support for Spansion S25FL2 chips. Add support for Spansion S25FL...S chips. Add support for remaining Numonyx (Micron) N25Q chips. chipdrivers.h | 15 +- flashchips.c | 3212 +++++++++++++++++++++++++++++++++++++---------------- flashchips.h | 61 +- spi.h | 10 + spi25.c | 88 ++ spi25_statusreg.c | 93 +- 6 files changed, 2505 insertions(+), 974 deletions(-) -- Kind regards, Stefan Tauner

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Re: [flashrom] USB 3 PCI Card support (request to add device)
by Philipp Post 13 Jun '13

13 Jun '13

I have added some flashrom and linux logs which might be helpfull: The USB 3 PCI card has the following system properties: DRIVER=xhci_hcd PCI_CLASS=C0330 PCI_ID=1033:0194 PCI_SUBSYS_ID=1033:0194 PCI_SLOT_NAME=0000:03:00.0 MODALIAS=pci:v00001033d00000194sv00001033sd00000194bc0Csc03i30 There is also a PCI NIC Intel 82541PI Gigabit Ethernet Controller (8086:107c, BDF 02:0a.0) and a PCI soundcard installed. Tried to read the flash rom out of the 82541PI Intel NIC without problems. /sys/bus/pci/devices/0000:02:0a.0 of the Intel NIC also gives access to "rom" which the USB 3 and the soundcard do not. I am not sure if that means that the rom is not accessible at all or if Ubuntu just does not know how. Thanks in advance, brgds Philipp -----Ursprüngliche Nachricht----- Von: Philipp Post [mailto:Post.Philipp@googlemail.com] Gesendet: Donnerstag, 24. Januar 2013 19:23 An: 'flashrom(a)flashrom.org' Betreff: USB 3 PCI Card support (request to add device) Good day, following configuration: - USB 3 PCI (not PCI-Express) card with RENESAS uPD720200A(Revision 4) USB chip and ATMEL AT25F512B (ATMEL 1138, 25F512B, SSH) rom chip in - IBM NetVista 8305 Desktop PC - built year 2003 The issue with the card is that it needs a flash rom update to work with Windows Vista and up, otherwise the device does not work at all in these OS ("device cannot start"). Windows XP with Renesas drivers and Linux Ubuntu 11.3 out of the box works fine. RENESAS has a rom update for the chip and a flash update tool which however does not work with PCI cards, but just chips soldered to mainboards. At least this seems to me the reason why it does not work. Chip is recognized but the RENESAS tool says "Can not load / access firmware". The tool has the option to change the device / vendor id as well via .ini file. The card used is the only PCI USB 3 card on the market and basically works very well when it works - with max PCI speed of course, which means approx. double speed of USB 2. The card exists in hardware version 1 (RENESAS chip uPD720200A) and 2 (RENESAS chip uPD720202). I do just have access to hardware version 1. The name of the manufacturer behind the card is unknown to me, but it could be an ADDONICS product. I do not have a technical drawing of the card and I fear I can not obtain one but I do have the card itself. My question: would it be possible to incorporate this card into flashrom? Would be great if someone could do it as I do not have the necessary skills to do it myself. In case you need further information, please let me know. Thanks in advance, brgds Philipp Links and further reading: -------------------------- Card Information from different sellers (same card): http://www.addonics.com/products/ad2u3pci.php http://eu.startech.com/Cards-Adapters/USB-3.0/Cards/2-Port-PCI-SuperSpeed-US B-3-Card-Adapter~PCIUSB3S2 http://www.lindy.de/premium-usb-3-karte-2-port-pci/51082.html ATMEL rom specification (contains info how to write rom images): www.atmel.com/Images/doc3689.pdf Renesas USB chip information: http://www.renesas.eu/products/soc/usb_assp/product/upd720200a/index.jsp RENESAS rom update 4.0.2.0 with Windows updater (32 + 64 Bit) and drivers: http://www.station-drivers.com/page/renesas.htm We need: "Firmware Version 4.0.2.0 pour uPD720200a" RENESAS MS DOS flash update tool (which did not do the job): http://www.computerbase.de/forum/attachment.php?attachmentid=283282&d=133832 3319 IBM NetVista 8305 Hardware Maintenance Manual: http://download.lenovo.com/ibmdl/pub/pc/pccbbs/netvista_pdf/24p2969.pdf Hardware Ids: Renesas Electronics USB 3.0 Host Controller: PCI\VEN_1033&DEV_0194&SUBSYS_01941033&REV_04\5&25043F3&0&0048F0 Renesas Electronics USB 3.0 Root Hub NUSB3\ROOT_HUB30\6&2D374EF3&2

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X79 Motherboard untested - reassurance? ;)
by Rupert Bailey 10 Jun '13

10 Jun '13

Hello team, Keen to find out if using flashbios is a good idea for my chipset Chipset: Intel X79 Motherboard: FX79 System: SX79R5 Shuttle Part of the reason why I think I need to do a bios update is because my 12.04 Ubuntu system is providing this error message on startup: [ 3.858429] EDAC sbridge: ECC is disabled. Aborting [ 3.858471] EDAC sbridge: Couldn't find mci handler And several forum posts were indicating that updates might fix this.

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