flashrom

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[commit] r1791 - trunk
by repository service 14 May '14

14 May '14

Author: stefanct Date: Wed May 14 15:19:50 2014 New Revision: 1791 URL: http://flashrom.org/trac/flashrom/changeset/1791 Log: Add support for Sanyo LE25FU406B. It is very similar to LE25FW418A, except for HD_READ support (that is not implemented in flashrom anyway yet) and allowed voltage range. Probing, erasing, reading and writing has been tested. This chip is found on Seagate Constellation hard drives. Signed-off-by: Jurij Munda <jurij.munda(a)uni-mb.si> Acked-by: Stefan Tauner <stefan.tauner(a)alumni.tuwien.ac.at> Modified: trunk/flashchips.c trunk/flashchips.h Modified: trunk/flashchips.c ============================================================================== --- trunk/flashchips.c Sat May 10 11:25:44 2014 (r1790) +++ trunk/flashchips.c Wed May 14 15:19:50 2014 (r1791) @@ -9040,6 +9040,37 @@ { .vendor = "Sanyo", + .name = "LE25FU406B", + .bustype = BUS_SPI, + .manufacture_id = SANYO_ID, + .model_id = SANYO_LE25FU406B, + .total_size = 512, + .page_size = 256, + .feature_bits = FEATURE_WRSR_WREN, + .tested = TEST_OK_PREW, + .probe = probe_spi_res2, + .probe_timing = TIMING_ZERO, + .block_erasers = { + { + .eraseblocks = { {4 * 1024, 128} }, + .block_erase = spi_block_erase_d7, + }, { + .eraseblocks = { {64 * 1024, 8} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {512 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, + .printlock = spi_prettyprint_status_register_default_bp2, + .unlock = spi_disable_blockprotect, /* #WP pin write-protects SRWP bit. */ + .write = spi_chip_write_256, + .read = spi_chip_read, + .voltage = {2300, 3600}, + }, + + { + .vendor = "Sanyo", .name = "LE25FW203A", .bustype = BUS_SPI, .manufacture_id = SANYO_ID, Modified: trunk/flashchips.h ============================================================================== --- trunk/flashchips.h Sat May 10 11:25:44 2014 (r1790) +++ trunk/flashchips.h Wed May 14 15:19:50 2014 (r1791) @@ -537,6 +537,7 @@ #define SANYO_LE25FW403A 0x1100 #define SANYO_LE25FW406 0x07 /* RES2 */ #define SANYO_LE25FW418A 0x10 /* RES2 and some weird 1 byte RDID variant */ +#define SANYO_LE25FU406B 0x1E /* LE25FW418A without HD_READ mode option variant */ #define SANYO_LE25FW806 0x26 /* RES2 and some weird 1 byte RDID variant */ #define SANYO_LE25FW808 0x20 /* RES2 and some weird 1 byte RDID variant */

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W836xx: HP ProLiant DL145 G3: flashrom -V
by Horacio J. Peña 14 May '14

14 May '14

HIH flashrom v0.9.5.2-r1546 on Linux 3.2.0-4-amd64 (x86_64) flashrom is free software, get the source code at http://www.flashrom.org flashrom was built with libpci 3.1.7, GCC 4.6.2, little endian Command line (1 args): flashrom -V Calibrating delay loop... OS timer resolution is 2 usecs, 367M loops per second, delay more than 10% too short (got 51% of expected delay), recalculating... 730M loops per second, 10 myus = 11 us, 100 myus = 101 us, 1000 myus = 1008 us, 10000 myus = 9997 us, 8 myus = 9 us, OK. Initializing internal programmer No coreboot table found. DMI string system-manufacturer: "HP" DMI string system-product-name: "ProLiant DL145 G3" DMI string system-version: " " DMI string baseboard-manufacturer: "NEWISYS" DMI string baseboard-product-name: " " DMI string baseboard-version: "rA3" DMI string chassis-type: "Rack Mount Chassis" W836xx enter config mode worked or we were already in config mode. W836xx leave config mode had no effect. Active config mode, unknown reg 0x20 ID: f2. Please send the output of "flashrom -V" to flashrom(a)flashrom.org with W836xx: your board name: flashrom -V as the subject to help us finish support for your Super I/O. Thanks. Found chipset "Broadcom HT-1000" with PCI ID 1166:0205. Enabling flash write... OK. Disabling flash write protection for board "HP ProLiant DL145 G3"... OK. The following protocols are supported: Non-SPI. Probing for AMD Am29F010A/B, 128 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29F002(N)BB, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29F002(N)BT, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29F016D, 2048 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29F040B, 512 kB: probe_jedec_common: id1 0x4e, id2 0x41, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29F080B, 1024 kB: probe_jedec_common: id1 0xf8, id2 0x00, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29LV001BB, 128 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29LV001BT, 128 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29LV002BB, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29LV002BT, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29LV004BB, 512 kB: probe_jedec_common: id1 0x4e, id2 0x41, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29LV004BT, 512 kB: probe_jedec_common: id1 0x4e, id2 0x41, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29LV008BB, 1024 kB: probe_jedec_common: id1 0xf8, id2 0x00, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29LV008BT, 1024 kB: probe_jedec_common: id1 0xf8, id2 0x00, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29LV040B, 512 kB: probe_jedec_common: id1 0x4e, id2 0x41, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29LV081B, 1024 kB: probe_jedec_common: id1 0xf8, id2 0x00, id1 is normal flash content, id2 is normal flash content Probing for AMIC A29002B, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMIC A29002T, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMIC A29040B, 512 kB: probe_jedec_common: id1 0x4e, id2 0x41, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMIC A49LF040A, 512 kB: probe_jedec_common: id1 0xbf, id2 0x5b Probing for Atmel AT29C512, 64 kB: probe_jedec_common: id1 0xbf, id2 0x5b Probing for Atmel AT29C010A, 128 kB: probe_jedec_common: id1 0xbf, id2 0x5b Probing for Atmel AT29C020, 256 kB: probe_jedec_common: id1 0xbf, id2 0x5b Probing for Atmel AT29C040A, 512 kB: probe_jedec_common: id1 0xbf, id2 0x5b Probing for Atmel AT49BV512, 64 kB: probe_jedec_common: id1 0xbf, id2 0x5b Probing for Atmel AT49F002(N), 256 kB: probe_jedec_common: id1 0xbf, id2 0x5b Probing for Atmel AT49F002(N)T, 256 kB: probe_jedec_common: id1 0xbf, id2 0x5b Probing for Atmel AT49F020, 256 kB: probe_jedec_common: id1 0xbf, id2 0x5b Probing for Atmel AT49F040, 512 kB: probe_jedec_common: id1 0xbf, id2 0x5b Probing for Atmel AT49LH002, 256 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Catalyst CAT28F512, 64 kB: probe_jedec_common: id1 0xbf, id2 0x5b Probing for Bright BM29F040, 512 kB: probe_jedec_common: id1 0xbf, id2 0x5b Probing for EMST F49B002UA, 256 kB: probe_jedec_common: id1 0xbf, id2 0x5b Probing for Eon EN29F010, 128 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Eon EN29F002(A)(N)B, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Eon EN29F002(A)(N)T, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Eon EN29LV640B, 8192 kB: probe_en29lv640b: id1 0xffff, id2 0x00ff Probing for Fujitsu MBM29F004BC, 512 kB: probe_jedec_common: id1 0x4e, id2 0x41, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Fujitsu MBM29F004TC, 512 kB: probe_jedec_common: id1 0x4e, id2 0x41, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Fujitsu MBM29F400BC, 512 kB: probe_m29f400bt: id1 0x4e, id2 0x50 Probing for Fujitsu MBM29F400TC, 512 kB: probe_m29f400bt: id1 0x4e, id2 0x50 Probing for Hyundai HY29F002T, 256 kB: probe_jedec_common: id1 0xbf, id2 0x5b Probing for Hyundai HY29F002B, 256 kB: probe_jedec_common: id1 0xbf, id2 0x5b Probing for Hyundai HY29F040A, 512 kB: probe_jedec_common: id1 0x4e, id2 0x41, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 28F001BN/BX-B, 128 kB: probe_jedec_common: id1 0xbf, id2 0x5b Probing for Intel 28F001BN/BX-T, 128 kB: probe_jedec_common: id1 0xbf, id2 0x5b Probing for Intel 28F002BC/BL/BV/BX-T, 256 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 28F008S3/S5/SC, 512 kB: probe_82802ab: id1 0x4e, id2 0x41, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 28F004B5/BE/BV/BX-B, 512 kB: probe_82802ab: id1 0x4e, id2 0x41, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 28F004B5/BE/BV/BX-T, 512 kB: probe_82802ab: id1 0x4e, id2 0x41, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 28F400BV/BX/CE/CV-B, 512 kB: probe_82802ab: id1 0x4e, id2 0x50, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 28F400BV/BX/CE/CV-T, 512 kB: probe_82802ab: id1 0x4e, id2 0x50, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 82802AB, 512 kB: probe_82802ab: id1 0x4e, id2 0x41, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 82802AC, 1024 kB: probe_82802ab: id1 0xf8, id2 0x00, id1 is normal flash content, id2 is normal flash content Probing for Macronix MX29F001B, 128 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Macronix MX29F001T, 128 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Macronix MX29F002(N)B, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Macronix MX29F002(N)T, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Macronix MX29F040, 512 kB: probe_jedec_common: id1 0x4e, id2 0x41, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Macronix MX29LV040, 512 kB: probe_jedec_common: id1 0x4e, id2 0x41, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for MoselVitelic V29C51000B, 64 kB: probe_jedec_common: id1 0xbf, id2 0x5b Probing for MoselVitelic V29C51000T, 64 kB: probe_jedec_common: id1 0xbf, id2 0x5b Probing for MoselVitelic V29C51400B, 512 kB: probe_jedec_common: id1 0xbf, id2 0x5b Probing for MoselVitelic V29C51400T, 512 kB: probe_jedec_common: id1 0xbf, id2 0x5b Probing for MoselVitelic V29LC51000, 64 kB: probe_jedec_common: id1 0xbf, id2 0x5b Probing for MoselVitelic V29LC51001, 128 kB: probe_jedec_common: id1 0xbf, id2 0x5b Probing for MoselVitelic V29LC51002, 256 kB: probe_jedec_common: id1 0xbf, id2 0x5b Probing for PMC Pm29F002T, 256 kB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm29F002B, 256 kB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm39LV010, 128 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm39LV020, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm39LV040, 512 kB: probe_jedec_common: id1 0x4e, id2 0x41, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm39LV512, 64 kB: probe_jedec_common: id1 0x00, id2 0x00, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm49FL002, 256 kB: probe_jedec_common: id1 0xbf, id2 0x5b Probing for PMC Pm49FL004, 512 kB: probe_jedec_common: id1 0xbf, id2 0x5b Probing for Sharp LH28F008BJT-BTLZ1, 1024 kB: probe_82802ab: id1 0xf8, id2 0x00, id1 is normal flash content, id2 is normal flash content Probing for Sharp LHF00L04, 1024 kB: probe_82802ab: id1 0xf8, id2 0x00, id1 is normal flash content, id2 is normal flash content Probing for SST SST28SF040A, 512 kB: probe_82802ab: id1 0x4e, id2 0x41, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST29EE010, 128 kB: probe_jedec_common: id1 0xbf, id2 0x5b Probing for SST SST29LE010, 128 kB: probe_jedec_common: id1 0xbf, id2 0x5b Probing for SST SST29EE020A, 256 kB: probe_jedec_common: id1 0xbf, id2 0x5b Probing for SST SST29LE020, 256 kB: probe_jedec_common: id1 0xbf, id2 0x5b Probing for SST SST39SF512, 64 kB: probe_jedec_common: id1 0xbf, id2 0x5b Probing for SST SST39SF010A, 128 kB: probe_jedec_common: id1 0xbf, id2 0x5b Probing for SST SST39SF020A, 256 kB: probe_jedec_common: id1 0xbf, id2 0x5b Probing for SST SST39SF040, 512 kB: probe_jedec_common: id1 0xbf, id2 0x5b Probing for SST SST39VF512, 64 kB: probe_jedec_common: id1 0xbf, id2 0x5b Probing for SST SST39VF010, 128 kB: probe_jedec_common: id1 0xbf, id2 0x5b Probing for SST SST39VF020, 256 kB: probe_jedec_common: id1 0xbf, id2 0x5b Probing for SST SST39VF040, 512 kB: probe_jedec_common: id1 0xbf, id2 0x5b Probing for SST SST39VF080, 1024 kB: probe_jedec_common: id1 0xbf, id2 0x5b Probing for SST SST49LF002A/B, 256 kB: probe_jedec_common: id1 0xbf, id2 0x5b Probing for SST SST49LF003A/B, 384 kB: probe_jedec_common: id1 0xbf, id2 0x5b Probing for SST SST49LF004A/B, 512 kB: probe_jedec_common: id1 0xbf, id2 0x5b Probing for SST SST49LF004C, 512 kB: probe_82802ab: id1 0x4e, id2 0x41, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF008A, 1024 kB: probe_jedec_common: id1 0xbf, id2 0x5b Probing for SST SST49LF008C, 1024 kB: probe_82802ab: id1 0xf8, id2 0x00, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF016C, 2048 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF020, 256 kB: probe_jedec_common: id1 0xbf, id2 0x5b Probing for SST SST49LF020A, 256 kB: probe_jedec_common: id1 0xbf, id2 0x5b Probing for SST SST49LF040, 512 kB: probe_jedec_common: id1 0xbf, id2 0x5b Probing for SST SST49LF040B, 512 kB: probe_jedec_common: id1 0xbf, id2 0x5b Probing for SST SST49LF080A, 1024 kB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0xbf, id2 0x5b Found SST flash chip "SST49LF080A" (1024 kB, LPC) at physical address 0xfff00000. Probing for SST SST49LF160C, 2048 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M29F002B, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M29F002T/NT, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M29F040B, 512 kB: probe_jedec_common: id1 0x4e, id2 0x41, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M29F400BB, 512 kB: probe_m29f400bt: id1 0x4e, id2 0x50 Probing for ST M29F400BT, 512 kB: probe_m29f400bt: id1 0x4e, id2 0x50 Probing for ST M29W010B, 128 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M29W040B, 512 kB: probe_jedec_common: id1 0x4e, id2 0x41, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M29W512B, 64 kB: probe_jedec_common: id1 0x00, id2 0x00, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW040A, 512 kB: probe_82802ab: id1 0x4e, id2 0x41, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW040B, 512 kB: probe_82802ab: id1 0x4e, id2 0x41, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080A, 1024 kB: probe_82802ab: id1 0xf8, id2 0x00, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080B, 1024 kB: probe_82802ab: id1 0xf8, id2 0x00, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW002, 256 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW016, 2048 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW040, 512 kB: probe_82802ab: id1 0x4e, id2 0x41, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW080, 1024 kB: probe_82802ab: id1 0xf8, id2 0x00, id1 is normal flash content, id2 is normal flash content Probing for ST M50LPW116, 2048 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SyncMOS/MoselVitelic {F,S,V}29C51001B, 128 kB: probe_jedec_common: id1 0xbf, id2 0x5b Probing for SyncMOS/MoselVitelic {F,S,V}29C51001T, 128 kB: probe_jedec_common: id1 0xbf, id2 0x5b Probing for SyncMOS/MoselVitelic {F,S,V}29C51002B, 256 kB: probe_jedec_common: id1 0xbf, id2 0x5b Probing for SyncMOS/MoselVitelic {F,S,V}29C51002T, 256 kB: probe_jedec_common: id1 0xbf, id2 0x5b Probing for SyncMOS/MoselVitelic {F,S,V}29C51004B, 512 kB: probe_jedec_common: id1 0xbf, id2 0x5b Probing for SyncMOS/MoselVitelic {F,S,V}29C51004T, 512 kB: probe_jedec_common: id1 0xbf, id2 0x5b Probing for SyncMOS/MoselVitelic {S,V}29C31004B, 512 kB: probe_jedec_common: id1 0xbf, id2 0x5b Probing for SyncMOS/MoselVitelic {S,V}29C31004T, 512 kB: probe_jedec_common: id1 0xbf, id2 0x5b Probing for TI TMS29F002RB, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for TI TMS29F002RT, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W29C010(M)/W29C011A/W29EE011/W29EE012-old, 128 kB: Old Winbond W29* probe method disabled because the probing sequence puts the AMIC A49LF040A in a funky state. Use 'flashrom -c W29C010(M)/W29C011A/W29EE011/W29EE012-old' if you have a board with such a chip. Probing for Winbond W29C010(M)/W29C011A/W29EE011/W29EE012, 128 kB: probe_jedec_common: id1 0xbf, id2 0x5b Probing for Winbond W29C020(C)/W29C022, 256 kB: probe_jedec_common: id1 0xbf, id2 0x5b Probing for Winbond W29C040/P, 512 kB: probe_jedec_common: id1 0xbf, id2 0x5b Probing for Winbond W39L040, 512 kB: probe_jedec_common: id1 0xbf, id2 0x5b Probing for Winbond W39V040A, 512 kB: probe_jedec_common: id1 0xbf, id2 0x5b Probing for Winbond W39V040B, 512 kB: probe_jedec_common: id1 0xbf, id2 0x5b Probing for Winbond W39V040C, 512 kB: probe_jedec_common: id1 0xbf, id2 0x5b Probing for Winbond W39V040FA, 512 kB: probe_jedec_common: id1 0xbf, id2 0x5b Probing for Winbond W39V040FB, 512 kB: probe_jedec_common: id1 0xbf, id2 0x5b Probing for Winbond W39V040FC, 512 kB: probe_jedec_common: id1 0xbf, id2 0x5b Probing for Winbond W39V080A, 1024 kB: probe_jedec_common: id1 0xbf, id2 0x5b Probing for Winbond W49F002U/N, 256 kB: probe_jedec_common: id1 0xbf, id2 0x5b Probing for Winbond W49F020, 256 kB: probe_jedec_common: id1 0xbf, id2 0x5b Probing for Winbond W49V002A, 256 kB: probe_jedec_common: id1 0xbf, id2 0x5b Probing for Winbond W49V002FA, 256 kB: probe_jedec_common: id1 0xbf, id2 0x5b Probing for Winbond W39V080FA, 1024 kB: probe_jedec_common: id1 0xbf, id2 0x5b Probing for Winbond W39V080FA (dual mode), 512 kB: probe_jedec_common: id1 0xbf, id2 0x5b Found SST flash chip "SST49LF080A" (1024 kB, LPC). No operations were specified. Restoring PCI config space for 00:02:0 reg 0x43 Restoring PCI config space for 00:02:0 reg 0x41 -- Horacio J. Peña horape(a)compendium.com.ar horape(a)uninet.edu

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Buspirate Erratic Results : WInbond W25Q128.V
by Roberto Denis 13 May '14

13 May '14

I have three workstations with the same motherboards, all identical (same revision, chips, etc.). Motherboards have a Winbond W25Q128 flash chip. I have flashed two of those successfully several times with Buspirate (internal programmer is a no-go on these boards). On the third motherboard flashrom fails to identify the flash chip 8 out of 10 times and terminates. Then on the few occasions when it does identify the flash chip it fails to complete the flashing process successfully (errors erasing). I have tried two different Buspirate flashed with firmware 5.1, 6.0, 6.1, and 6.2 (same results regardless of firmware). All the hardware connections are fine - I have checked continuity from the flash chip legs to the Pomona clip to Buspirate. My wire leads from Buspirate to the Pomona clip are short, 10 cm. I am certain this is not a hardware issue since Buspirate/flashrom work on two other motherboards. I just do not know what other test should be pursued to get to a resolution. I have attached the –V logs for a successful flash from one of the two boards flashrom works, log where flash chip found but aborts on errors, log where flash chip not found, and a –VVV log for the latter. I note that the ‘probing’ results are very different but do not know what that may lead to conclude. Any pointers, comments, help welcome.

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Flashrom and KT4V in 2014
by Ronald 13 May '14

13 May '14

Hi there, I tried to use flashrom to upgrade my kt4v mobo. However, verifying the data read from the bios through flashrom was not the exact same as bios version from the manufacturer's website. It seems to appear that the BIOS read through flashrom holds more data than the BIOS from the manufacturer's website. So, it was decided to use the propietary tool from the manufacturer. Eventually, the bios was succesfully upgraded with freedos and the propietary utility of the manufacturer's website. After the upgrade, another verification was done using flashrom. Again, it seems that flashrom reads more data than what is provided by the BIOS image from the manufacturer's website. Maybe it's an idea to blacklist this mobo if the difference cannot be explained? I'm just an end user reporting my findings. If I'm incorrect in assuming that both should match then please consider this message as not send. Ronald P.S. The upgrade involved the KT4V 1.0A mobo, bios version 1.8->1.0C

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[PATCH] nicintel_eeprom: New programmer for Intel Nics eeproms
by Ricardo Ribalda Delgado 12 May '14

12 May '14

This patch let you read and write the eeprom on your gigagit nic card. So far it has been tested on the 82580 NIC, but there should be other boards also compatibles. It is a nice substitution for the eeupdate tool. Speed is quite decent root@qt5022:~# time ./flashrom -p nicintel_eeprom:pci=03:00.0 -E flashrom v0.9.7-r1622 on Linux 3.11.0-qtec-standard (x86_64) flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OK. Found Programmer flash chip "Opaque flash chip" (32 kB, Programmer-specific) on nicintel_eeprom. Erasing and writing flash chip... Erase/write done. real 0m4.699s user 0m4.676s sys 0m0.024s root@qt5022:~# time ./flashrom -p nicintel_eeprom:pci=03:00.0 -w original.kk flashrom v0.9.7-r1622 on Linux 3.11.0-qtec-standard (x86_64) flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OK. Found Programmer flash chip "Opaque flash chip" (32 kB, Programmer-specific) on nicintel_eeprom. Reading old flash chip contents... done. Erasing and writing flash chip... Erase/write done. Verifying flash... VERIFIED. real 0m3.533s user 0m3.516s sys 0m0.018s Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda(a)gmail.com> --- Makefile | 9 ++ flashrom.c | 12 ++ nicintel_eeprom.c | 329 ++++++++++++++++++++++++++++++++++++++++++++++++++++++ programmer.h | 9 ++ 4 files changed, 359 insertions(+) create mode 100644 nicintel_eeprom.c diff --git a/Makefile b/Makefile index 70ef640..e9d5fbf 100644 --- a/Makefile +++ b/Makefile @@ -396,6 +396,9 @@ CONFIG_NICINTEL ?= yes # Always enable SPI on Intel NICs for now. CONFIG_NICINTEL_SPI ?= yes +# Always enable EEPROM on Intel NICs for now. +CONFIG_NICINTEL_EEPROM ?= yes + # Always enable SPI on OGP cards for now. CONFIG_OGP_SPI ?= yes @@ -560,6 +563,12 @@ PROGRAMMER_OBJS += nicintel_spi.o NEED_PCI := yes endif +ifeq ($(CONFIG_NICINTEL_EEPROM), yes) +FEATURE_CFLAGS += -D'CONFIG_NICINTEL_EEPROM=1' +PROGRAMMER_OBJS += nicintel_eeprom.o +NEED_PCI := yes +endif + ifeq ($(CONFIG_OGP_SPI), yes) FEATURE_CFLAGS += -D'CONFIG_OGP_SPI=1' PROGRAMMER_OBJS += ogp_spi.o diff --git a/flashrom.c b/flashrom.c index a00347e..0cb948b 100644 --- a/flashrom.c +++ b/flashrom.c @@ -273,6 +273,18 @@ const struct programmer_entry programmer_table[] = { }, #endif +#if CONFIG_NICINTEL_EEPROM == 1 + { + .name = "nicintel_eeprom", + .type = PCI, + .devs.dev = nics_intel_ee, + .init = nicintel_ee_init, + .map_flash_region = fallback_map, + .unmap_flash_region = fallback_unmap, + .delay = internal_delay, + }, +#endif + #if CONFIG_OGP_SPI == 1 { .name = "ogp_spi", diff --git a/nicintel_eeprom.c b/nicintel_eeprom.c new file mode 100644 index 0000000..9719c24 --- /dev/null +++ b/nicintel_eeprom.c @@ -0,0 +1,329 @@ +/* + * This file is part of the flashrom project. + * + * Copyright (C) 2013 Ricardo Ribalda - Qtechnology A/S + * + * Based on nicinctel_spi.c and ichspi.c + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* + * Datasheet: Intel 82580 Quad/Dual Gigabit Ethernet LAN Controller Datasheet + */ + +#include <stdlib.h> +#include <unistd.h> +#include "flash.h" +#include "programmer.h" +#include "hwaccess.h" + +#define PCI_VENDOR_ID_INTEL 0x8086 +#define MEMMAP_SIZE getpagesize() + +/* EEPROM/Flash Control & Data Register */ +#define EECD 0x10 +#define EERD 0x14 + +/* Eeprom Access register bits +* Section 8.4.1 +*/ +#define EE_SCK 0 +#define EE_CS 1 +#define EE_SI 2 +#define EE_SO 3 +#define EE_REQ 6 +#define EE_GNT 7 +#define EE_PRES 8 +#define EE_SIZE 11 +#define EE_SIZE_MASK 0xf + +#define EERD_START 0 +#define EERD_DONE 1 +#define EERD_ADDR 2 +#define EERD_DATA 16 + +#define BIT(x) (1<<x) +#define PAGE_MASK 0x3f + +uint8_t *nicintel_eebar; +struct pci_dev *nicintel_pci; + +#define UNPROG_DEVICE 0x1509 + +const struct dev_entry nics_intel_ee[] = { + {PCI_VENDOR_ID_INTEL, 0x150e, OK, "Intel", "82580 Quad/Dual Gigabit Ethernet LAN Controller"}, + {PCI_VENDOR_ID_INTEL, UNPROG_DEVICE, OK, "Intel", "Unprogrammed 82580 Quad/Dual Gigabit Ethernet LAN Controller"}, + {0}, +}; + +static int nicintel_ee_probe(struct flashctx *flash) +{ + if (nicintel_pci->device_id == UNPROG_DEVICE) + flash->chip->total_size = 16; + else{ + uint32_t tmp; + tmp = pci_mmio_readl(nicintel_eebar + EECD); + tmp = ((tmp >> EE_SIZE) & EE_SIZE_MASK); + switch (tmp) { + case 7: + flash->chip->total_size = 16; + break; + case 8: + flash->chip->total_size = 32; + break; + default: + msg_cerr("Non supported chip size 0x%x\n", tmp); + return 0; + } + } + + flash->chip->page_size = PAGE_MASK + 1; + flash->chip->tested = TEST_OK_PREW; + flash->chip->gran = write_gran_1byte; + flash->chip->block_erasers->eraseblocks[0].size = (PAGE_MASK + 1); + flash->chip->block_erasers->eraseblocks[0].count = + (flash->chip->total_size * 1024) / (PAGE_MASK + 1); + + return 1; +} + +#define RETRIES_EERD 10000000 +static int nicintel_ee_read_word(unsigned int daddr, uint16_t * word) +{ + uint32_t tmp; + int i; + + tmp = BIT(EERD_START) + (daddr << EERD_ADDR); + pci_mmio_writel(tmp, nicintel_eebar + EERD); + + for (i = 0; i < RETRIES_EERD; i++) { + tmp = pci_mmio_readl(nicintel_eebar + EERD); + if (tmp & BIT(EERD_DONE)) { + *word = (tmp >> EERD_DATA) & 0xffff; + return 0; + } + } + + return -1; +} + +static int nicintel_ee_read(struct flashctx *flash, uint8_t * buf, + unsigned int addr, unsigned int len) +{ + uint16_t word; + + if (addr & 1) { + if (nicintel_ee_read_word(addr / 2, &word)) + return -1; + *buf++ = word & 0xff; + addr++; + len--; + } + + while (len) { + if (nicintel_ee_read_word(addr / 2, &word)) + return -1; + *buf++ = word & 0xff; + addr++; + len--; + if (len) { + *buf++ = (word >> 8) & 0xff; + addr++; + len--; + } + } + + return 0; +} + +static int nicintel_ee_bitset(int reg, int bit, int val) +{ + uint32_t tmp; + + tmp = pci_mmio_readl(nicintel_eebar + reg); + if (val) + tmp |= BIT(bit); + else + tmp &= ~BIT(bit); + pci_mmio_writel(tmp, nicintel_eebar + reg); + + return -1; +} + +static int nicintel_ee_byte(uint8_t mosi, uint8_t * miso) +{ + int i; + uint8_t out = 0x0; + + for (i = 7; i >= 0; i--) { + nicintel_ee_bitset(EECD, EE_SI, mosi & BIT(i)); + nicintel_ee_bitset(EECD, EE_SCK, 1); + if (miso) { + uint32_t tmp = pci_mmio_readl(nicintel_eebar + EECD); + if (tmp & BIT(EE_SO)) + out |= BIT(i); + } + nicintel_ee_bitset(EECD, EE_SCK, 0); + } + + if (miso) + *miso = out; + + return 0; +} + +#define OPCODE_RDSR 0x5 +#define RETRIES_RDSR 100 +#define RDSR_WIP 0 +static int nicintel_ee_ready() +{ + int i; + uint8_t rdsr; + + nicintel_ee_bitset(EECD, EE_CS, 0); + nicintel_ee_byte(OPCODE_RDSR, NULL); + for (i = 0; i < RETRIES_RDSR; i++) { + nicintel_ee_byte(0x00, &rdsr); + if (!(rdsr & BIT(RDSR_WIP))) { + nicintel_ee_bitset(EECD, EE_CS, 1); + programmer_delay(1); + return 0; + } + } + + nicintel_ee_bitset(EECD, EE_CS, 1); + programmer_delay(1); + + return -1; +} + +static int nicintel_ee_req() +{ + uint32_t tmp; + nicintel_ee_bitset(EECD, EE_REQ, 1); + + tmp = pci_mmio_readl(nicintel_eebar + EECD); + if (!(tmp & BIT(EE_GNT))) { + msg_perr("Enabling eeprom access failed.\n"); + return 1; + } + + nicintel_ee_bitset(EECD, EE_SCK, 0); + return 0; +} + +#define DELAY_WRITE 1000 +#define OPCODE_WRITE 0x2 +#define OPCODE_WREN 0x6 +static int nicintel_ee_write(struct flashctx *flash, uint8_t * buf, + unsigned int addr, unsigned int len) +{ + if (nicintel_ee_req()) + return -1; + + if (nicintel_ee_ready()) { + nicintel_ee_bitset(EECD, EE_REQ, 0); + return -1; + } + + while (len) { + //wren + nicintel_ee_bitset(EECD, EE_CS, 0); + nicintel_ee_byte(OPCODE_WREN, NULL); + nicintel_ee_bitset(EECD, EE_CS, 1); + programmer_delay(1); + + //data + nicintel_ee_bitset(EECD, EE_CS, 0); + nicintel_ee_byte(OPCODE_WRITE, NULL); + nicintel_ee_byte((addr >> 8) & 0xff, NULL); + nicintel_ee_byte(addr & 0xff, NULL); + while (len) { + nicintel_ee_byte((buf) ? *buf++ : 0xff, NULL); + len--; + addr++; + if (!(addr & PAGE_MASK)) + break; + } + nicintel_ee_bitset(EECD, EE_CS, 1); + programmer_delay(1); + if (nicintel_ee_ready()) { + nicintel_ee_bitset(EECD, EE_REQ, 0); + return -1; + } + } + + nicintel_ee_bitset(EECD, EE_REQ, 0); + return 0; +} + +static int nicintel_ee_erase(struct flashctx *flash, unsigned int addr, + unsigned int len) +{ + return nicintel_ee_write(flash, NULL, addr, len); +} + +static const struct opaque_programmer opaque_programmer_nicintel_ee = { + .probe = nicintel_ee_probe, + .read = nicintel_ee_read, + .write = nicintel_ee_write, + .erase = nicintel_ee_erase, +}; + +static int nicintel_spi_shutdown(void *data) +{ + + /* See the comment about EECD in nicintel_ee_init() for details. */ + + return 0; +} + +int nicintel_ee_init(void) +{ + struct pci_dev *dev = NULL; + uint32_t tmp; + + if (rget_io_perms()) + return 1; + + dev = pcidev_init(nics_intel_ee, PCI_BASE_ADDRESS_0); + if (!dev) + return 1; + + io_base_addr = pcidev_readbar(dev, PCI_BASE_ADDRESS_0); + if (!io_base_addr) + return 1; + + nicintel_eebar = rphysmap("Intel Gigabit NIC w/ SPI EEPROM", + io_base_addr, MEMMAP_SIZE); + nicintel_pci=dev; + /* Automatic restore of EECD on shutdown is not possible because EECD + * does not only contain EE_REQ but other bits with side effects as well. + * Those other bits must be left untouched. + */ + if (dev->device_id != UNPROG_DEVICE) { + tmp = pci_mmio_readl(nicintel_eebar + EECD); + + if (!(tmp & BIT(EE_PRES))) { + msg_perr("EEprom not present.\n"); + return 1; + } + } + + if (register_shutdown(nicintel_spi_shutdown, NULL)) + return 1; + + return register_opaque_programmer(&opaque_programmer_nicintel_ee); +} diff --git a/programmer.h b/programmer.h index f792d9a..dcf9911 100644 --- a/programmer.h +++ b/programmer.h @@ -78,6 +78,9 @@ enum programmer { #if CONFIG_NICINTEL_SPI == 1 PROGRAMMER_NICINTEL_SPI, #endif +#if CONFIG_NICINTEL_EEPROM == 1 + PROGRAMMER_NICINTEL_EEPROM, +#endif #if CONFIG_OGP_SPI == 1 PROGRAMMER_OGP_SPI, #endif @@ -406,6 +409,12 @@ int nicintel_spi_init(void); extern const struct dev_entry nics_intel_spi[]; #endif +/* nicintel_eeprom.c */ +#if CONFIG_NICINTEL_EEPROM == 1 +int nicintel_ee_init(void); +extern const struct dev_entry nics_intel_ee[]; +#endif + /* ogp_spi.c */ #if CONFIG_OGP_SPI == 1 int ogp_spi_init(void); -- 1.8.4.rc3

2 3

[PATCH v2] nicintel_eeprom: New programmer for Intel Nics eeproms
by Ricardo Ribalda Delgado 12 May '14

12 May '14

This patch let you read and write the eeprom on your gigagit nic card. So far it has been tested on the 82580 NIC, but there should be other boards also compatibles. It is a nice substitution for the eeupdate tool. Speed is quite decent root@qt5022:~# time ./flashrom -p nicintel_eeprom:pci=03:00.0 -E flashrom v0.9.7-r1622 on Linux 3.11.0-qtec-standard (x86_64) flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OK. Found Programmer flash chip "Opaque flash chip" (32 kB, Programmer-specific) on nicintel_eeprom. Erasing and writing flash chip... Erase/write done. real 0m4.699s user 0m4.676s sys 0m0.024s root@qt5022:~# time ./flashrom -p nicintel_eeprom:pci=03:00.0 -w original.kk flashrom v0.9.7-r1622 on Linux 3.11.0-qtec-standard (x86_64) flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OK. Found Programmer flash chip "Opaque flash chip" (32 kB, Programmer-specific) on nicintel_eeprom. Reading old flash chip contents... done. Erasing and writing flash chip... Erase/write done. Verifying flash... VERIFIED. real 0m3.533s user 0m3.516s sys 0m0.018s Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda(a)gmail.com> --- v2: -Changes by Stefan Tauner -Manpage Makefile | 9 ++ flashrom.8.tmpl | 6 +- flashrom.c | 12 ++ nicintel_eeprom.c | 336 ++++++++++++++++++++++++++++++++++++++++++++++++++++++ programmer.h | 9 ++ 5 files changed, 370 insertions(+), 2 deletions(-) create mode 100644 nicintel_eeprom.c diff --git a/Makefile b/Makefile index 346d46a..c412bdc 100644 --- a/Makefile +++ b/Makefile @@ -408,6 +408,9 @@ CONFIG_NICINTEL ?= yes # Always enable SPI on Intel NICs for now. CONFIG_NICINTEL_SPI ?= yes +# Always enable EEPROM on Intel NICs for now. +CONFIG_NICINTEL_EEPROM ?= yes + # Always enable SPI on OGP cards for now. CONFIG_OGP_SPI ?= yes @@ -592,6 +595,12 @@ PROGRAMMER_OBJS += nicintel_spi.o NEED_PCI := yes endif +ifeq ($(CONFIG_NICINTEL_EEPROM), yes) +FEATURE_CFLAGS += -D'CONFIG_NICINTEL_EEPROM=1' +PROGRAMMER_OBJS += nicintel_eeprom.o +NEED_PCI := yes +endif + ifeq ($(CONFIG_OGP_SPI), yes) FEATURE_CFLAGS += -D'CONFIG_OGP_SPI=1' PROGRAMMER_OBJS += ogp_spi.o diff --git a/flashrom.8.tmpl b/flashrom.8.tmpl index 8d46ffe..6d400b4 100644 --- a/flashrom.8.tmpl +++ b/flashrom.8.tmpl @@ -221,6 +221,8 @@ bitbanging adapter) .sp .BR "* usbblaster_spi" " (for SPI flash ROMs attached to an Altera USB-Blaster compatible cable)" .sp +.BR "* nicintel_eeprom" " (for SPI EEPROMs on Intel Gigabit network cards)" +.sp Some programmers have optional or mandatory parameters which are described in detail in the .B PROGRAMMER SPECIFIC INFO @@ -566,9 +568,9 @@ syntax where .B content is an 8-bit hexadecimal value. .SS -.BR "nic3com" , " nicrealtek" , " nicnatsemi" , " nicintel\ +.BR "nic3com" , " nicrealtek" , " nicnatsemi" , " nicintel", " nicintel_eeprom\ " , " nicintel_spi" , " gfxnvidia" , " ogp_spi" , " drkaiser" , " satasii\ -" , " satamv" ", and " atahpt " programmers +" , " satamv", ", and " atahpt " programmers These programmers have an option to specify the PCI address of the card your want to use, which must be specified if more than one card supported by the selected programmer is installed in your system. The syntax is diff --git a/flashrom.c b/flashrom.c index b3661c1..1b0a687 100644 --- a/flashrom.c +++ b/flashrom.c @@ -273,6 +273,18 @@ const struct programmer_entry programmer_table[] = { }, #endif +#if CONFIG_NICINTEL_EEPROM == 1 + { + .name = "nicintel_eeprom", + .type = PCI, + .devs.dev = nics_intel_ee, + .init = nicintel_ee_init, + .map_flash_region = fallback_map, + .unmap_flash_region = fallback_unmap, + .delay = internal_delay, + }, +#endif + #if CONFIG_OGP_SPI == 1 { .name = "ogp_spi", diff --git a/nicintel_eeprom.c b/nicintel_eeprom.c new file mode 100644 index 0000000..c80be37 --- /dev/null +++ b/nicintel_eeprom.c @@ -0,0 +1,336 @@ +/* + * This file is part of the flashrom project. + * + * Copyright (C) 2013 Ricardo Ribalda - Qtechnology A/S + * Copyright (C) 2011, 2014 Stefan Tauner + * + * Based on nicinctel_spi.c and ichspi.c + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +/* + * Datasheet: Intel 82580 Quad/Dual Gigabit Ethernet LAN Controller Datasheet + * Section 7.4: Register Descriptions + */ + +#include <stdlib.h> +#include <unistd.h> +#include "flash.h" +#include "spi.h" +#include "programmer.h" +#include "hwaccess.h" + +#define PCI_VENDOR_ID_INTEL 0x8086 +#define MEMMAP_SIZE (0x14 + 3) /* Only EEC and EERD are needed. */ + +#define EEC 0x10 /* EEPROM/Flash Control Register */ +#define EERD 0x14 /* EEPROM Read Register */ + +/* EPROM/Flash Control Register bits */ +#define EE_SCK 0 +#define EE_CS 1 +#define EE_SI 2 +#define EE_SO 3 +#define EE_REQ 6 +#define EE_GNT 7 +#define EE_PRES 8 +#define EE_SIZE 11 +#define EE_SIZE_MASK 0xf + +/* EEPROM Read Register bits */ +#define EERD_START 0 +#define EERD_DONE 1 +#define EERD_ADDR 2 +#define EERD_DATA 16 + +#define BIT(x) (1<<x) +#define PAGE_MASK 0x3f + +static uint8_t *nicintel_eebar; +static struct pci_dev *nicintel_pci; + +#define UNPROG_DEVICE 0x1509 + +const struct dev_entry nics_intel_ee[] = { + {PCI_VENDOR_ID_INTEL, 0x150e, OK, "Intel", + "82580 Quad/Dual Gigabit Ethernet LAN Controller"}, + {PCI_VENDOR_ID_INTEL, UNPROG_DEVICE, OK, "Intel", + "Unprogrammed 82580 Quad/Dual " + "Gigabit Ethernet LAN Controller"}, + {0}, +}; + +static int nicintel_ee_probe(struct flashctx *flash) +{ + if (nicintel_pci->device_id == UNPROG_DEVICE) + flash->chip->total_size = 16; + else{ + uint32_t tmp = pci_mmio_readl(nicintel_eebar + EEC); + tmp = ((tmp >> EE_SIZE) & EE_SIZE_MASK); + switch (tmp) { + case 7: + flash->chip->total_size = 16; + break; + case 8: + flash->chip->total_size = 32; + break; + default: + msg_cerr("Unsupported chip size 0x%x\n", tmp); + return 0; + } + } + + flash->chip->page_size = PAGE_MASK + 1; + flash->chip->tested = TEST_OK_PREW; + /* FIXME: Due to the write_granularity set below we do 0xFF dummy + * writes to fake erases on every write which is completely pointless + * and potentially even harmful for the hardware. Programmers/devices + * should be able to indicate that erases are not needed for writes. */ + flash->chip->gran = write_gran_1byte; + flash->chip->block_erasers->eraseblocks[0].size = (PAGE_MASK + 1); + flash->chip->block_erasers->eraseblocks[0].count = + (flash->chip->total_size * 1024) / (PAGE_MASK + 1); + + return 1; +} + +static int nicintel_ee_read_word(unsigned int addr, uint16_t *word) +{ + uint32_t tmp = BIT(EERD_START) | (addr << EERD_ADDR); + uint32_t i; + + pci_mmio_writel(tmp, nicintel_eebar + EERD); + + /* Poll done flag */ + for (i = 0; i < 10000000; i++) { + tmp = pci_mmio_readl(nicintel_eebar + EERD); + if (tmp & BIT(EERD_DONE)) { + *word = (tmp >> EERD_DATA) & 0xffff; + return 0; + } + } + + return -1; +} + +static int nicintel_ee_read(struct flashctx *flash, uint8_t *buf, + unsigned int addr, unsigned int len) +{ + uint16_t word; + + /* The NIC interface always reads 16 b words so we need to convert the + * address and handle odd address explicitly at the start (and also + * at the end in the loop below). */ + if (addr & 1) { + if (nicintel_ee_read_word(addr / 2, &word)) + return -1; + *buf++ = word & 0xff; + addr++; + len--; + } + + while (len > 0) { + if (nicintel_ee_read_word(addr / 2, &word)) + return -1; + *buf++ = word & 0xff; + addr++; + len--; + if (len > 0) { + *buf++ = (word >> 8) & 0xff; + addr++; + len--; + } + } + + return 0; +} + +static int nicintel_ee_bitset(int reg, int bit, bool val) +{ + uint32_t tmp; + + tmp = pci_mmio_readl(nicintel_eebar + reg); + if (val) + tmp |= BIT(bit); + else + tmp &= ~BIT(bit); + pci_mmio_writel(tmp, nicintel_eebar + reg); + + return -1; +} + +static int nicintel_ee_byte(uint8_t mosi, uint8_t *miso) +{ + int i; + uint8_t out = 0x0; + + for (i = 7; i >= 0; i--) { + nicintel_ee_bitset(EEC, EE_SI, mosi & BIT(i)); + nicintel_ee_bitset(EEC, EE_SCK, 1); + if (miso != NULL) { + uint32_t tmp = pci_mmio_readl(nicintel_eebar + EEC); + if (tmp & BIT(EE_SO)) + out |= BIT(i); + } + nicintel_ee_bitset(EEC, EE_SCK, 0); + } + + if (miso != NULL) + *miso = out; + + return 0; +} + +static int nicintel_ee_ready(void) +{ + unsigned int i; + + for (i = 0; i < 1000; i++) { + uint8_t rdsr; + + nicintel_ee_bitset(EEC, EE_CS, 0); + nicintel_ee_byte(JEDEC_RDSR, NULL); + nicintel_ee_byte(0x00, &rdsr); + nicintel_ee_bitset(EEC, EE_CS, 1); + programmer_delay(1); + if (!(rdsr & SPI_SR_WIP)) + return 0; + } + + return -1; +} + +static int nicintel_ee_req(void) +{ + uint32_t tmp; + nicintel_ee_bitset(EEC, EE_REQ, 1); + + tmp = pci_mmio_readl(nicintel_eebar + EEC); + if (!(tmp & BIT(EE_GNT))) { + msg_perr("Enabling eeprom access failed.\n"); + return 1; + } + + nicintel_ee_bitset(EEC, EE_SCK, 0); + return 0; +} + +static int nicintel_ee_write(struct flashctx *flash, const uint8_t *buf, + unsigned int addr, unsigned int len) +{ + if (nicintel_ee_req()) + return -1; + + int ret = -1; + if (nicintel_ee_ready()) + goto out; + + while (len > 0) { + /*wren*/ + nicintel_ee_bitset(EEC, EE_CS, 0); + nicintel_ee_byte(JEDEC_WREN, NULL); + nicintel_ee_bitset(EEC, EE_CS, 1); + programmer_delay(1); + + /*data*/ + nicintel_ee_bitset(EEC, EE_CS, 0); + nicintel_ee_byte(JEDEC_BYTE_PROGRAM, NULL); + nicintel_ee_byte((addr >> 8) & 0xff, NULL); + nicintel_ee_byte(addr & 0xff, NULL); + while (len > 0) { + nicintel_ee_byte((buf) ? *buf++ : 0xff, NULL); + len--; + addr++; + if (!(addr & PAGE_MASK)) + break; + } + nicintel_ee_bitset(EEC, EE_CS, 1); + programmer_delay(1); + if (nicintel_ee_ready()) + goto out; + } + ret = 0; +out: + nicintel_ee_bitset(EEC, EE_REQ, 0); + return ret; +} + +static int nicintel_ee_erase(struct flashctx *flash, unsigned int addr, + unsigned int len) +{ + return nicintel_ee_write(flash, NULL, addr, len); +} + +static const struct opaque_programmer opaque_programmer_nicintel_ee = { + .probe = nicintel_ee_probe, + .read = nicintel_ee_read, + .write = nicintel_ee_write, + .erase = nicintel_ee_erase, +}; + +static int nicintel_spi_shutdown(void *eecp) +{ + int ret; + uint32_t old_eec = *(uint32_t *)eecp; + + /* Request bitbanging and unselect the chip first to be safe. */ + if (nicintel_ee_req() || nicintel_ee_bitset(EEC, EE_CS, 1)) + return -1; + + /* Try to restore individual bits we care about. */ + ret = nicintel_ee_bitset(EEC, EE_SCK, old_eec & BIT(EE_SCK)); + ret |= nicintel_ee_bitset(EEC, EE_SI, old_eec & BIT(EE_SI)); + ret |= nicintel_ee_bitset(EEC, EE_CS, old_eec & BIT(EE_CS)); + ret |= nicintel_ee_bitset(EEC, EE_REQ, old_eec & BIT(EE_REQ)); + + free(eecp); + return ret; +} + +int nicintel_ee_init(void) +{ + struct pci_dev *dev; + + if (rget_io_perms()) + return 1; + + dev = pcidev_init(nics_intel_ee, PCI_BASE_ADDRESS_0); + if (!dev) + return 1; + + io_base_addr = pcidev_readbar(dev, PCI_BASE_ADDRESS_0); + if (!io_base_addr) + return 1; + + nicintel_eebar = rphysmap("Intel Gigabit NIC w/ SPI EEPROM", + io_base_addr, MEMMAP_SIZE); + nicintel_pci = dev; + if (dev->device_id != UNPROG_DEVICE) { + uint32_t eec = pci_mmio_readl(nicintel_eebar + EEC); + uint32_t *eecp; + + if (!(eec & BIT(EE_PRES))) { + msg_perr("EEPROM not present.\n"); + return 1; + } + + eecp = malloc(sizeof(uint32_t)); + if (eecp == NULL) + return 1; + *eecp = eec; + + if (register_shutdown(nicintel_spi_shutdown, eecp)) + return 1; + } + + return register_opaque_programmer(&opaque_programmer_nicintel_ee); +} diff --git a/programmer.h b/programmer.h index 7670784..84a4c68 100644 --- a/programmer.h +++ b/programmer.h @@ -78,6 +78,9 @@ enum programmer { #if CONFIG_NICINTEL_SPI == 1 PROGRAMMER_NICINTEL_SPI, #endif +#if CONFIG_NICINTEL_EEPROM == 1 + PROGRAMMER_NICINTEL_EEPROM, +#endif #if CONFIG_OGP_SPI == 1 PROGRAMMER_OGP_SPI, #endif @@ -410,6 +413,12 @@ int nicintel_spi_init(void); extern const struct dev_entry nics_intel_spi[]; #endif +/* nicintel_eeprom.c */ +#if CONFIG_NICINTEL_EEPROM == 1 +int nicintel_ee_init(void); +extern const struct dev_entry nics_intel_ee[]; +#endif + /* ogp_spi.c */ #if CONFIG_OGP_SPI == 1 int ogp_spi_init(void); -- 2.0.0.rc0

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Re: [flashrom] Flashrom verbose log
by Stefan Tauner 12 May '14

12 May '14

Hello Rajiv, can you please send us the log file created by flashrom -p internal -VV -o probe.log This redirects more output directly into the file "probe.log" and allows us to investigate the problem better. Thank you. -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

2 1

at45db buffer overflow
by degener_trash＠mail.ru 10 May '14

10 May '14

I found buffer overflow at at45db module. Error was in chunk length calculation. Patch is attached. Chip AT45DB041D: reading, writing and erasing operations works correctly. Best regards, Alexander Irenkov

3 4

Re: [flashrom] [PATCH] Refine messages related to erase/write recovery.
by Stefan Tauner 10 May '14

10 May '14

On Wed, 7 Aug 2013 17:07:47 +0200 Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> wrote: > We are more verbose inside erase_and_write_flash() although it does not > matter as much as here - at the end of the process. > > New output for the non-fatal (i.e. read-protected + successful read) case: > > Reading old flash chip contents... done. > Erasing and writing flash chip... spi_block_erase_d8 failed during command execution at address 0x8000 > Reading current flash chip contents... done. spi_chip_erase_c7 failed during command execution > FAILED! > Uh oh. Erase/write failed. Checking if anything has changed. > Reading current flash chip contents... done. > Good. Writing to the flash chip apparently didn't do anything. > Please check the connections (especially those to write protection pins) between > the programmer and the flash chip. If you think the error is caused by flashrom > please report this on IRC at chat.freenode.net (channel #flashrom) or > mail flashrom(a)flashrom.org, thanks! > > Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Slightly refined, Acked-by: Stefan Tauner <stefan.tauner(a)alumni.tuwien.ac.at> and committed in r1790. -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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[commit] r1790 - trunk
by repository service 10 May '14

10 May '14

Author: stefanct Date: Sat May 10 11:25:44 2014 New Revision: 1790 URL: http://flashrom.org/trac/flashrom/changeset/1790 Log: Refine messages related to erase/write recovery. We are more verbose inside erase_and_write_flash() although it does not matter as much as at the end of the whole process in doit(). New output for the non-fatal (i.e. read-protected + successful recovery read) case: Reading old flash chip contents... done. Erasing and writing flash chip... spi_block_erase_d8 failed during command execution at address 0x8000 Reading current flash chip contents... done. spi_chip_erase_c7 failed during command execution FAILED! Uh oh. Erase/write failed. Checking if anything has changed. Reading current flash chip contents... done. Good, writing to the flash chip apparently didn't do anything. Please check the connections (especially those to write protection pins) between the programmer and the flash chip. If you think the error is caused by flashrom please report this on IRC at chat.freenode.net (channel #flashrom) or mail flashrom(a)flashrom.org, thanks! Signed-off-by: Stefan Tauner <stefan.tauner(a)alumni.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner(a)alumni.tuwien.ac.at> Modified: trunk/flashrom.c Modified: trunk/flashrom.c ============================================================================== --- trunk/flashrom.c Fri May 9 23:16:21 2014 (r1789) +++ trunk/flashrom.c Sat May 10 11:25:44 2014 (r1790) @@ -1521,7 +1521,7 @@ static void nonfatal_help_message(void) { - msg_gerr("Writing to the flash chip apparently didn't do anything.\n"); + msg_gerr("Good, writing to the flash chip apparently didn't do anything.\n"); #if CONFIG_INTERNAL == 1 if (programmer == PROGRAMMER_INTERNAL) msg_gerr("This means we have to add special support for your board, programmer or flash\n" @@ -2008,16 +2008,18 @@ if (write_it) { if (erase_and_write_flash(flash, oldcontents, newcontents)) { - msg_cerr("Uh oh. Erase/write failed. Checking if " - "anything changed.\n"); + msg_cerr("Uh oh. Erase/write failed. Checking if anything has changed.\n"); + msg_cinfo("Reading current flash chip contents... "); if (!flash->chip->read(flash, newcontents, 0, size)) { + msg_cinfo("done.\n"); if (!memcmp(oldcontents, newcontents, size)) { - msg_cinfo("Good. It seems nothing was changed.\n"); nonfatal_help_message(); ret = 1; goto out; } - } + msg_cerr("Apparently at least some data has changed.\n"); + } else + msg_cerr("Can't even read anymore!\n"); emergency_help_message(); ret = 1; goto out;

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