flashrom

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9161 discussions

WinBond Chip Support
by Jordan Hill 17 Apr '18

17 Apr '18

Hello there, I have a Dell Inspiron 5559 Laptop which contains a Winbond 25Q128FVSQ Chip. I tried running flashrom natively on the laptop and got the usual EC warning so i stopped there. I then desoldered the SMD chip off the motherboard and hooked it up to a RPI and connected it through the SPI protocol. Flashrom then recognized it as a "Generic" flash chip and would not allow the data to be read as it was still unrecognized. Unfortunately I do not have any logs. I believe that this chip is on the list of supported hardware yet it was not recognized in flashrom. I am using the latest version as of April 18th 2018. Any suggestions or help would be appreciated. Thank You

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Re: [flashrom] no spi flash IS25LP128
by Nico Huber 17 Apr '18

17 Apr '18

On 16.04.2018 05:07, 山中老虎 wrote: > no spi flash IS25LP128 This chip is supported on our master branch only. You'd have to clone the repository and build flashrom yourself, see [1]. Nico PS. Please don't send unnecessary large attachments to the mailing list. [1] https://flashrom.org/Downloads

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As requested, W25Q256.V works perfectly with Bus Pirate
by Richard Hughes 04 Apr '18

04 Apr '18

Using git master: Using clock_gettime for delay loops (clk_id: 1, resolution: 1ns). Bus Pirate firmware 6.1 and older does not support SPI speeds above 2 MHz. Limiting speed to 2 MHz. It is recommended to upgrade to firmware 6.2 or newer. Found Winbond flash chip "W25Q256.V" (32768 kB, SPI) on buspirate_spi. === This flash part has status UNTESTED for operations: PROBE READ ERASE WRITE The test status of this chip may have been updated in the latest development version of flashrom. If you are running the latest development version, please email a report to flashrom(a)flashrom.org if any of the above operations work correctly for you with this flash chip. Please include the flashrom log file for all operations you tested (see the man page for details), and mention which mainboard or programmer you tested in the subject line. Thanks for your help! Reading old flash chip contents... done. Erasing and writing flash chip... Erase/write done. Verifying flash... VERIFIED. Richard.

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NVIDIA CK804: TYAN VX50 B4985: unexpected second chipset match: "NVIDIA CK804"
by Paul Menzel 03 Apr '18

03 Apr '18

Dear flashrom folks, As asked by flashrom, here is the output for the TYAN VX50 B4985 [1]. ``` $ sudo flashrom -p internal flashrom v1.0 on Linux 4.14.30.mx64.211 (x86_64) flashrom is free software, get the source code at https://flashrom.org Using clock_gettime for delay loops (clk_id: 1, resolution: 1ns). Found chipset "NVIDIA CK804". Enabling flash write... OK. Warning: unexpected second chipset match: "NVIDIA CK804" ignoring, please report lspci and board URL to flashrom(a)flashrom.org with 'CHIPSET: your board name' in the subject line. Found SST flash chip "SST49LF080A" (1024 kB, LPC) mapped at physical address 0x00000000fff00000. No operations were specified. $ lspci 00:00.0 Memory controller: NVIDIA Corporation CK804 Memory Controller (rev a4) 00:01.0 ISA bridge: NVIDIA Corporation CK804 ISA Bridge (rev f1) 00:01.1 SMBus: NVIDIA Corporation CK804 SMBus (rev a2) 00:02.0 USB controller: NVIDIA Corporation CK804 USB Controller (rev a2) 00:02.1 USB controller: NVIDIA Corporation CK804 USB Controller (rev a4) 00:06.0 IDE interface: NVIDIA Corporation CK804 IDE (rev f3) 00:07.0 IDE interface: NVIDIA Corporation CK804 Serial ATA Controller (rev f3) 00:08.0 IDE interface: NVIDIA Corporation CK804 Serial ATA Controller (rev f3) 00:09.0 PCI bridge: NVIDIA Corporation CK804 PCI Bridge (rev f2) 00:0a.0 Bridge: NVIDIA Corporation CK804 Ethernet Controller (rev f3) 00:0b.0 PCI bridge: NVIDIA Corporation CK804 PCIE Bridge (rev f3) 00:0c.0 PCI bridge: NVIDIA Corporation CK804 PCIE Bridge (rev f3) 00:0d.0 PCI bridge: NVIDIA Corporation CK804 PCIE Bridge (rev f3) 00:0e.0 PCI bridge: NVIDIA Corporation CK804 PCIE Bridge (rev a3) 00:18.0 Host bridge: Advanced Micro Devices, Inc. [AMD] Family 10h Processor HyperTransport Configuration 00:18.1 Host bridge: Advanced Micro Devices, Inc. [AMD] Family 10h Processor Address Map 00:18.2 Host bridge: Advanced Micro Devices, Inc. [AMD] Family 10h Processor DRAM Controller 00:18.3 Host bridge: Advanced Micro Devices, Inc. [AMD] Family 10h Processor Miscellaneous Control 00:18.4 Host bridge: Advanced Micro Devices, Inc. [AMD] Family 10h Processor Link Control 00:19.0 Host bridge: Advanced Micro Devices, Inc. [AMD] Family 10h Processor HyperTransport Configuration 00:19.1 Host bridge: Advanced Micro Devices, Inc. [AMD] Family 10h Processor Address Map 00:19.2 Host bridge: Advanced Micro Devices, Inc. [AMD] Family 10h Processor DRAM Controller 00:19.3 Host bridge: Advanced Micro Devices, Inc. [AMD] Family 10h Processor Miscellaneous Control 00:19.4 Host bridge: Advanced Micro Devices, Inc. [AMD] Family 10h Processor Link Control 00:1a.0 Host bridge: Advanced Micro Devices, Inc. [AMD] Family 10h Processor HyperTransport Configuration 00:1a.1 Host bridge: Advanced Micro Devices, Inc. [AMD] Family 10h Processor Address Map 00:1a.2 Host bridge: Advanced Micro Devices, Inc. [AMD] Family 10h Processor DRAM Controller 00:1a.3 Host bridge: Advanced Micro Devices, Inc. [AMD] Family 10h Processor Miscellaneous Control 00:1a.4 Host bridge: Advanced Micro Devices, Inc. [AMD] Family 10h Processor Link Control 00:1b.0 Host bridge: Advanced Micro Devices, Inc. [AMD] Family 10h Processor HyperTransport Configuration 00:1b.1 Host bridge: Advanced Micro Devices, Inc. [AMD] Family 10h Processor Address Map 00:1b.2 Host bridge: Advanced Micro Devices, Inc. [AMD] Family 10h Processor DRAM Controller 00:1b.3 Host bridge: Advanced Micro Devices, Inc. [AMD] Family 10h Processor Miscellaneous Control 00:1b.4 Host bridge: Advanced Micro Devices, Inc. [AMD] Family 10h Processor Link Control 00:1c.0 Host bridge: Advanced Micro Devices, Inc. [AMD] Family 10h Processor HyperTransport Configuration 00:1c.1 Host bridge: Advanced Micro Devices, Inc. [AMD] Family 10h Processor Address Map 00:1c.2 Host bridge: Advanced Micro Devices, Inc. [AMD] Family 10h Processor DRAM Controller 00:1c.3 Host bridge: Advanced Micro Devices, Inc. [AMD] Family 10h Processor Miscellaneous Control 00:1c.4 Host bridge: Advanced Micro Devices, Inc. [AMD] Family 10h Processor Link Control 00:1d.0 Host bridge: Advanced Micro Devices, Inc. [AMD] Family 10h Processor HyperTransport Configuration 00:1d.1 Host bridge: Advanced Micro Devices, Inc. [AMD] Family 10h Processor Address Map 00:1d.2 Host bridge: Advanced Micro Devices, Inc. [AMD] Family 10h Processor DRAM Controller 00:1d.3 Host bridge: Advanced Micro Devices, Inc. [AMD] Family 10h Processor Miscellaneous Control 00:1d.4 Host bridge: Advanced Micro Devices, Inc. [AMD] Family 10h Processor Link Control 00:1e.0 Host bridge: Advanced Micro Devices, Inc. [AMD] Family 10h Processor HyperTransport Configuration 00:1e.1 Host bridge: Advanced Micro Devices, Inc. [AMD] Family 10h Processor Address Map 00:1e.2 Host bridge: Advanced Micro Devices, Inc. [AMD] Family 10h Processor DRAM Controller 00:1e.3 Host bridge: Advanced Micro Devices, Inc. [AMD] Family 10h Processor Miscellaneous Control 00:1e.4 Host bridge: Advanced Micro Devices, Inc. [AMD] Family 10h Processor Link Control 00:1f.0 Host bridge: Advanced Micro Devices, Inc. [AMD] Family 10h Processor HyperTransport Configuration 00:1f.1 Host bridge: Advanced Micro Devices, Inc. [AMD] Family 10h Processor Address Map 00:1f.2 Host bridge: Advanced Micro Devices, Inc. [AMD] Family 10h Processor DRAM Controller 00:1f.3 Host bridge: Advanced Micro Devices, Inc. [AMD] Family 10h Processor Miscellaneous Control 00:1f.4 Host bridge: Advanced Micro Devices, Inc. [AMD] Family 10h Processor Link Control 01:06.0 Ethernet controller: Intel Corporation 82541GI Gigabit Ethernet Controller (rev 05) 01:09.0 VGA compatible controller: XGI Technology Inc. (eXtreme Graphics Innovation) Z7/Z9 (XG20 core) 05:00.0 RAID bus controller: 3ware Inc 9650SE SATA-II RAID PCIe (rev 01) 0a:00.0 RAID bus controller: 3ware Inc 9690SA SAS/SATA-II RAID PCIe (rev 01) 80:00.0 Memory controller: NVIDIA Corporation CK804 Memory Controller (rev a4) 80:01.0 Memory controller: NVIDIA Corporation CK804 Memory Controller (rev f1) 80:0a.0 Bridge: NVIDIA Corporation CK804 Ethernet Controller (rev f3) 80:0b.0 PCI bridge: NVIDIA Corporation CK804 PCIE Bridge (rev f3) 80:0c.0 PCI bridge: NVIDIA Corporation CK804 PCIE Bridge (rev f3) 80:0d.0 PCI bridge: NVIDIA Corporation CK804 PCIE Bridge (rev f3) 80:0e.0 PCI bridge: NVIDIA Corporation CK804 PCIE Bridge (rev a3) ``` Kind regards, Paul [1] https://www.tyan.com/Barebones_VX50B4985_Transport%20VX50

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Re: [flashrom] Winbond 25Q40EWNIG
by Nico Huber 30 Mar '18

30 Mar '18

Hello Matt, your mail never made it to the list, due to it's excessive size. Please don't send such huge attachments. On 20.03.2018 00:10, Matt Risen wrote: > Is there any chance we could get support for the Winbond 25Q40EWNIG SPI > eeprom? Yes, we recently added support for the next bigger version 25Q80EW, and I just pushed a patch for 25Q40EW [1]. With Git, you can fetch / apply it as follows: git fetch https://review.coreboot.org/flashrom refs/changes/62/25462/1 git cherry-pick FETCH_HEAD It's still untested, though. Nico [1] https://review.coreboot.org/25462/

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Re: [flashrom] Can't Flash on AOpen i965GMt-LA motherboard
by Luc Verhaegen 29 Mar '18

29 Mar '18

On Wed, Mar 28, 2018 at 04:24:25PM +0200, Idwer Vollering wrote: > I took the liberty to submit this change to gerrit; > https://review.coreboot.org/#/c/flashrom/+/25396/ Please fix the author. Luc Verhaegen.

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Re: [flashrom] Can't Flash on AOpen i965GMt-LA motherboard
by Luc Verhaegen 28 Mar '18

28 Mar '18

On Tue, Mar 20, 2018 at 12:22:02PM +0100, Björn Tantau wrote: > > > Am 19. März 2018 18:21:36 MEZ schrieb Luc Verhaegen <libv(a)skynet.be>: > >On Mon, Mar 19, 2018 at 05:01:06PM +0100, Björn Tantau wrote: > >> Am 19.03.2018 um 00:08 schrieb Luc Verhaegen: > >> > > >> >My current hypothesis: smsc at 0x480 > >> > > >> >Action required: 0x48E |= 0x10. > > > >> Do you want to scan for Super I/O sensors? (YES/no): Probing for > >Super-I/O at 0x2e/0x2f > >> Trying family `VIA/Winbond/Nuvoton/Fintek'... Yes > >> Found `Winbond W83627DHG Super IO Sensors' Success! > >> (address 0x290, driver `w83627ehf') > > > >Hrm. Perpendicular to what the bios that i got from AOpen tells me. > > > >Please mail a copy of your existing rom to me personally (exclude the > >flashrom ml, binary blobs should not go there). > > Here you go. Thanks for your help! Ok, this shows how rusty i am with respect to flashrom. Not recognizing the + 0x0C as the typical offset for intel gpio line toggle. What this board needs is a call to intel_ich_gpio20_raise(); Will provide a patch later today. I am a bit worried though that the lpc io BAR is empty in your lspci. I am not sure whether that is handled in any way, and i do not think the intel gpio code in flashrom will deal with an empty bar gracefully. Luc Verhaegen.

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In situ Thinkpad E420 Sandy Bridge/Cougar Point PCH
by awokd 24 Mar '18

24 Mar '18

Having trouble getting a good read from a Macronix MX25L3206E in situ Thinkpad E420 Sandy Bridge/Cougar Point PCH. Don't believe it's a programmer problem because I used the same programmer and pinouts to successfully flash a Winbond W25Q32.V in a different system. I found the Wistron LLW-1/LGG-1 schematic and matched the flash chip up with the silk-screened label. Tried it in system with system power. I've pulled the board and RAM. Also tried removing CPU. Symptoms of the problem are: - On system power, doesn't detect chip. - Using an external PS, when I restrict the current to the point there's a vdroop to ~3.0v-3.2v, flashrom detects the chip. If I give it more current (at 3.3v), the chip disappears and flashrom no longer sees it. - Occasionally it acts like a successful read, WRSR updates correctly but resulting file is mostly FF with a section of pages of 00 and some with alternating bit patterns. Oddly, the file is consistent over multiple runs and diff reports no differences, but there is nothing in it that looks like actual data and ifdtool says there's no descriptor. Suspect the issue is as described on https://www.flashrom.org/ISP- that ME is getting powered and locking/hiding the chip. It suggests connecting the reset line to CS. Searching the schematic for RST results in numerous pages. How can I identify the right place to accomplish this, preferably without soldering? Alternatively, I see in the SPI programming guide there might be a couple other ways to disable ME? 1. Temporarily disable the Intel® ME through the MEBX. Power off or cold reset. - This option is only applicable to non-Intel ME Ignition firmware. 2. HDA_SDO(Manufacturing mode jumper or Flash descriptor override jumper) asserted HIGH on the rising edge of PWROK. Power off or cold reset. Note: this is only valid as long as you do not specifically set the variable Flash Descriptor Overrride Pin-Strap Ignore in the Flash Image Tool to false. I found #2 on the schematic with a not installed resistor (what does "DY" stand for anyways, "Damn You"?) but can't find the label for it on the motherboard and it looked like it would also need soldering beyond my capability. Any suggestions?

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Re: [flashrom] Thinkpad T420
by Ivan Ivanov 22 Mar '18

22 Mar '18

Sorry for late reply. Yes, it looks like your connection is bad. Try using the shorter wires, and hopefully of a good quality ( e.g. pure copper wires could be 1.5 longer than the cheap aluminium wires and still have the same conductivity given the same internal thickness ) You have mentioned that you have updated the Bus Pirate firmware. To what version did you upgrade? I always recommend upgrading to the latest Bus Pirate community firmware (the old official one is dead) You could obtain it here - https://github.com/BusPirate/Bus_Pirate Alternatively, you may try a $3 very cheap CH341A USB programmer, which is also supported by flashrom project and has a much simpler hardware, i.e. it does not have the internal firmware, just a tiny EEPROM of 20 or 32 bytes size + 8 bit CFG register. The board of CH341A usb programmer is small and extremely simple, and the simplicity could be a key to success Best regards, Ivan 2018-03-17 14:31 GMT+03:00 <aadu(a)airmail.cc>: > > I apologise if I should write to flashrom mailing list instead and not you > directly. > > It was night when I wrote that message and I was tired. Bit more of what I > was doing. > > I was trying to do external flashing following instructions from coreboot > wiki. > I used command "sudo flashrom -p buspirate_spi:dev=/dev/ttyUSB0 -r > filename", and I got: > Calibrating delay loop... OK. > Found Generic flash chip "unknown SPI chip (RDID)" (0 kB, SPI) on > buspirate_spi. > === > This flash part has status NOT WORKING for operations: PROBE READ ERASE > WRITE > The test status of this chip may have been updated in the latest development > version of flashrom. If you are running the latest development version, > please email a report to flashrom(a)flashrom.org if any of the above > operations > work correctly for you with this flash part. Please include the flashrom > output with the additional -V option for all operations you tested (-V, -Vr, > -VE, -Vw), and mention which mainboard or programmer you tested. > Please mention your board in the subject line. Thanks for your help! > Read is not working on this chip. Aborting. > > Was that because it had bad connection or am I doing something really > stupid? > Then I used "flashrom -L" and it showed that T420 support was marked as > "BAD". > I bought Bus Pirate v3b and Pomona 5250 SOIC test clip. Have updated the Bus > Pirate firmware. > > Aadu >

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Unsupported laptop - output
by Leya 21 Mar '18

21 Mar '18

Hello team Here's the output of flashrom on my machine, as well as my system information. I will of course not use it, I am sharing this based on your request in here https://www.flashrom.org/Board_Testing_HOWTO This is the manufacturer website https://www.acer.com/ac/en/US/content/support-product/5977?b=1 Let me know if you need further, Thank you, sudo flashrom -p internal flashrom p1.0-22-g0bfa819 on Linux 4.14.27-1-MANJARO (x86_64) flashrom is free software, get the source code at https://flashrom.org Using clock_gettime for delay loops (clk_id: 1, resolution: 1ns). ======================================================================== WARNING! You seem to be running flashrom on an unsupported laptop. Laptops, notebooks and netbooks are difficult to support and we recommend to use the vendor flashing utility. The embedded controller (EC) in these machines often interacts badly with flashing. See the manpage and https://flashrom.org/Laptops for details. If flash is shared with the EC, erase is guaranteed to brick your laptop and write may brick your laptop. Read and probe may irritate your EC and cause fan failure, backlight failure and sudden poweroff. You have been warned. ======================================================================== Aborting. Error: Programmer initialization failed. inxi -Fx System: Kernel: 4.14.27-1-MANJARO x86_64 bits: 64 gcc: 7.3.0 Desktop: Xfce 4.12.4 (Gtk 2.24.31) Distro: Manjaro Linux Machine: Device: laptop System: Acer product: Aspire E5-573G v: V3.72 serial: N/A Mobo: Acer model: ZORO_BH v: Type2 - A01 Board Version serial: N/A UEFI [Legacy]: Insyde v: V1.15 date: 05/27/2015 Battery BAT1: charge: 33.1 Wh 100.0% condition: 33.1/37.0 Wh (90%) model: SANYO AL15A32 status: Full CPU: Dual core Intel Core i7-5500U (-MT-MCP-) arch: Broadwell rev.4 cache: 4096 KB flags: (lm nx sse sse2 sse3 sse4_1 sse4_2 ssse3 vmx) bmips: 9580 clock speeds: max: 3000 MHz 1: 2794 MHz 2: 2718 MHz 3: 2738 MHz 4: 2940 MHz

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