flashrom

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9161 discussions

AT25SF041 chip support
by adam 04 Dec '18

04 Dec '18

Hello, I'm trying to manage AT25SF041 using FT4232 MiniModule programmer. I'm using flashrom v1.0 on Linux 4.15.0-42-generic (x86_64) compiled from sources. Trying to erase chip at first and get this output: ./flashrom -p ft2232_spi:type=4232H,port=A -Ef Using clock_gettime for delay loops (clk_id: 1, resolution: 1ns). Found Atmel flash chip "unknown Atmel SPI chip" (0 kB, SPI) on ft2232_spi. === This flash part has status NOT WORKING for operations: PROBE READ ERASE WRITE The test status of this chip may have been updated in the latest development version of flashrom. If you are running the latest development version, please email a report to flashrom(a)flashrom.org if any of the above operations work correctly for you with this flash chip. Please include the flashrom log file for all operations you tested (see the man page for details), and mention which mainboard or programmer you tested in the subject line. Thanks for your help! Read is not working on this chip. Continuing anyway. flashrom has no read function for this flash chip. Aborting. Your flash chip is in an unknown state. Please report this on IRC at chat.freenode.net (channel #flashrom) or mail flashrom(a)flashrom.org, thanks! According to https://www.flashrom.org/Supported_hardware page, this chip should be fully supported. Please advice. Thank you, Adam

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FOSDEM Hardware Enablement Devroom
by Paul Kocialkowski 04 Dec '18

04 Dec '18

A Hardware Enablement devroom will be taking place at FOSDEM this year, on Sunday 10 December 2017. This newly-created devroom is the result of 3 proposals that were merged together. It is co-organized by several individuals. The devroom covers all aspects related to hardware enablement and support with free software, including aspects related to boot software, firmwares, drivers and userspace tools and adaptation. Proposals for talks related to these topics are welcome and can be submitted until Sunday 26 November 2017 via the pentabarf interface. Short talks are encouraged over longer ones in order to cover a wide range of topics. The announcement for the devroom, that contains all the useful information, was published at: https://lists.fosdem.org/pipermail/fosdem/2017-October/002649.html Cheers and see you at FOSDEM! -- Paul Kocialkowski, developer of free digital technology and hardware support Website: https://www.paulk.fr/ Coding blog: https://code.paulk.fr/ Git repositories: https://git.paulk.fr/ https://git.code.paulk.fr/

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Question about SIL3114 board with a N28F010-120 flash chip on it
by Peter Cost 30 Nov '18

30 Nov '18

Dear Reader, I have a SIL3114 PCI board with an Intel N28F010-120 flash chip on it, and I can't reprogram it since it lacks the 12V Vpp. I checked that there is no +12V connection on the PCI edge connector of the board and the VPP pin seems to be unconnected. My question is this. When I apply 12V Vpp to the chip will I then be able to reprogram the board with the Lattice (Silicon Image) dos utility or the flashrom utility. I am an experienced engineer, but my eprom day's are from way back in the 80's and early 90's and I have never done anything with flash proms other than reprogramming boards with the supplied software. Thanks for any response. Kind regards, Peter Cost

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Support for On Semiconductor LE25U20AMB-AH 2Mbit Flash Memory, 10ms, 8 pin SOP-K
by Andrew Hancock 28 Nov '18

28 Nov '18

Trying to read a firmware BIOS HDD for an external USB 1TB Western Digital which uses a Support for On Semiconductor LE25U20AMB-AH 2Mbit Flash Memory,10ms, 8 pin SOP-K No support found on Website or versions 0.9.9 and version 1.0 running on Ubuntu Will there be any support for this chip ?

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Heads Up: Ongoing layout-support work
by Nico Huber 25 Nov '18

25 Nov '18

Dear fellow flashrom contributors, I'll likely work on flashrom's layout support in the next few weeks. Part of it will be to finalize the work on per-region file arguments. There were multiple proposals for the command-line syntax without a real consent so far, [1] sums it up. If you have any preferences, please comment soon before things are set in stone. Nico [1] https://www.flashrom.org/Per_region_file_arguments

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(no subject)
by Сергей Калиничев 25 Nov '18

25 Nov '18

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Researching Lenovo IdeaPad 300-15ISK for Possible Future Support with FlashROM, and Later, CoreBoot
by moriel5 25 Nov '18

25 Nov '18

The title pretty much sums it up, however here are the details. I have managed to get a hold of my laptop's schematics due to them being leaked.I am currently working with someone over at Bios-Mods to modify the firmware ("unlocking it").Interestingly, this laptop (which I had already updated it's firmware), has no WiFi whitelist, and I had bought brand-new, about a month after it came out. The EC controller, an ITE IT8586E-LQFP, is connected via the LCP bus, and the touchpad, internal keyboard, and the NCT7718W thermal sensor are all connected to it, according to the schematics.I forget whether I have the same exact chip (though I believe it to be so) on my laptop, as 99% of the details match my laptop. The schematics refer to 2 SPI chips, an 8MB W25Q64FVSSIQ_SO8 on UC3 as the main SPI chip, and an 4MB W25Q32FVSSIQ_SO8 on UC6 as backup.I have only one SPI chip, an 8MB W25Q64FVS1011532 on UC3, with the UC6 solder point existing, so I could theoretically solder a backup SPI chip.A TPM chip, the Z32H320TC, also sits on the LCP bus, with a direct connection to the chipset, unlike the touchpad, internal keyboard and the thermal sensor, according to the schematics.I forget whether I have this TPM chip, but once again, I believe that it is so. The IdeaPad 300-15's motherboard is codenamed "Paris". It also (optionally) comes with an AMD dGPU, without direct connection to any graphical output.My specific model only has no dGPU. Can anyone help me with my research? I'm still not very experienced with the actual work regarding electronics, most of my experience is with researching them.If there is any more information required from the schematics, I'll gladly share them, and if anyone wants the schematics, I can send them over.

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Output of motherboard Acer EM61SM/EM61PM
by Roberto Masutti 24 Nov '18

24 Nov '18

flashrom v0.9.5.2-r1546 on Linux 3.2.0-4-amd64 (x86_64) flashrom is free software, get the source code at http://www.flashrom.org flashrom was built with libpci 3.1.7, GCC 4.6.2, little endian Command line (1 args): flashrom -V Calibrating delay loop... OS timer resolution is 1 usecs, 870M loops per second, 10 myus = 11 us, 100 myus = 101 us, 1000 myus = 1000 us, 10000 myus = 10016 us, 4 myus = 5 us, OK. Initializing internal programmer No coreboot table found. DMI string system-manufacturer: "Acer" DMI string system-product-name: "Aspire T180" DMI string system-version: "R01-B4" DMI string baseboard-manufacturer: "Acer" DMI string baseboard-product-name: "EM61SM/EM61PM " DMI string baseboard-version: " " DMI string chassis-type: "Desktop" Found ITE Super I/O, ID 0x8726 on port 0x2e Found chipset "NVIDIA MCP61" with PCI ID 10de:03e0. Enabling flash write... This chipset is not really supported yet. Guesswork... ISA/LPC bridge reg 0x8a contents: 0x00, bit 6 is 0, bit 5 is 0 Flash bus type is LPC Found SMBus device 10de:03eb at 00:01:1 MCP SPI BAR is at 0x00000000 MCP SPI is not used. Please send the output of "flashrom -V" to flashrom(a)flashrom.org with your board name: flashrom -V as the subject to help us finish support for your chipset. Thanks. OK. Super I/O ID 0x8726 is not on the list of flash capable controllers. The following protocols are supported: LPC. Probing for AMIC A49LF040A, 512 kB: probe_jedec_common: id1 0xbf, id2 0x50 Probing for Atmel AT49LH002, 256 kB: probe_82802ab: id1 0x26, id2 0xff, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm49FL002, 256 kB: probe_jedec_common: id1 0xbf, id2 0x50 Probing for PMC Pm49FL004, 512 kB: probe_jedec_common: id1 0xbf, id2 0x50 Probing for SST SST49LF020, 256 kB: probe_jedec_common: id1 0xbf, id2 0x50 Probing for SST SST49LF020A, 256 kB: probe_jedec_common: id1 0xbf, id2 0x50 Probing for SST SST49LF040, 512 kB: probe_jedec_common: id1 0xbf, id2 0x50 Probing for SST SST49LF040B, 512 kB: probe_jedec_common: id1 0xbf, id2 0x50 Found SST flash chip "SST49LF040B" (512 kB, LPC) at physical address 0xfff80000. Probing for SST SST49LF080A, 1024 kB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF160C, 2048 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW040A, 512 kB: probe_82802ab: id1 0x49, id2 0x4d, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW040B, 512 kB: probe_82802ab: id1 0x49, id2 0x4d, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080A, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080B, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50LPW116, 2048 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040A, 512 kB: probe_jedec_common: id1 0xbf, id2 0x50 Probing for Winbond W39V040B, 512 kB: probe_jedec_common: id1 0xbf, id2 0x50 Probing for Winbond W39V040C, 512 kB: probe_jedec_common: id1 0xbf, id2 0x50 Probing for Winbond W39V080A, 1024 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W49V002A, 256 kB: probe_jedec_common: id1 0xbf, id2 0x50 Found SST flash chip "SST49LF040B" (512 kB, LPC). No operations were specified. Restoring PCI config space for 00:01:0 reg 0x6d Restoring PCI config space for 00:01:0 reg 0x90 Restoring PCI config space for 00:01:0 reg 0x8c Restoring PCI config space for 00:01:0 reg 0x88

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[PATCH] Do not abuse cs_bit
by Vicente Bergas 23 Nov '18

23 Nov '18

"cs_bit[s]" variable stores the bit location for Chip Select, as implied by the name. A new variable "cfg" is added for static configuration bits, like Output Enables. If outputs are disabled during operation, then the result will depend on the target having proper pull-up resistors, which is not always guaranteed. Signed-off-by: Vicente Bergas <vicencb(a)gmail.com> --- ft2232_spi.c | 33 +++++++++++++++------------------ 1 file changed, 15 insertions(+), 18 deletions(-) diff --git a/ft2232_spi.c b/ft2232_spi.c index 95584aa..fe7fcf8 100644 --- a/ft2232_spi.c +++ b/ft2232_spi.c @@ -84,18 +84,19 @@ const struct dev_entry devs_ft2232spi[] = { #define BITMODE_BITBANG_NORMAL 1 #define BITMODE_BITBANG_SPI 2 -/* The variables cs_bits and pindir store the values for the "set data bits low byte" MPSSE command that +/* The variables cs_bit, cfg and pindir store the values for the "set data bits low byte" MPSSE command that * sets the initial state and the direction of the I/O pins. The pin offsets are as follows: * SCK is bit 0. * DO is bit 1. * DI is bit 2. - * CS is bit 3. + * CS is at cs_bit. Default is bit 3. * * The default values (set below) are used for most devices: * value: 0x08 CS=high, DI=low, DO=low, SK=low * dir: 0x0b CS=output, DI=input, DO=output, SK=output */ -static uint8_t cs_bits = 0x08; +static uint8_t cs_bit = 0x08; +static uint8_t cfg = 0x00; static uint8_t pindir = 0x0b; static struct ftdi_context ftdic_context; @@ -209,10 +210,9 @@ int ft2232_spi_init(void) ft2232_type = AMONTEC_JTAGKEY_PID; channel_count = 2; /* JTAGkey(2) needs to enable its output via Bit4 / GPIOL0 - * value: 0x18 OE=high, CS=high, DI=low, DO=low, SK=low - * dir: 0x1b OE=output, CS=output, DI=input, DO=output, SK=output */ - cs_bits = 0x18; - pindir = 0x1b; + * value: 0x08 #OE=low, CS=high, DI=low, DO=low, SK=low + * dir: 0x1b #OE=output, CS=output, DI=input, DO=output, SK=output */ + pindir |= 0x10; } else if (!strcasecmp(arg, "picotap")) { ft2232_vid = GOEPEL_VID; ft2232_type = GOEPEL_PICOTAP_PID; @@ -229,8 +229,7 @@ int ft2232_spi_init(void) /* In its default configuration it is a jtagkey clone */ ft2232_type = FTDI_FT2232H_PID; channel_count = 2; - cs_bits = 0x18; - pindir = 0x1b; + pindir |= 0x10; } else if (!strcasecmp(arg, "openmoko")) { ft2232_vid = FIC_VID; ft2232_type = OPENMOKO_DBGBOARD_PID; @@ -242,8 +241,7 @@ int ft2232_spi_init(void) /* arm-usb-ocd(-h) has an output buffer that needs to be enabled by pulling ADBUS4 low. * value: 0x08 #OE=low, CS=high, DI=low, DO=low, SK=low * dir: 0x1b #OE=output, CS=output, DI=input, DO=output, SK=output */ - cs_bits = 0x08; - pindir = 0x1b; + pindir |= 0x10; } else if (!strcasecmp(arg, "arm-usb-tiny")) { ft2232_vid = OLIMEX_VID; ft2232_type = OLIMEX_ARM_TINY_PID; @@ -253,8 +251,7 @@ int ft2232_spi_init(void) ft2232_type = OLIMEX_ARM_OCD_H_PID; channel_count = 2; /* See arm-usb-ocd */ - cs_bits = 0x08; - pindir = 0x1b; + pindir |= 0x10; } else if (!strcasecmp(arg, "arm-usb-tiny-h")) { ft2232_vid = OLIMEX_VID; ft2232_type = OLIMEX_ARM_TINY_H_PID; @@ -338,8 +335,8 @@ int ft2232_spi_init(void) return -2; } else { unsigned int pin = temp + 4; - cs_bits |= 1 << pin; - pindir |= 1 << pin; + cs_bit = 1 << pin; + pindir = (pindir & ~0x08) | cs_bit; } } free(arg); @@ -425,7 +422,7 @@ int ft2232_spi_init(void) msg_pdbg("Set data bits\n"); buf[0] = SET_BITS_LOW; - buf[1] = cs_bits; + buf[1] = cfg | cs_bit; buf[2] = pindir; if (send_buf(ftdic, buf, 3)) { ret = -8; @@ -480,7 +477,7 @@ static int ft2232_spi_send_command(struct flashctx *flash, */ msg_pspew("Assert CS#\n"); buf[i++] = SET_BITS_LOW; - buf[i++] = 0 & ~cs_bits; /* assertive */ + buf[i++] = cfg & ~cs_bit; buf[i++] = pindir; if (writecnt) { @@ -521,7 +518,7 @@ static int ft2232_spi_send_command(struct flashctx *flash, msg_pspew("De-assert CS#\n"); buf[i++] = SET_BITS_LOW; - buf[i++] = cs_bits; + buf[i++] = cfg | cs_bit; buf[i++] = pindir; ret = send_buf(ftdic, buf, i); failed |= ret; -- 2.19.1

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Raspberry Pi spidev failure
by Sean Cross 22 Nov '18

22 Nov '18

Hi, I got this email from a mailing list somewhere. I'm experiencing an issue where I'm unable to flash using spidev on a Raspberry Pi. I'm running "4.14.79-1.rpi.fc27.armv7hl", which is based on Fedberry. I'm experiencing two issues: 1) I'm completely unable to access any SPI chips. This appears to be due to a bug in the kernel driver, which always yanks the CS line high despite the cs_change set to 0. A workaround I've come up with is to do everything as a single transaction, which seems to fix the problem on my device: diff --git a/linux_spi.c b/linux_spi.c index 3e60492..50f8220 100644 --- a/linux_spi.c +++ b/linux_spi.c @@ -183,14 +183,12 @@ static int linux_spi_send_command(struct flashctx *flash, unsigned int writecnt, unsigned char *rxbuf) { int iocontrol_code; + char tmp_buf[readcnt + writecnt]; struct spi_ioc_transfer msg[2] = { { .tx_buf = (uint64_t)(uintptr_t)txbuf, - .len = writecnt, - }, - { - .rx_buf = (uint64_t)(uintptr_t)rxbuf, - .len = readcnt, + .rx_buf = (uint64_t)(uintptr_t)tmp_buf, + .len = writecnt+readcnt, }, }; @@ -203,15 +201,14 @@ static int linux_spi_send_command(struct flashctx *flash, unsigned int writecnt, /* Just submit the first (write) request in case there is nothing to read. Otherwise submit both requests. */ - if (readcnt == 0) - iocontrol_code = SPI_IOC_MESSAGE(1); - else - iocontrol_code = SPI_IOC_MESSAGE(2); + iocontrol_code = SPI_IOC_MESSAGE(1); if (ioctl(fd, iocontrol_code, msg) == -1) { msg_cerr("%s: ioctl: %s\n", __func__, strerror(errno)); return -1; } + + memcpy(rxbuf, tmp_buf + writecnt, readcnt); return 0; } ------------------- 2) The other issue is that my device appears to want SPI_MODE_1. When I set SPI_MODE_1, it is able to detect and program the board, but fails to verify. The image that gets loaded still works, but I'm unsure of what's causing the issue. I can do some more debugging, but changing SPI_MODE_1 and applying the above-mentioned patch solves the issue for me. Sean

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