flashrom

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9161 discussions

Re: [flashrom] New chip erase function
by Nico Huber 28 Oct '18

28 Oct '18

Hello Max, On 10/28/18 6:59 PM, M.Altschaeffel(a)gmx.de wrote: > Hi, > i have a problem with flashing a new blank bios chip. It´s a MX25L3206E chip. the failed byte counts in the log look rather random, which usually means the hardware setup is failing. Did you try to read+verify with this setup? only if reading is 100% reliable, writing will work. Do you have the plain chip connected or is it already soldered to the board? If the former, make sure to connect all input pins, i.e. /HOLD and /WP too. If the latter, power supply can be a problem; using the regular laptop PSU works best (might have to get it into a wake-on-lan state). Also, the T530 lacks pull-ups on the /CS lines of both flash chips. If that is the case for the T430 too, idk, but if, you should make sure that the /CS of the chip you _don't_ want to access is pulled high. Hope that helps, Nico

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Re: [flashrom] Failed p4vxasd2+
by Nico Huber 28 Oct '18

28 Oct '18

Hello Ilya, On 10/28/18 5:47 PM, Илья Пинясов wrote: > Failed p4vxasd2 + > I'm using lubuntu 18.04 do you need any help or did you just want to report this? If you need help, please provide the command you used and the error message you got (a verbose log would be appreciated). Nico

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New chip erase function
by M.Altschaeffel＠gmx.de 28 Oct '18

28 Oct '18

Hi, i have a problem with flashing a new blank bios chip. It´s a MX25L3206E chip. Using clock_gettime for delay loops (clk_id: 1, resolution: 1ns). Found Macronix flash chip "MX25L3206E/MX25L3208E" (4096 kB, SPI) on linux_spi. Reading old flash chip contents... done. Erasing and writing flash chip... FAILED at 0x00000000! Expected=0xff, Found=0x00, failed byte count from 0x00000000-0x00000fff: 0xffb ERASE FAILED! Reading current flash chip contents... done. Looking for another erase function. FAILED at 0x00000000! Expected=0xff, Found=0x00, failed byte count from 0x00000000-0x0000ffff: 0xc2e5 ERASE FAILED! Reading current flash chip contents... done. Looking for another erase function. FAILED at 0x00000136! Expected=0xff, Found=0x00, failed byte count from 0x00000000-0x0000ffff: 0xb25d ERASE FAILED! Reading current flash chip contents... done. Looking for another erase function. FAILED at 0x00000157! Expected=0xff, Found=0xfe, failed byte count from 0x00000000-0x003fffff: 0x2ef018 ERASE FAILED! Reading current flash chip contents... done. Looking for another erase function. FAILED at 0x00000073! Expected=0xff, Found=0x00, failed byte count from 0x00000000-0x003fffff: 0x2ed6f7 ERASE FAILED! Reading current flash chip contents... done. Looking for another erase function. Looking for another erase function. Looking for another erase function. No usable erase functions left. FAILED! Uh oh. Erase/write failed. Checking if anything has changed. Reading current flash chip contents... done. Apparently at least some data has changed. Your flash chip is in an unknown state. Please report this on IRC at chat.freenode.net (channel #flashrom) or mail flashrom(a)flashrom.org, thanks! I started flashrom with : " sudo flashrom -n --programmer linux_spi:dev=/dev/spidev0.0,spispeed=512 --chip "MX25L3206E/MX25L3208E" -f --write /tmp/t430.rom " I can´t skip the erase function, my thought -n and -f would help but no difference. For any help i would be thankful. Regards, max

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Failed p4vxasd2+
by Илья Пинясов 28 Oct '18

28 Oct '18

Failed p4vxasd2 + I'm using lubuntu 18.04

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Fwd: Intel QS77 chipet on MBA 2012
by Nico Huber 26 Oct '18

26 Oct '18

Sorry, it seems this one got lost in moderation, forwarding... -------- Forwarded Message -------- Subject: Intel QS77 chipet on MBA 2012 Date: Wed, 24 Oct 2018 23:18:40 +0200 From: Laura Martín <hoshi.utsuku(a)gmail.com> To: flashrom(a)flashrom.org Hi all, I'm trying to fix a corrupted EFI on a Macbook Air 13'' of 2012. I messed up with efibootmgr and that's the result... It's not a locked EFI, in the laptop Gentoo is installed, so I can access to the OS, although I can't boot from USB. So, I modified an EFI-dump for my laptop (I checked out it's not locked as well), I made a dump of the current EFI and replaced the serial number and other parameters. The size is OK, I checked out with hexdump. The stanza to made the write is: *# flashrom -p internal:pci=8086:1e56.0 -c "MX25L6406E/MX25L6408E" -V -w /home/m00n/nueva.rom* The output: Using clock_gettime for delay loops (clk_id: 1, resolution: 1ns). Initializing internal programmer No coreboot table found. Using Internal DMI decoder. No DMI table found. *Found chipset "Intel QS77" with PCI ID 8086:1e56.* This chipset is marked as untested. If you are using an up-to-date version of flashrom *and* were (not) able to successfully update your firmware with it, then please email a report to flashrom(a)flashrom.org including a verbose (-V) log. Thank you! Enabling flash write... Root Complex Register Block address = 0xfed1c000 GCS = 0xc21: BIOS Interface Lock-Down: enabled, Boot BIOS Straps: 0x3 (SPI) ... BIOS_CNTL = 0x01: BIOS Lock Enable: disabled, BIOS Write Enable: enabled .... BMWAG 0x00, BMRAG 0x00, BRWA 0xff, BRRA 0xff 0x54: 0x00000000 FREG0: Flash Descriptor region (0x00000000-0x00000fff) is read-write. 0x58: 0x07ff0190 FREG1: BIOS region (0x00190000-0x007fffff) is read-write. 0x5C: 0x018f0001 FREG2: Management Engine region (0x00001000-0x0018ffff) is read-write. 0x74: 0x866f0190 PR0: Warning: 0x00190000-0x0066ffff is read-only. 0x78: 0x9fff0692 PR1: Warning: 0x00692000-0x01ffffff is read-only. Writes have been disabled for safety reasons. You can enforce write support with the ich_spi_force programmer option, but you will most likely harm your hardware! If you force flashrom you will get no support if something breaks. On a few mainboards it is possible to enable write access by setting a jumper (see its documentation or the board itself). 0x90: 0xc4 (SSFS) SSFS: SCIP=0, FDONE=1, FCERR=0, AEL=0 0x91: 0xf94140 (SSFC) SSFC: SCGO=0, ACS=0, SPOP=0, COP=4, DBC=1, SME=0, SCF=1 0x94: 0x0606 (PREOP) 0x96: 0x3c6c (OPTYPE) 0x98: 0x0103029f (OPMENU) 0x9c: 0xffd82005 (OPMENU+4) 0xA0: 0x00000000 (BBAR) 0xC4: 0x00800000 (LVSCC) LVSCC: BES=0x0, WG=0, WSR=0, WEWS=0, EO=0x0, VCL=1 0xC8: 0x00002005 (UVSCC) UVSCC: BES=0x1, WG=1, WSR=0, WEWS=0, EO=0x20 0xD0: 0x00000000 (FPB) OK. Unhandled programmer parameters: pci=8086:1e56.0 Aborting. Error: Programmer initialization failed. Restoring MMIO space at 0x7f50ae5978a0 Restoring PCI config space for 00:1f:0 reg 0xdc So, what I'm doing wrong? It's an old laptop and with external devices I've read that it's possible to flash, From the same device it should be possible to do it .... I suppose that I'm missing some parameter.... But I can't find which. Any help would be appreciated... KR

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Intel QS77 chipet on MBA 2012
by Laura Martín 24 Oct '18

24 Oct '18

Hi all, I'm trying to fix a corrupted EFI on a Macbook Air 13'' of 2012. I messed up with efibootmgr and that's the result... It's not a locked EFI, in the laptop Gentoo is installed, so I can access to the OS, although I can't boot from USB. So, I modified an EFI-dump for my laptop (I checked out it's not locked as well), I made a dump of the current EFI and replaced the serial number and other parameters. The size is OK, I checked out with hexdump. The stanza to made the write is: *# flashrom -p internal:pci=8086:1e56.0 -c "MX25L6406E/MX25L6408E" -V -w /home/m00n/nueva.rom* The output: Using clock_gettime for delay loops (clk_id: 1, resolution: 1ns). Initializing internal programmer No coreboot table found. Using Internal DMI decoder. No DMI table found. *Found chipset "Intel QS77" with PCI ID 8086:1e56.* This chipset is marked as untested. If you are using an up-to-date version of flashrom *and* were (not) able to successfully update your firmware with it, then please email a report to flashrom(a)flashrom.org including a verbose (-V) log. Thank you! Enabling flash write... Root Complex Register Block address = 0xfed1c000 GCS = 0xc21: BIOS Interface Lock-Down: enabled, Boot BIOS Straps: 0x3 (SPI) ... BIOS_CNTL = 0x01: BIOS Lock Enable: disabled, BIOS Write Enable: enabled .... BMWAG 0x00, BMRAG 0x00, BRWA 0xff, BRRA 0xff 0x54: 0x00000000 FREG0: Flash Descriptor region (0x00000000-0x00000fff) is read-write. 0x58: 0x07ff0190 FREG1: BIOS region (0x00190000-0x007fffff) is read-write. 0x5C: 0x018f0001 FREG2: Management Engine region (0x00001000-0x0018ffff) is read-write. 0x74: 0x866f0190 PR0: Warning: 0x00190000-0x0066ffff is read-only. 0x78: 0x9fff0692 PR1: Warning: 0x00692000-0x01ffffff is read-only. Writes have been disabled for safety reasons. You can enforce write support with the ich_spi_force programmer option, but you will most likely harm your hardware! If you force flashrom you will get no support if something breaks. On a few mainboards it is possible to enable write access by setting a jumper (see its documentation or the board itself). 0x90: 0xc4 (SSFS) SSFS: SCIP=0, FDONE=1, FCERR=0, AEL=0 0x91: 0xf94140 (SSFC) SSFC: SCGO=0, ACS=0, SPOP=0, COP=4, DBC=1, SME=0, SCF=1 0x94: 0x0606 (PREOP) 0x96: 0x3c6c (OPTYPE) 0x98: 0x0103029f (OPMENU) 0x9c: 0xffd82005 (OPMENU+4) 0xA0: 0x00000000 (BBAR) 0xC4: 0x00800000 (LVSCC) LVSCC: BES=0x0, WG=0, WSR=0, WEWS=0, EO=0x0, VCL=1 0xC8: 0x00002005 (UVSCC) UVSCC: BES=0x1, WG=1, WSR=0, WEWS=0, EO=0x20 0xD0: 0x00000000 (FPB) OK. Unhandled programmer parameters: pci=8086:1e56.0 Aborting. Error: Programmer initialization failed. Restoring MMIO space at 0x7f50ae5978a0 Restoring PCI config space for 00:1f:0 reg 0xdc So, what I'm doing wrong? It's an old laptop and with external devices I've read that it's possible to flash, From the same device it should be possible to do it .... I suppose that I'm missing some parameter.... But I can't find which. Any help would be appreciated... KR

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Libflashrom development and integration with fwupd
by artur.raglis＠3mdeb.com 24 Oct '18

24 Oct '18

Hello, We would like to contribute to the flashrom project by adding missing libflashrom features like queries, proper flashrom_shutdown etc. Until now, I have implemented and tested missing libflashrom functions from query section [https://www.flashrom.org/Libflashrom] (based on patches from Łukasz Dmitrowski [https://patchwork.coreboot.org/patch/4316/]). There are 2 ways to get required information (e.g. supported programmers): const char **flashrom_supported_programmers(void); //#1 int flashrom_supported_programmers(const char **supported_programmers); //#2 I suppose that returning function status (#2) is not necessary with query functions, so I'll stick to the first approach. What we want to accomplish is remote firmware updates for brand new platforms straight from the factory. To do so, libflashrom will be integrated with fwupd which would control all required lib resources. I have read the conversation in the https://www.mail-archive.com/flashrom@flashrom.org/msg13518.html from which it appears that process callbacks for the progress bar is still high priority task. Are there any new ideas / hints that we need to know for further development? Best regards, Artur Raglis

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IS25LQ080 unlisted chip
by Olev 23 Oct '18

23 Oct '18

I include only important lines (no point pasting probes for everything). I could read the device no problems, did not try programming. Calibrating delay loop... OS timer resolution is 999 usecs, 1860M loops per second, 10 myus = 0 us, 100 myus = 0 us, 1000 myus = 999 us, 10000 myus = 9998 us, 3996 myus = 4000 us, OK. Initializing ch341a_spi programmer Device revision is 3.0.4 The following protocols are supported: SPI. Probing for Unknown SFDP-capable chip, 0 kB: SFDP revision = 1.5 SFDP number of parameter headers is 2 (NPH = 1). SFDP parameter table header 0/1: ID 0x00, version 1.5 Length 36 B, Parameter Table Pointer 0x000030 Parsing JEDEC flash parameter table... 3-Byte only addressing. Status register is non-volatile and the standard does not allow vendors to tell us whether EWSR/WREN is needed for status register writes - assuming EWSR. Write chunk size is at least 64 B. Flash chip size is 1024 kB. Block eraser 0: 256 x 4096 B with opcode 0x20 Tried to add a duplicate block eraser: 256 x 4096 B with opcode 0x20. Block eraser 1: 32 x 32768 B with opcode 0x52 Block eraser 2: 16 x 65536 B with opcode 0xd8 done. SFDP parameter table header 1/1: ID 0x9d, version 1.5 Length 12 B, Parameter Table Pointer 0x000080 === SFDP has autodetected a flash chip which is not natively supported by flashrom yet. All standard operations (read, verify, erase and write) should work, but to support all possible features we need to add them manually. You can help us by mailing us the output of the following command to flashrom(a)flashrom.org: 'flashrom -VV [plus the -p/--programmer parameter]' Thanks for your help! === Found Unknown flash chip "SFDP-capable chip" (1024 kB, SPI) on ch341a_spi.

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Re: [flashrom] Failing to WRITE an eeprom image to an "SST25VF512(A)" eeprom using a Bus Pirate (under Linux)
by awokd 20 Oct '18

20 Oct '18

Adam Ward: > (Flashrom Logfile attached) > > I'm having great difficulty performing a "-w" operation on an SST25VF512(A) > chip using my Bus Pirate under Linux. > > My hardware is as follows: > A brand new EEPROM (fresh from the tube) is *carefully* soldered onto a SMD > SOIC8 breakout board / programming harness I made, the ribbon going to the > bus pirate is less than 80mm long. There is a 0.1 uF decoupling ceramic > cap very close to the power pins on the IC. I have verified that the IC is > receiving 3.3 V from the Bus Pirate. There are no shorts or stray flying > wires anywhere. I have tried turning the speed all the way down to > "spispeed=30k" and the behaviour is the same. I believe the pinouts are > all correct as it looks like the flashrom program can read data from the > chips. > > I have tried 3 separate EEPROM chips (all the same type) just in cast I had > exceeded the write endurance of the silicon. They all fail in the same way > but one of them managed to get to the 5th block before it hanged. > > The log file I have attached just stops at the last line and never gets any > further. > > Can someone suggest a reason for this failure? I really need to get this > working. I can provide photos of the setup if that would help. You could try updating the BP firmware like http://dangerousprototypes.com/forum/viewtopic.php?f=28&t=8498&start=90#p67… . I've read the BP power output is relatively weak. Shouldn't matter if the only thing it's powering is that chip but maybe try an external power supply? Are your CS and WP pins tied appropriately?

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Failing to WRITE an eeprom image to an "SST25VF512(A)" eeprom using a Bus Pirate (under Linux)
by Adam Ward 19 Oct '18

19 Oct '18

(Flashrom Logfile attached) I'm having great difficulty performing a "-w" operation on an SST25VF512(A) chip using my Bus Pirate under Linux. My hardware is as follows: A brand new EEPROM (fresh from the tube) is *carefully* soldered onto a SMD SOIC8 breakout board / programming harness I made, the ribbon going to the bus pirate is less than 80mm long. There is a 0.1 uF decoupling ceramic cap very close to the power pins on the IC. I have verified that the IC is receiving 3.3 V from the Bus Pirate. There are no shorts or stray flying wires anywhere. I have tried turning the speed all the way down to "spispeed=30k" and the behaviour is the same. I believe the pinouts are all correct as it looks like the flashrom program can read data from the chips. I have tried 3 separate EEPROM chips (all the same type) just in cast I had exceeded the write endurance of the silicon. They all fail in the same way but one of them managed to get to the 5th block before it hanged. The log file I have attached just stops at the last line and never gets any further. Can someone suggest a reason for this failure? I really need to get this working. I can provide photos of the setup if that would help. Adam

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