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Re: [flashrom] [commit] r759 - trunk
by Luc Verhaegen 06 Dec '09

06 Dec '09

On Sun, Nov 15, 2009 at 06:13:29PM +0100, svn(a)flashrom.org wrote: > Author: hailfinger > Date: 2009-11-15 18:13:29 +0100 (Sun, 15 Nov 2009) > New Revision: 759 > static int enable_flash_sis630(struct pci_dev *dev, const char *name) > /* First probe for Super I/O on config port 0x2e. */ > - OUTB(0x87, 0x2e); > - OUTB(0x01, 0x2e); > - OUTB(0x55, 0x2e); > - OUTB(0x55, 0x2e); > + siobase = 0x2e; > + enter_conf_mode_ite(siobase); > > - if (INB(0x2f) != 0x87) { > + if (INB(siobase + 1) != 0x87) { > /* If that failed, try config port 0x4e. */ > - OUTB(0x87, 0x4e); > - OUTB(0x01, 0x4e); > - OUTB(0x55, 0x4e); > - OUTB(0xaa, 0x4e); > - if (INB(0x4f) != 0x87) { > - printf("Can not access SiS 950\n"); > + siobase = 0x4e; > + enter_conf_mode_ite(siobase); > + if (INB(siobase + 1) != 0x87) { > + printf("Can not find SuperI/O.\n"); > return -1; > } > - OUTB(0x24, 0x4e); > - b = INB(0x4f) | 0xfc; > - OUTB(0x24, 0x4e); > - OUTB(b, 0x4f); > - OUTB(0x02, 0x4e); > - OUTB(0x02, 0x4f); > } > > - OUTB(0x24, 0x2e); > - printf_debug("2f is %#x\n", INB(0x2f)); > - b = INB(0x2f) | 0xfc; > - OUTB(0x24, 0x2e); > - OUTB(b, 0x2f); > + /* Enable flash mapping. Works for most old ITE style SuperI/O. */ > + tmp = sio_read(siobase, 0x24); > + tmp |= 0xfc; > + sio_write(siobase, 0x24, tmp); > > - OUTB(0x02, 0x2e); > - OUTB(0x02, 0x2f); > + exit_conf_mode_ite(siobase); > > - return 0; > + return ret; > } Superio code in the chipset enable... Needs to be moved out, some VT823x based boards also require the same stuff. Maybe we need a superio_enable.c, which not only sets bits like that (some winbonds need the same) but which also contain the gpio specific routines. Luc Verhaegen.

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I have problem making latest flashrom
by guy lacroix 05 Dec '09

05 Dec '09

Dear Sirs, i learned how to install libpcidev,(zlib1g-dev), libftdi-dev. That is done. I did not install subversion. Source code folder flashrom-0.9.1 is in /home/guy and there I type make flashrom. Then I get output as in included error make flashrom. When I type sudo make flasrom I get guy@asus-p4b:~/flashrom-0.9.1$ sudo make flashrom [sudo] password for guy: Checking for a C compiler... found. Checking for FTDI support... found. cc -Os -Wall -Werror -D'SERPROG_SUPPORT=1' -D'FT2232_SPI_SUPPORT=1' -D'FLASHROM_VERSION="0.9.1-r710"' -o physmap.o -c physmap.c cc1: warnings being treated as errors physmap.c: In function ‘rdmsr’: physmap.c:146: error: dereferencing type-punned pointer will break strict-aliasing rules make: *** [physmap.o] Fout 1 guy@asus-p4b:~/flashrom-0.9.1$ Thanks for your help! I'm learing something this way.

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ERASE FAILURE! using flashrom-0.9.1-r792 as well on SST49LF002A in ASUS P4B rev 1.05
by guy lacroix 05 Dec '09

05 Dec '09

Dear Sirs, I realised that I have to type the full path to the flashrom located in /home/guy/flashrom-0.1.9-r792. Before I assumed that the flashrom in the current directory would be executed, This assumption is wrong. guy@asus-p4b:~/flashrom-0.9.1-r792$ sudo /home/guy/flashrom-0.9.1-r792/flashrom -r 1008.bin flashrom v0.9.1-r792 No coreboot table found. Found chipset "Intel ICH2", enabling flash write... OK. This chipset supports the following protocols: Non-SPI. Disabling flash write protection for board "ASUS P4B266"... Intel ICH LPC Bridge: Raising GPIO22. OK. Calibrating delay loop... OK. Found chip "SST SST49LF002A/B" (256 KB, FWH) at physical address 0xfffc0000. Reading flash... done. guy@asus-p4b:~/flashrom-0.9.1-r792$ sudo /home/guy/flashrom-0.9.1-r792/flashrom -w 1012.bin flashrom v0.9.1-r792 No coreboot table found. Found chipset "Intel ICH2", enabling flash write... OK. This chipset supports the following protocols: Non-SPI. Disabling flash write protection for board "ASUS P4B266"... Intel ICH LPC Bridge: Raising GPIO22. OK. Calibrating delay loop... OK. Found chip "SST SST49LF002A/B" (256 KB, FWH) at physical address 0xfffc0000. Flash image seems to be a legacy BIOS. Disabling checks. Writing flash chip... Programming page: 0000 at address: 0x00000000ERASE FAILED at 0x00000000! Expected=0xff, Read=0x25, failed byte count from 0x00000000-0x00003fff: 0x3fc0 ERASE FAILED! ERASE FAILED! FAILED! Your flash chip is in an unknown state. Get help on IRC at irc.freenode.net (channel #flashrom) or mail flashrom(a)flashrom.org! ------------------------------------------------------------------------------- DO NOT REBOOT OR POWEROFF! guy@asus-p4b:~/flashrom-0.9.1-r792$

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superiotool report for ASUS P4B ERASE FAILED on SST49LF002A
by guy lacroix 05 Dec '09

05 Dec '09

Dear Sirs, please find here the requested output With Kind Regards, Guy Lacroix

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requested info to troubleshoot an ERASE FAILED! on SST49LF002A in asus P4B
by guy lacroix 05 Dec '09

05 Dec '09

Dear Sirs, please find here some of the requested as for sudo superiotool -dev I get file not found (I did not dig this out) The board is ASUS P4B REV. 1.05 using latest released bios 1012 (I did not want to try beta bios) which can be found at http://support.asus.com/download/download.aspx?SLanguage=en-us javascript:global_click(this,'P4B','mb/sock478/p4b/1012.zip','1','15','1','1','1012.zip','0','1');show_bios_warnning('3'); Thank You for your promp assistance. You may want to know that the write operation failed on a spare flashrom. I can reinsert the original after power off.

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Asrock K7VT4A+
by Tor P 04 Dec '09

04 Dec '09

Hi I saw that someone was asking for support for the k7VT4A+ Since I desperately need support for this board to get my epia board working again here is the F segment from my board Tor

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Unable to flash bios on a Asus M2N68-VM
by Alessandro Polverini 04 Dec '09

04 Dec '09

Hello, this is the output of flashrom: flashrom v0.9.1-r706 No coreboot table found. Found chipset "NVIDIA MCP67", enabling flash write... OK. This chipset supports the following protocols: Non-SPI. Calibrating delay loop... OK. No EEPROM/flash device found. I attach the output of lspci -vvnnxxxx . If I can be of any help for providing more infos just ask. thanks, Alessandro 00:00.0 RAM memory [0500]: nVidia Corporation MCP67 Memory Controller [10de:0547] (rev a2) Subsystem: ASUSTeK Computer Inc. Device [1043:82b3] Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 Capabilities: [44] HyperTransport: Slave or Primary Interface Command: BaseUnitID=0 UnitCnt=15 MastHost- DefDir- DUL- Link Control 0: CFlE+ CST- CFE- <LkFail- Init+ EOC- TXO- <CRCErr=0 IsocEn- LSEn+ ExtCTL- 64b- Link Config 0: MLWI=16bit DwFcIn- MLWO=16bit DwFcOut- LWI=16bit DwFcInEn- LWO=16bit DwFcOutEn- Link Control 1: CFlE- CST- CFE- <LkFail+ Init- EOC+ TXO+ <CRCErr=0 IsocEn- LSEn- ExtCTL- 64b- Link Config 1: MLWI=8bit DwFcIn- MLWO=8bit DwFcOut- LWI=8bit DwFcInEn- LWO=8bit DwFcOutEn- Revision ID: 1.03 Link Frequency 0: 1.0GHz Link Error 0: <Prot- <Ovfl- <EOC- CTLTm- Link Frequency Capability 0: 200MHz+ 300MHz+ 400MHz+ 500MHz+ 600MHz+ 800MHz+ 1.0GHz+ 1.2GHz- 1.4GHz- 1.6GHz- Vend- Feature Capability: IsocFC+ LDTSTOP+ CRCTM- ECTLT- 64bA- UIDRD- Link Frequency 1: 200MHz Link Error 1: <Prot- <Ovfl- <EOC- CTLTm- Link Frequency Capability 1: 200MHz- 300MHz- 400MHz- 500MHz- 600MHz- 800MHz- 1.0GHz- 1.2GHz- 1.4GHz- 1.6GHz- Vend- Error Handling: PFlE+ OFlE+ PFE- OFE- EOCFE- RFE- CRCFE- SERRFE- CF- RE- PNFE- ONFE- EOCNFE- RNFE- CRCNFE- SERRNFE- Prefetchable memory behind bridge Upper: 00-00 Bus Number: 00 Capabilities: [dc] HyperTransport: MSI Mapping Enable+ Fixed- Mapping Address Base: 00000000fee00000 00: de 10 47 05 06 00 b0 00 a2 00 00 05 00 00 00 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 43 10 b3 82 30: 00 00 00 00 44 00 00 00 00 00 00 00 00 00 00 00 40: 43 10 b3 82 08 dc e0 01 22 20 11 11 d0 00 00 00 50: 23 06 7f 00 03 00 00 00 00 00 03 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 06 15 10 f1 70: 44 44 44 00 d0 09 00 00 11 00 00 00 11 11 88 00 80: 23 99 88 00 fa 00 64 0d 03 00 00 00 7f 00 00 00 90: 70 00 00 80 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 01 01 01 01 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 80 00 0f 0f 06 00 00 00 d0: 20 10 00 00 f0 ff ff ff 00 00 00 00 08 00 01 a8 e0: 00 00 e0 fe 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:01.0 ISA bridge [0601]: nVidia Corporation MCP67 ISA Bridge [10de:0548] (rev a2) Subsystem: ASUSTeK Computer Inc. Device [1043:82b3] Control: I/O+ Mem+ BusMaster+ SpecCycle+ MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap- 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort+ >SERR- <PERR- INTx- Latency: 0 Region 0: I/O ports at 0900 [size=256] 00: de 10 48 05 0f 00 a0 20 a2 00 01 06 00 00 80 00 10: 01 09 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 43 10 b3 82 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40: 43 10 b3 82 00 00 d0 fe fa 3e ff 00 fa 3e ff 00 50: fa 3e ff 00 00 5a 62 02 00 00 00 05 2b 00 4c 02 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 01 00 00 70: 10 00 ff ff c5 80 00 00 00 00 04 19 c6 00 40 00 80: 09 20 00 10 08 d2 0d 10 ff 00 40 01 ff 00 00 00 90: ff 7f 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 01 00 10 80 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 30 02 af 02 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 02 00 00 e0: 41 20 e6 24 8b 35 ee 41 0a 44 91 48 00 00 00 00 f0: 00 00 00 00 00 00 00 00 10 00 00 00 00 00 00 00 00:01.1 SMBus [0c05]: nVidia Corporation MCP67 SMBus [10de:0542] (rev a2) Subsystem: ASUSTeK Computer Inc. Device [1043:82b3] Control: I/O+ Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Interrupt: pin A routed to IRQ 10 Region 0: I/O ports at cc00 [size=64] Region 4: I/O ports at 0600 [size=64] Region 5: I/O ports at 0700 [size=64] Capabilities: [44] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot+,D3cold+) Status: D0 PME-Enable- DSel=0 DScale=0 PME- 00: de 10 42 05 01 00 b0 00 a2 00 05 0c 00 00 80 00 10: 01 cc 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 01 06 00 00 01 07 00 00 00 00 00 00 43 10 b3 82 30: 00 00 00 00 44 00 00 00 00 00 00 00 0a 01 00 00 40: 43 10 b3 82 01 00 02 c0 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 01 05 00 00 01 08 00 00 01 0d 00 00 00 00 00 00 70: 00 00 00 00 00 00 c8 fe 00 00 fe fe 01 00 00 00 80: 00 10 fe fe 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: d4 30 80 01 01 00 00 00 21 82 02 02 0d 0d 19 19 d0: 40 00 40 01 13 10 14 0a 05 00 00 00 00 00 00 00 e0: 88 10 04 13 05 40 00 01 80 22 00 00 62 44 44 00 f0: 02 ff 1e bf 01 00 40 80 10 00 00 00 00 00 00 00 00:02.0 USB Controller [0c03]: nVidia Corporation MCP67 OHCI USB 1.1 Controller [10de:055e] (rev a2) (prog-if 10) Subsystem: ASUSTeK Computer Inc. Device [1043:82b3] Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 (750ns min, 250ns max) Interrupt: pin A routed to IRQ 20 Region 0: Memory at dbeff000 (32-bit, non-prefetchable) [size=4K] Capabilities: [44] Power Management version 2 Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot+,D3cold+) Status: D0 PME-Enable- DSel=0 DScale=0 PME- Kernel driver in use: ohci_hcd 00: de 10 5e 05 07 00 b0 00 a2 10 03 0c 00 00 80 00 10: 00 f0 ef db 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 43 10 b3 82 30: 00 00 00 00 44 00 00 00 00 00 00 00 07 01 03 01 40: 43 10 b3 82 01 00 02 fe 00 00 00 00 00 00 00 00 50: 04 00 00 00 1d 47 40 00 10 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 02 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:02.1 USB Controller [0c03]: nVidia Corporation MCP67 EHCI USB 2.0 Controller [10de:055f] (rev a2) (prog-if 20) Subsystem: ASUSTeK Computer Inc. Device [1043:82b3] Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 (750ns min, 250ns max) Interrupt: pin B routed to IRQ 22 Region 0: Memory at dbefec00 (32-bit, non-prefetchable) [size=256] Capabilities: [44] Debug port: BAR=1 offset=0098 Capabilities: [80] Power Management version 2 Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot+,D3cold+) Status: D0 PME-Enable- DSel=0 DScale=0 PME+ Kernel driver in use: ehci_hcd 00: de 10 5f 05 06 00 b0 00 a2 20 03 0c 00 00 80 00 10: 00 ec ef db 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 43 10 b3 82 30: 00 00 00 00 44 00 00 00 00 00 00 00 0b 02 03 01 40: 43 10 b3 82 0a 80 98 20 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 20 20 01 00 00 60 18 85 03 3c 0a 01 00 00 00 00 70: 00 00 08 05 00 10 20 80 89 3d b6 22 77 25 04 00 80: 01 00 02 fe 00 80 00 00 00 00 00 00 15 16 00 00 90: 00 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 01 00 00 00 00 00 08 00 00 00 00 00 00 00 00 00 b0: 00 11 22 33 44 44 00 00 55 05 00 00 00 00 00 00 c0: 10 10 2d 0d 00 00 00 00 00 00 00 00 00 00 00 00 d0: 02 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 10 00 00 00 00 00 00 00 00:04.0 USB Controller [0c03]: nVidia Corporation MCP67 OHCI USB 1.1 Controller [10de:055e] (rev a2) (prog-if 10) Subsystem: ASUSTeK Computer Inc. Device [1043:82b3] Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 (750ns min, 250ns max) Interrupt: pin A routed to IRQ 23 Region 0: Memory at dbefd000 (32-bit, non-prefetchable) [size=4K] Capabilities: [44] Power Management version 2 Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot+,D3cold+) Status: D0 PME-Enable- DSel=0 DScale=0 PME- Kernel driver in use: ohci_hcd 00: de 10 5e 05 07 00 b0 00 a2 10 03 0c 00 00 80 00 10: 00 d0 ef db 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 43 10 b3 82 30: 00 00 00 00 44 00 00 00 00 00 00 00 0a 01 03 01 40: 43 10 b3 82 01 00 02 fe 00 00 00 00 00 00 00 00 50: 0a 00 00 00 1d 47 40 00 10 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 02 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:04.1 USB Controller [0c03]: nVidia Corporation MCP67 EHCI USB 2.0 Controller [10de:055f] (rev a2) (prog-if 20) Subsystem: ASUSTeK Computer Inc. Device [1043:82b3] Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 (750ns min, 250ns max) Interrupt: pin B routed to IRQ 21 Region 0: Memory at dbefe800 (32-bit, non-prefetchable) [size=256] Capabilities: [44] Debug port: BAR=1 offset=0098 Capabilities: [80] Power Management version 2 Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot+,D3cold+) Status: D0 PME-Enable- DSel=0 DScale=0 PME+ Kernel driver in use: ehci_hcd 00: de 10 5f 05 06 00 b0 00 a2 20 03 0c 00 00 80 00 10: 00 e8 ef db 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 43 10 b3 82 30: 00 00 00 00 44 00 00 00 00 00 00 00 07 02 03 01 40: 43 10 b3 82 0a 80 98 20 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 20 20 01 00 00 60 18 85 03 3c 0a 01 00 00 00 00 70: 00 00 08 05 00 10 20 80 89 3d b6 22 77 25 04 00 80: 01 00 02 fe 00 80 00 00 00 00 00 00 15 16 00 00 90: 00 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 01 00 00 00 00 00 08 00 00 00 00 00 00 00 00 00 b0: 00 11 22 33 44 44 00 00 aa 0a 00 00 00 00 00 00 c0: 10 10 2d 0d 00 00 00 00 00 00 00 00 00 00 00 00 d0: 02 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 10 00 00 00 00 00 00 00 00:06.0 IDE interface [0101]: nVidia Corporation MCP67 IDE Controller [10de:0560] (rev a1) (prog-if 8a [Master SecP PriP]) Subsystem: ASUSTeK Computer Inc. (Wrong ID) Device [f043:82b3] Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 (750ns min, 250ns max) Region 0: [virtual] Memory at 000001f0 (32-bit, non-prefetchable) [disabled] [size=8] Region 1: [virtual] Memory at 000003f0 (type 3, non-prefetchable) [disabled] [size=1] Region 2: [virtual] Memory at 00000170 (32-bit, non-prefetchable) [disabled] [size=8] Region 3: [virtual] Memory at 00000370 (type 3, non-prefetchable) [disabled] [size=1] Region 4: I/O ports at ffa0 [size=16] Capabilities: [44] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 PME-Enable- DSel=0 DScale=0 PME- Kernel driver in use: pata_amd 00: de 10 60 05 05 00 b0 00 a1 8a 01 01 00 00 00 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: a1 ff 00 00 00 00 00 00 00 00 00 00 43 f0 b3 82 30: 00 00 00 00 44 00 00 00 00 00 00 00 00 00 03 01 40: 43 f0 b3 82 01 00 02 00 00 00 00 00 00 00 00 00 50: 02 f0 00 00 00 00 00 00 99 99 99 99 aa 00 a8 a8 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 01 01 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 10 00 00 00 00 00 00 00 00:07.0 Audio device [0403]: nVidia Corporation MCP67 High Definition Audio [10de:055c] (rev a1) Subsystem: ASUSTeK Computer Inc. Device [1043:8345] Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 (500ns min, 1250ns max) Interrupt: pin A routed to IRQ 21 Region 0: Memory at dbef8000 (32-bit, non-prefetchable) [size=16K] Capabilities: [44] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot+,D3cold+) Status: D0 PME-Enable- DSel=0 DScale=0 PME- Capabilities: [50] Message Signalled Interrupts: Mask+ 64bit+ Queue=0/0 Enable- Address: 0000000000000000 Data: 0000 Masking: 00000000 Pending: 00000000 Capabilities: [6c] HyperTransport: MSI Mapping Enable+ Fixed+ Kernel driver in use: HDA Intel Kernel modules: snd-hda-intel 00: de 10 5c 05 06 00 b0 00 a1 00 03 04 00 00 80 00 10: 00 80 ef db 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 43 10 45 83 30: 00 00 00 00 44 00 00 00 00 00 00 00 0b 01 02 05 40: 43 10 45 83 01 50 02 c0 00 00 00 00 01 01 0f 00 50: 05 6c 80 01 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 0f 00 00 00 08 00 03 a8 70: 03 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 0f 40 00 22 00 00 67 00 01 00 00 20 00 00 00 00 f0: 00 00 00 00 00 00 00 47 00 29 00 00 00 00 00 00 00:08.0 PCI bridge [0604]: nVidia Corporation MCP67 PCI Bridge [10de:0561] (rev a2) (prog-if 01) Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 Bus: primary=00, secondary=01, subordinate=01, sec-latency=64 I/O behind bridge: 0000d000-0000dfff Memory behind bridge: dbf00000-dbffffff Prefetchable memory behind bridge: bf800000-bfffffff Secondary status: 66MHz- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort+ <SERR- <PERR- BridgeCtl: Parity- SERR+ NoISA- VGA- MAbort- >Reset- FastB2B- PriDiscTmr- SecDiscTmr+ DiscTmrStat+ DiscTmrSERREn- Capabilities: [b8] Subsystem: ASUSTeK Computer Inc. Device [1043:82b3] Capabilities: [8c] HyperTransport: MSI Mapping Enable+ Fixed- Mapping Address Base: 00000000fee00000 00: de 10 61 05 07 00 b0 00 a2 01 04 06 00 00 01 00 10: 00 00 00 00 00 00 00 00 00 01 01 40 d0 d0 80 22 20: f0 db f0 db 80 bf f0 bf 00 00 00 00 00 00 00 00 30: 00 00 00 00 b8 00 00 00 00 00 00 00 00 00 02 06 40: 00 00 73 07 01 00 02 00 0f 00 00 00 00 00 40 00 50: 00 00 00 00 00 00 00 00 ff 1f ff 1f 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 06 00 00 04 f8 ff db 00 00 00 00 08 00 01 a8 90: 00 00 e0 fe 00 00 00 00 00 00 00 00 00 00 00 00 a0: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 ff ff 00 00 0d 8c 00 00 43 10 b3 82 c0: 43 10 b3 82 03 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:09.0 IDE interface [0101]: nVidia Corporation MCP67 AHCI Controller [10de:0550] (rev a2) (prog-if 85 [Master SecO PriO]) Subsystem: ASUSTeK Computer Inc. Device [1043:82b3] Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- DisINTx- Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 (750ns min, 250ns max) Interrupt: pin A routed to IRQ 23 Region 0: I/O ports at c480 [size=8] Region 1: I/O ports at c400 [size=4] Region 2: I/O ports at c080 [size=8] Region 3: I/O ports at c000 [size=4] Region 4: I/O ports at bc00 [size=16] Region 5: Memory at dbef6000 (32-bit, non-prefetchable) [size=8K] Capabilities: [44] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 PME-Enable- DSel=0 DScale=0 PME- Capabilities: [8c] SATA HBA <?> Kernel driver in use: ahci 00: de 10 50 05 07 01 b0 00 a2 85 01 01 00 00 80 00 10: 81 c4 00 00 01 c4 00 00 81 c0 00 00 01 c0 00 00 20: 01 bc 00 00 00 60 ef db 00 00 00 00 43 10 b3 82 30: 00 00 00 00 44 00 00 00 00 00 00 00 0f 01 03 01 40: 43 10 b3 82 01 8c 02 00 00 00 00 00 00 00 00 00 50: 1f 68 38 60 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 01 0f 06 42 00 00 00 00 70: 2c 78 c4 40 00 00 00 00 02 00 00 08 20 00 20 78 80: 04 00 00 40 00 00 00 00 00 00 00 00 12 00 10 00 90: 5f 02 00 00 00 00 00 00 03 9f 22 e3 01 01 00 00 a0: 6e 5a 00 3f 80 00 00 00 00 00 00 00 23 34 00 02 b0: 05 cc 86 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 08 00 02 a8 d0: 00 00 00 00 00 00 00 00 00 00 40 00 00 00 00 00 e0: 00 00 00 00 00 00 3f 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 02 01 1e 00 00 00 00 00 00:0a.0 Ethernet controller [0200]: nVidia Corporation MCP67 Ethernet [10de:054c] (rev a2) Subsystem: ASUSTeK Computer Inc. Device [1043:82b3] Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+ Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 (250ns min, 5000ns max) Interrupt: pin A routed to IRQ 2296 Region 0: Memory at dbefc000 (32-bit, non-prefetchable) [size=4K] Region 1: I/O ports at b880 [size=8] Region 2: Memory at dbefe400 (32-bit, non-prefetchable) [size=256] Region 3: Memory at dbefe000 (32-bit, non-prefetchable) [size=16] Capabilities: [44] Power Management version 2 Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot+,D3cold+) Status: D0 PME-Enable+ DSel=0 DScale=0 PME- Capabilities: [50] Message Signalled Interrupts: Mask+ 64bit+ Queue=0/3 Enable+ Address: 00000000fee0f00c Data: 41b9 Masking: 000000fe Pending: 00000000 Capabilities: [6c] HyperTransport: MSI Mapping Enable+ Fixed+ Kernel driver in use: forcedeth Kernel modules: forcedeth 00: de 10 4c 05 07 04 b0 00 a2 00 00 02 00 00 00 00 10: 00 c0 ef db 81 b8 00 00 00 e4 ef db 00 e0 ef db 20: 00 00 00 00 00 00 00 00 00 00 00 00 43 10 b3 82 30: 00 00 00 00 44 00 00 00 00 00 00 00 0b 01 01 14 40: 43 10 b3 82 01 50 02 fe 00 01 00 00 08 00 00 00 50: 05 6c 87 01 0c f0 e0 fe 00 00 00 00 b9 41 00 00 60: fe 00 00 00 00 00 00 00 ff 00 00 00 08 00 03 a8 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 02 00 00 00 30 00 00 00 02 01 00 00 02 00 00 08 00:0b.0 PCI bridge [0604]: nVidia Corporation MCP67 PCI Express Bridge [10de:0562] (rev a2) Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+ Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0, Cache Line Size: 64 bytes Bus: primary=00, secondary=02, subordinate=02, sec-latency=0 I/O behind bridge: 0000e000-0000efff Memory behind bridge: dc000000-dfffffff Prefetchable memory behind bridge: 00000000c0000000-00000000cfffffff Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- <SERR- <PERR- BridgeCtl: Parity- SERR+ NoISA- VGA+ MAbort- >Reset- FastB2B- PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- Capabilities: [40] Subsystem: ASUSTeK Computer Inc. Device [1043:82b3] Capabilities: [48] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot+,D3cold+) Status: D0 PME-Enable- DSel=0 DScale=0 PME- Capabilities: [50] Message Signalled Interrupts: Mask- 64bit+ Queue=0/1 Enable+ Address: 00000000fee0f00c Data: 4149 Capabilities: [60] HyperTransport: MSI Mapping Enable+ Fixed- Mapping Address Base: 00000000fee00000 Capabilities: [80] Express (v1) Root Port (Slot+), MSI 00 DevCap: MaxPayload 256 bytes, PhantFunc 0, Latency L0s <64ns, L1 <1us ExtTag+ RBE+ FLReset- DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop+ MaxPayload 128 bytes, MaxReadReq 512 bytes DevSta: CorrErr+ UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend- LnkCap: Port #0, Speed 2.5GT/s, Width x16, ASPM L0s L1, Latency L0 <512ns, L1 <4us ClockPM- Suprise- LLActRep+ BwNot- LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- Retrain- CommClk- ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- LnkSta: Speed 2.5GT/s, Width x16, TrErr- Train- SlotClk+ DLActive+ BWMgmt- ABWMgmt- SltCap: AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug- Surpise- Slot # 1, PowerLimit 75.000000; Interlock- NoCompl- SltCtl: Enable: AttnBtn- PwrFlt- MRL- PresDet- CmdCplt- HPIrq- LinkChg- Control: AttnInd Off, PwrInd On, Power- Interlock- SltSta: Status: AttnBtn- PowerFlt- MRL- CmdCplt- PresDet+ Interlock- Changed: MRL- PresDet+ LinkState+ RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna- CRSVisible- RootCap: CRSVisible- RootSta: PME ReqID 0000, PMEStatus- PMEPending- Capabilities: [100] Virtual Channel <?> Kernel driver in use: pcieport-driver Kernel modules: shpchp 00: de 10 62 05 07 04 10 00 a2 00 04 06 10 00 01 00 10: 00 00 00 00 00 00 00 00 00 02 02 00 e1 e1 00 00 20: 00 dc f0 df 01 c0 f1 cf 00 00 00 00 00 00 00 00 30: 00 00 00 00 40 00 00 00 00 00 00 00 00 00 1a 00 40: 0d 48 00 00 43 10 b3 82 01 50 02 f8 00 00 00 00 50: 05 60 83 00 0c f0 e0 fe 00 00 00 00 49 41 00 00 60: 08 80 01 a8 00 00 e0 fe 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 10 00 41 01 21 80 00 00 10 28 01 00 01 3d 11 00 90: 00 00 01 31 80 25 08 00 c0 01 48 01 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 100: 02 00 01 00 00 00 00 00 00 00 00 00 02 00 00 00 110: 00 00 00 00 ff 00 00 80 00 00 00 00 00 00 00 00 120: 00 00 00 01 00 00 00 00 00 00 00 00 00 00 00 00 130: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 140: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 150: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 160: 01 00 01 00 00 00 00 00 00 00 00 00 11 20 06 00 170: 01 00 00 00 00 20 00 00 a0 00 00 00 00 00 00 00 180: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 190: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 1a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 1b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 1c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 1d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 1e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 1f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 200: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 210: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 220: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 230: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 240: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 250: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 260: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 270: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 280: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 290: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 2a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 2b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 2c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 2d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 2e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 2f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 300: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 310: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 320: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 330: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 340: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 350: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 360: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 370: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 380: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 390: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 3a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 3b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 3c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 3d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 3e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 3f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 400: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 410: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 420: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 430: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 440: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 450: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 460: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 470: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 480: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 490: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 4a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 4b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 4c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 4d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 4e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 4f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 500: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 510: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 520: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 530: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 540: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 550: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 560: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 570: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 580: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 590: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 5a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 5b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 5c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 5d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 5e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 5f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 600: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 610: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 620: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 630: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 640: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 650: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 660: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 670: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 680: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 690: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 6a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 6b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 6c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 6d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 6e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 6f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 700: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 710: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 720: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 730: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 740: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 750: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 760: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 770: 00 00 00 00 00 00 00 00 00 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00 00 00 00 fc0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 fd0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 fe0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ff0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:0c.0 PCI bridge [0604]: nVidia Corporation MCP67 PCI Express Bridge [10de:0563] (rev a2) Control: I/O- Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+ Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0, Cache Line Size: 64 bytes Bus: primary=00, secondary=03, subordinate=03, sec-latency=0 Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- <SERR- <PERR- BridgeCtl: Parity- SERR+ NoISA- VGA- MAbort- >Reset- FastB2B- PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- Capabilities: [40] Subsystem: ASUSTeK Computer Inc. Device [1043:82b3] Capabilities: [48] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot+,D3cold+) Status: D0 PME-Enable- DSel=0 DScale=0 PME- Capabilities: [50] Message Signalled Interrupts: Mask- 64bit+ Queue=0/1 Enable+ Address: 00000000fee0f00c Data: 4151 Capabilities: [60] HyperTransport: MSI Mapping Enable+ Fixed- Mapping Address Base: 00000000fee00000 Capabilities: [80] Express (v1) Root Port (Slot+), MSI 00 DevCap: MaxPayload 256 bytes, PhantFunc 0, Latency L0s <64ns, L1 <1us ExtTag+ RBE+ FLReset- DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop+ MaxPayload 128 bytes, MaxReadReq 512 bytes DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend- LnkCap: Port #1, Speed 2.5GT/s, Width x1, ASPM L0s L1, Latency L0 <512ns, L1 <4us ClockPM- Suprise- LLActRep+ BwNot- LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- Retrain- CommClk- ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- LnkSta: Speed 2.5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt- SltCap: AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug- Surpise- Slot # 2, PowerLimit 10.000000; Interlock- NoCompl- SltCtl: Enable: AttnBtn- PwrFlt- MRL- PresDet- CmdCplt- HPIrq- LinkChg- Control: AttnInd Off, PwrInd On, Power- Interlock- SltSta: Status: AttnBtn- PowerFlt- MRL- CmdCplt- PresDet- Interlock- Changed: MRL- PresDet+ LinkState- RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna- CRSVisible- RootCap: CRSVisible- RootSta: PME ReqID 0000, PMEStatus- PMEPending- Capabilities: [100] Virtual Channel <?> Kernel driver in use: pcieport-driver Kernel modules: shpchp 00: de 10 63 05 04 04 10 00 a2 00 04 06 10 00 01 00 10: 00 00 00 00 00 00 00 00 00 03 03 00 f1 01 00 00 20: f0 ff 00 00 f1 ff 01 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 40 00 00 00 00 00 00 00 00 00 02 00 40: 0d 48 00 00 43 10 b3 82 01 50 02 f8 00 00 00 00 50: 05 60 83 00 0c f0 e0 fe 00 00 00 00 51 41 00 00 60: 08 80 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00 00 00 fc0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 fd0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 fe0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ff0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:0d.0 PCI bridge [0604]: nVidia Corporation MCP67 PCI Express Bridge [10de:0563] (rev a2) Control: I/O- Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+ Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0, Cache Line Size: 64 bytes Bus: primary=00, secondary=04, subordinate=04, sec-latency=0 Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- <SERR- <PERR- BridgeCtl: Parity- SERR+ NoISA- VGA- MAbort- >Reset- FastB2B- PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- Capabilities: [40] Subsystem: ASUSTeK Computer Inc. Device [1043:82b3] Capabilities: [48] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot+,D3cold+) Status: D0 PME-Enable- DSel=0 DScale=0 PME- Capabilities: [50] Message Signalled Interrupts: Mask- 64bit+ Queue=0/1 Enable+ Address: 00000000fee0f00c Data: 4159 Capabilities: [60] HyperTransport: MSI Mapping Enable+ Fixed- Mapping Address Base: 00000000fee00000 Capabilities: [80] Express (v1) Root Port (Slot+), MSI 00 DevCap: MaxPayload 256 bytes, PhantFunc 0, Latency L0s <64ns, L1 <1us ExtTag+ RBE+ FLReset- DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop+ MaxPayload 128 bytes, MaxReadReq 512 bytes DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend- LnkCap: Port #2, Speed 2.5GT/s, Width x1, ASPM L0s L1, Latency L0 <512ns, L1 <4us ClockPM- Suprise- LLActRep+ BwNot- LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- Retrain- CommClk- ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- LnkSta: Speed 2.5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt- SltCap: AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug- Surpise- Slot # 3, PowerLimit 10.000000; Interlock- NoCompl- SltCtl: Enable: AttnBtn- PwrFlt- MRL- PresDet- CmdCplt- HPIrq- LinkChg- Control: AttnInd Off, PwrInd On, Power- Interlock- SltSta: Status: AttnBtn- PowerFlt- MRL- CmdCplt- PresDet- Interlock- Changed: MRL- PresDet+ LinkState- RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna- CRSVisible- RootCap: CRSVisible- RootSta: PME ReqID 0000, PMEStatus- PMEPending- Capabilities: [100] Virtual Channel <?> Kernel driver in use: pcieport-driver Kernel modules: shpchp 00: de 10 63 05 04 04 10 00 a2 00 04 06 10 00 01 00 10: 00 00 00 00 00 00 00 00 00 04 04 00 f1 01 00 00 20: f0 ff 00 00 f1 ff 01 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 40 00 00 00 00 00 00 00 00 00 02 00 40: 0d 48 00 00 43 10 b3 82 01 50 02 f8 00 00 00 00 50: 05 60 83 00 0c f0 e0 fe 00 00 00 00 59 41 00 00 60: 08 80 01 a8 00 00 e0 fe 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 10 00 41 01 21 80 00 00 10 28 00 00 11 3c 11 02 90: 00 00 11 10 00 05 18 00 c0 01 08 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 100: 02 00 01 00 00 00 00 00 00 00 00 00 02 00 00 00 110: 00 00 00 00 ff 00 00 80 00 00 00 00 00 00 00 00 120: 00 00 00 01 00 00 00 00 00 00 00 00 00 00 00 00 130: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 140: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 150: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 160: 01 00 01 00 00 00 00 00 00 00 00 00 11 20 06 00 170: 00 00 00 00 00 20 00 00 a0 00 00 00 00 00 00 00 180: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 190: 00 00 00 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00 00 00 00 00 00 00 00 00 00 00 00 00 00 c40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ca0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 cb0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 cc0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 cd0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ce0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 cf0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d00: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 da0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 db0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 dc0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 dd0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 de0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 df0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e00: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ea0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 eb0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ec0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ed0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ee0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ef0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f00: 00 00 00 38 00 00 38 04 00 ff 03 00 16 01 80 01 f10: ff ff ff ff 1b 00 00 00 00 00 00 00 00 00 00 00 f20: 00 05 18 00 00 00 00 00 00 00 00 00 00 00 00 00 f30: 00 00 00 00 00 00 00 00 00 00 00 00 40 40 60 10 f40: 80 c0 23 00 00 00 00 12 6f 00 16 05 00 00 00 00 f50: 1f 00 48 00 00 00 00 00 00 00 00 00 04 04 10 00 f60: 20 00 00 00 00 00 00 00 c4 09 40 06 20 11 60 30 f70: 00 00 00 00 00 00 00 00 00 00 2b 02 00 00 00 00 f80: 00 00 00 00 00 00 00 00 00 00 00 00 e4 d8 9f 00 f90: 2b 02 00 00 00 00 00 00 00 00 00 00 69 25 ad 00 fa0: 8f 00 f2 06 00 00 00 00 10 32 54 76 98 ba dc fe fb0: 43 10 b3 82 00 00 00 00 12 00 40 00 00 00 00 00 fc0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 fd0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 fe0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ff0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:0e.0 PCI bridge [0604]: nVidia Corporation MCP67 PCI Express Bridge [10de:0563] (rev a2) Control: I/O- Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+ Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0, Cache Line Size: 64 bytes Bus: primary=00, secondary=05, subordinate=05, sec-latency=0 Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- <SERR- <PERR- BridgeCtl: Parity- SERR+ NoISA- VGA- MAbort- >Reset- FastB2B- PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- Capabilities: [40] Subsystem: ASUSTeK Computer Inc. Device [1043:82b3] Capabilities: [48] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot+,D3cold+) Status: D0 PME-Enable- DSel=0 DScale=0 PME- Capabilities: [50] Message Signalled Interrupts: Mask- 64bit+ Queue=0/1 Enable+ Address: 00000000fee0f00c Data: 4161 Capabilities: [60] HyperTransport: MSI Mapping Enable+ Fixed- Mapping Address Base: 00000000fee00000 Capabilities: [80] Express (v1) Root Port (Slot+), MSI 00 DevCap: MaxPayload 256 bytes, PhantFunc 0, Latency L0s <64ns, L1 <1us ExtTag+ RBE+ FLReset- DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop+ MaxPayload 128 bytes, MaxReadReq 512 bytes DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend- LnkCap: Port #3, Speed 2.5GT/s, Width x1, ASPM L0s L1, Latency L0 <512ns, L1 <4us ClockPM- Suprise- LLActRep+ BwNot- LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- Retrain- CommClk- ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- LnkSta: Speed 2.5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt- SltCap: AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug- Surpise- Slot # 4, PowerLimit 10.000000; Interlock- NoCompl- SltCtl: Enable: AttnBtn- PwrFlt- MRL- PresDet- CmdCplt- HPIrq- LinkChg- Control: AttnInd Off, PwrInd On, Power- Interlock- SltSta: Status: AttnBtn- PowerFlt- MRL- CmdCplt- PresDet- Interlock- Changed: MRL- PresDet+ LinkState- RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna- CRSVisible- RootCap: CRSVisible- RootSta: PME ReqID 0000, PMEStatus- PMEPending- Capabilities: [100] Virtual Channel <?> Kernel driver in use: pcieport-driver Kernel modules: shpchp 00: de 10 63 05 04 04 10 00 a2 00 04 06 10 00 01 00 10: 00 00 00 00 00 00 00 00 00 05 05 00 f1 01 00 00 20: f0 ff 00 00 f1 ff 01 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 40 00 00 00 00 00 00 00 00 00 02 00 40: 0d 48 00 00 43 10 b3 82 01 50 02 f8 00 00 00 00 50: 05 60 83 00 0c f0 e0 fe 00 00 00 00 61 41 00 00 60: 08 80 01 a8 00 00 e0 fe 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 10 00 41 01 21 80 00 00 10 28 00 00 11 3c 11 03 90: 00 00 11 10 00 05 20 00 c0 01 08 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 100: 02 00 01 00 00 00 00 00 00 00 00 00 02 00 00 00 110: 00 00 00 00 ff 00 00 80 00 00 00 00 00 00 00 00 120: 00 00 00 01 00 00 00 00 00 00 00 00 00 00 00 00 130: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 140: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 150: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 160: 01 00 01 00 00 00 00 00 00 00 00 00 11 20 06 00 170: 00 00 00 00 00 20 00 00 a0 00 00 00 00 00 00 00 180: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 190: 00 00 00 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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 da0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 db0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 dc0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 dd0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 de0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 df0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e00: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ea0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 eb0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ec0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ed0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ee0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ef0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f00: 00 00 00 38 00 00 38 04 00 ff 03 00 16 01 80 01 f10: ff ff ff ff 1b 00 00 00 00 00 00 00 00 00 00 00 f20: 00 05 20 00 00 00 00 00 00 00 00 00 00 00 00 00 f30: 00 00 00 00 00 00 00 00 00 00 00 00 40 40 60 10 f40: 80 c0 23 00 00 00 00 12 6f 00 16 05 00 00 00 00 f50: 1f 00 48 00 00 00 00 00 00 00 00 00 04 04 10 00 f60: 20 00 00 00 00 00 00 00 c4 09 40 06 20 11 60 30 f70: 00 00 00 00 00 00 00 00 00 00 2b 02 00 00 00 00 f80: 00 00 00 00 00 00 00 00 00 00 00 00 e4 d8 9f 00 f90: 2b 02 00 00 00 00 00 00 00 00 00 00 69 25 ad 00 fa0: 8f 00 f2 06 00 00 00 00 10 32 54 76 98 ba dc fe fb0: 43 10 b3 82 00 00 00 00 13 00 40 00 00 00 00 00 fc0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 fd0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 fe0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ff0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:0f.0 PCI bridge [0604]: nVidia Corporation MCP67 PCI Express Bridge [10de:0563] (rev a2) Control: I/O- Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+ Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0, Cache Line Size: 64 bytes Bus: primary=00, secondary=06, subordinate=06, sec-latency=0 Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- <SERR- <PERR- BridgeCtl: Parity- SERR+ NoISA- VGA- MAbort- >Reset- FastB2B- PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- Capabilities: [40] Subsystem: ASUSTeK Computer Inc. Device [1043:82b3] Capabilities: [48] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot+,D3cold+) Status: D0 PME-Enable- DSel=0 DScale=0 PME- Capabilities: [50] Message Signalled Interrupts: Mask- 64bit+ Queue=0/1 Enable+ Address: 00000000fee0f00c Data: 4169 Capabilities: [60] HyperTransport: MSI Mapping Enable+ Fixed- Mapping Address Base: 00000000fee00000 Capabilities: [80] Express (v1) Root Port (Slot+), MSI 00 DevCap: MaxPayload 256 bytes, PhantFunc 0, Latency L0s <64ns, L1 <1us ExtTag+ RBE+ FLReset- DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop+ MaxPayload 128 bytes, MaxReadReq 512 bytes DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend- LnkCap: Port #4, Speed 2.5GT/s, Width x1, ASPM L0s L1, Latency L0 <512ns, L1 <4us ClockPM- Suprise- LLActRep+ BwNot- LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- Retrain- CommClk- ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- LnkSta: Speed 2.5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt- SltCap: AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug- Surpise- Slot # 5, PowerLimit 10.000000; Interlock- NoCompl- SltCtl: Enable: AttnBtn- PwrFlt- MRL- PresDet- CmdCplt- HPIrq- LinkChg- Control: AttnInd Off, PwrInd On, Power- Interlock- SltSta: Status: AttnBtn- PowerFlt- MRL- CmdCplt- PresDet- Interlock- Changed: MRL- PresDet+ LinkState- RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna- CRSVisible- RootCap: CRSVisible- RootSta: PME ReqID 0000, PMEStatus- PMEPending- Capabilities: [100] Virtual Channel <?> Kernel driver in use: pcieport-driver Kernel modules: shpchp 00: de 10 63 05 04 04 10 00 a2 00 04 06 10 00 01 00 10: 00 00 00 00 00 00 00 00 00 06 06 00 f1 01 00 00 20: f0 ff 00 00 f1 ff 01 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 40 00 00 00 00 00 00 00 00 00 02 00 40: 0d 48 00 00 43 10 b3 82 01 50 02 f8 00 00 00 00 50: 05 60 83 00 0c f0 e0 fe 00 00 00 00 69 41 00 00 60: 08 80 01 a8 00 00 e0 fe 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 10 00 41 01 21 80 00 00 10 28 00 00 11 3c 11 04 90: 00 00 11 10 00 05 28 00 c0 01 08 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 100: 02 00 01 00 00 00 00 00 00 00 00 00 02 00 00 00 110: 00 00 00 00 ff 00 00 80 00 00 00 00 00 00 00 00 120: 00 00 00 01 00 00 00 00 00 00 00 00 00 00 00 00 130: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 140: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 150: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 160: 01 00 01 00 00 00 00 00 00 00 00 00 11 20 06 00 170: 00 00 00 00 00 20 00 00 a0 00 00 00 00 00 00 00 180: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 190: 00 00 00 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00 00 00 fc0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 fd0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 fe0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ff0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:10.0 PCI bridge [0604]: nVidia Corporation MCP67 PCI Express Bridge [10de:0563] (rev a2) Control: I/O- Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+ Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0, Cache Line Size: 64 bytes Bus: primary=00, secondary=07, subordinate=07, sec-latency=0 Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- <SERR- <PERR- BridgeCtl: Parity- SERR+ NoISA- VGA- MAbort- >Reset- FastB2B- PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- Capabilities: [40] Subsystem: ASUSTeK Computer Inc. Device [1043:82b3] Capabilities: [48] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot+,D3cold+) Status: D0 PME-Enable- DSel=0 DScale=0 PME- Capabilities: [50] Message Signalled Interrupts: Mask- 64bit+ Queue=0/1 Enable+ Address: 00000000fee0f00c Data: 4171 Capabilities: [60] HyperTransport: MSI Mapping Enable+ Fixed- Mapping Address Base: 00000000fee00000 Capabilities: [80] Express (v1) Root Port (Slot+), MSI 00 DevCap: MaxPayload 256 bytes, PhantFunc 0, Latency L0s <64ns, L1 <1us ExtTag+ RBE+ FLReset- DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop+ MaxPayload 128 bytes, MaxReadReq 512 bytes DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend- LnkCap: Port #5, Speed 2.5GT/s, Width x1, ASPM L0s L1, Latency L0 <512ns, L1 <4us ClockPM- Suprise- LLActRep+ BwNot- LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- Retrain- CommClk- ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- LnkSta: Speed 2.5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt- SltCap: AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug- Surpise- Slot # 6, PowerLimit 10.000000; Interlock- NoCompl- SltCtl: Enable: AttnBtn- PwrFlt- MRL- PresDet- CmdCplt- HPIrq- LinkChg- Control: AttnInd Off, PwrInd On, Power- Interlock- SltSta: Status: AttnBtn- PowerFlt- MRL- CmdCplt- PresDet- Interlock- Changed: MRL- PresDet+ LinkState- RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna- CRSVisible- RootCap: CRSVisible- RootSta: PME ReqID 0000, PMEStatus- PMEPending- Capabilities: [100] Virtual Channel <?> Kernel driver in use: pcieport-driver Kernel modules: shpchp 00: de 10 63 05 04 04 10 00 a2 00 04 06 10 00 01 00 10: 00 00 00 00 00 00 00 00 00 07 07 00 f1 01 00 00 20: f0 ff 00 00 f1 ff 01 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 40 00 00 00 00 00 00 00 00 00 02 00 40: 0d 48 00 00 43 10 b3 82 01 50 02 f8 00 00 00 00 50: 05 60 83 00 0c f0 e0 fe 00 00 00 00 71 41 00 00 60: 08 80 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00 00 00 fc0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 fd0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 fe0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ff0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:11.0 PCI bridge [0604]: nVidia Corporation MCP67 PCI Express Bridge [10de:0563] (rev a2) Control: I/O- Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+ Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0, Cache Line Size: 64 bytes Bus: primary=00, secondary=08, subordinate=08, sec-latency=0 Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- <SERR- <PERR- BridgeCtl: Parity- SERR+ NoISA- VGA- MAbort- >Reset- FastB2B- PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- Capabilities: [40] Subsystem: ASUSTeK Computer Inc. Device [1043:82b3] Capabilities: [48] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot+,D3cold+) Status: D0 PME-Enable- DSel=0 DScale=0 PME- Capabilities: [50] Message Signalled Interrupts: Mask- 64bit+ Queue=0/1 Enable+ Address: 00000000fee0f00c Data: 4179 Capabilities: [60] HyperTransport: MSI Mapping Enable+ Fixed- Mapping Address Base: 00000000fee00000 Capabilities: [80] Express (v1) Root Port (Slot+), MSI 00 DevCap: MaxPayload 256 bytes, PhantFunc 0, Latency L0s <64ns, L1 <1us ExtTag+ RBE+ FLReset- DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop+ MaxPayload 128 bytes, MaxReadReq 512 bytes DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend- LnkCap: Port #6, Speed 2.5GT/s, Width x1, ASPM L0s L1, Latency L0 <512ns, L1 <4us ClockPM- Suprise- LLActRep+ BwNot- LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- Retrain- CommClk- ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- LnkSta: Speed 2.5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt- SltCap: AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug- Surpise- Slot # 7, PowerLimit 10.000000; Interlock- NoCompl- SltCtl: Enable: AttnBtn- PwrFlt- MRL- PresDet- CmdCplt- HPIrq- LinkChg- Control: AttnInd Off, PwrInd On, Power- Interlock- SltSta: Status: AttnBtn- PowerFlt- MRL- CmdCplt- PresDet- Interlock- Changed: MRL- PresDet+ LinkState- RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna- CRSVisible- RootCap: CRSVisible- RootSta: PME ReqID 0000, PMEStatus- PMEPending- Capabilities: [100] Virtual Channel <?> Kernel driver in use: pcieport-driver Kernel modules: shpchp 00: de 10 63 05 04 04 10 00 a2 00 04 06 10 00 01 00 10: 00 00 00 00 00 00 00 00 00 08 08 00 f1 01 00 00 20: f0 ff 00 00 f1 ff 01 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 40 00 00 00 00 00 00 00 00 00 02 00 40: 0d 48 00 00 43 10 b3 82 01 50 02 f8 00 00 00 00 50: 05 60 83 00 0c f0 e0 fe 00 00 00 00 79 41 00 00 60: 08 80 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00 00 00 fc0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 fd0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 fe0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ff0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:18.0 Host bridge [0600]: Advanced Micro Devices [AMD] Family 10h [Opteron, Athlon64, Sempron] HyperTransport Configuration [1022:1200] Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Capabilities: [80] HyperTransport: Host or Secondary Interface Command: WarmRst+ DblEnd- DevNum=0 ChainSide- HostHide+ Slave- <EOCErr- DUL- Link Control: CFlE- CST- CFE- <LkFail- Init+ EOC- TXO- <CRCErr=0 IsocEn- LSEn- ExtCTL- 64b- Link Config: MLWI=16bit DwFcIn- MLWO=16bit DwFcOut- LWI=16bit DwFcInEn- LWO=16bit DwFcOutEn- Revision ID: 3.00 Link Frequency: 1.0GHz Link Error: <Prot- <Ovfl- <EOC- CTLTm- Link Frequency Capability: 200MHz+ 300MHz- 400MHz+ 500MHz- 600MHz+ 800MHz+ 1.0GHz+ 1.2GHz+ 1.4GHz- 1.6GHz- Vend- Feature Capability: IsocFC+ LDTSTOP+ CRCTM- ECTLT- 64bA+ UIDRD- ExtRS- UCnfE- 00: 22 10 00 12 00 00 10 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 80 00 00 00 00 00 00 00 00 00 00 00 40: 01 02 04 00 01 02 04 00 01 02 04 00 01 02 04 00 50: 01 02 04 00 01 02 04 00 01 02 04 00 01 02 04 00 60: 00 00 03 00 e0 00 00 00 20 a8 4e 00 20 f8 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 08 00 01 21 20 00 11 11 60 06 f5 87 13 00 00 00 90: 92 02 85 04 00 00 00 00 07 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 100: 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00 00 00 00 00 00 f30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 fa0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 fb0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 fc0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 fd0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 fe0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ff0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:18.1 Host bridge [0600]: Advanced Micro Devices [AMD] Family 10h [Opteron, Athlon64, Sempron] Address Map [1022:1201] Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap- 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- 00: 22 10 01 12 00 00 00 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40: 03 00 00 00 00 00 4f 02 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 03 00 e0 00 80 ff ef 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 03 0a 00 00 00 0b 00 00 03 00 b0 00 00 0b fe 00 c0: 13 10 00 00 00 f0 ff 00 00 00 00 00 00 00 00 00 d0: 03 10 00 00 00 10 00 00 00 00 00 00 00 00 00 00 e0: 03 00 00 07 00 00 00 00 00 00 00 00 00 00 00 00 f0: 03 50 00 b0 00 00 00 00 00 00 00 00 00 00 00 00 100: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 110: 00 00 00 30 00 ff ff 1f 00 00 00 00 00 00 00 00 120: 00 00 00 00 49 00 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f50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 fa0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 fb0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 fc0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 fd0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 fe0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ff0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:18.2 Host bridge [0600]: Advanced Micro Devices [AMD] Family 10h [Opteron, Athlon64, Sempron] DRAM Controller [1022:1202] Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap- 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- 00: 22 10 02 12 00 00 00 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 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00 00 00 00 00 00 00 00 00 00 f80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 fa0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 fb0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 fc0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 fd0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 fe0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ff0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:18.3 Host bridge [0600]: Advanced Micro Devices [AMD] Family 10h [Opteron, Athlon64, Sempron] Miscellaneous Control [1022:1203] Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Capabilities: [f0] Secure device <?> 00: 22 10 03 12 00 00 10 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 f0 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00 00 00 00 00 00 00 00 00 00 00 00 00 00 e70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ea0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 eb0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ec0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ed0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ee0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ef0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f00: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 fa0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 fb0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 fc0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 fd0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 fe0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ff0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:18.4 Host bridge [0600]: Advanced Micro Devices [AMD] Family 10h [Opteron, Athlon64, Sempron] Link Control [1022:1204] Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap- 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- 00: 22 10 04 12 00 00 00 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 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00 00 00 00 00 00 00 fc0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 fd0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 fe0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ff0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 01:06.0 Ethernet controller [0200]: Realtek Semiconductor Co., Ltd. RTL-8169 Gigabit Ethernet [10ec:8169] (rev 10) Subsystem: Realtek Semiconductor Co., Ltd. RTL-8169 Gigabit Ethernet [10ec:8169] Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV+ VGASnoop- ParErr- Stepping- SERR+ FastB2B- DisINTx- Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR+ INTx- Latency: 64 (8000ns min, 16000ns max), Cache Line Size: 32 bytes Interrupt: pin A routed to IRQ 18 Region 0: I/O ports at d800 [size=256] Region 1: Memory at dbfffc00 (32-bit, non-prefetchable) [size=256] Expansion ROM at dbf00000 [disabled] [size=128K] Capabilities: [dc] Power Management version 2 Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0-,D1+,D2+,D3hot+,D3cold-) Status: D0 PME-Enable- DSel=0 DScale=0 PME- Kernel driver in use: r8169 Kernel modules: r8169 00: ec 10 69 81 17 01 b0 82 10 00 00 02 08 40 00 00 10: 01 d8 00 00 00 fc ff db 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 ec 10 69 81 30: 00 00 fc db dc 00 00 00 00 00 00 00 0a 01 20 40 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 01 00 02 76 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 01:07.0 RAID bus controller [0104]: 3ware Inc 9xxx-series SATA-RAID [13c1:1002] Subsystem: 3ware Inc 9xxx-series SATA-RAID [13c1:1002] Control: I/O+ Mem+ BusMaster+ SpecCycle+ MemWINV+ VGASnoop- ParErr- Stepping- SERR+ FastB2B- DisINTx- Status: Cap+ 66MHz+ UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 64 (2250ns min), Cache Line Size: 64 bytes Interrupt: pin A routed to IRQ 19 Region 0: I/O ports at d400 [size=256] Region 1: Memory at dbfff800 (64-bit, non-prefetchable) [size=256] Region 3: Memory at bf800000 (64-bit, prefetchable) [size=8M] Expansion ROM at dbf20000 [disabled] [size=64K] Capabilities: [48] Power Management version 2 Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot+,D3cold-) Status: D0 PME-Enable- DSel=0 DScale=0 PME- Kernel driver in use: 3w-9xxx Kernel modules: 3w-9xxx 00: c1 13 02 10 1f 01 30 02 00 00 04 01 10 40 00 00 10: 01 d4 00 00 04 f8 ff db 00 00 00 00 0c 00 80 bf 20: 00 00 00 00 00 00 00 00 00 00 00 00 c1 13 02 10 30: 00 00 fe db 48 00 00 00 00 00 00 00 07 01 09 00 40: 07 48 00 00 f8 ff 03 00 01 00 02 7e 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 02:00.0 VGA compatible controller [0300]: nVidia Corporation GeForce 8600 GT [10de:0402] (rev a1) Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 Interrupt: pin A routed to IRQ 17 Region 0: Memory at df000000 (32-bit, non-prefetchable) [size=16M] Region 1: Memory at c0000000 (64-bit, prefetchable) [size=256M] Region 3: Memory at dc000000 (64-bit, non-prefetchable) [size=32M] Region 5: I/O ports at ec00 [size=128] [virtual] Expansion ROM at defe0000 [disabled] [size=128K] Capabilities: [60] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 PME-Enable- DSel=0 DScale=0 PME- Capabilities: [68] Message Signalled Interrupts: Mask- 64bit+ Queue=0/0 Enable- Address: 0000000000000000 Data: 0000 Capabilities: [78] Express (v1) Endpoint, MSI 00 DevCap: MaxPayload 128 bytes, PhantFunc 0, Latency L0s <512ns, L1 <4us ExtTag+ AttnBtn- AttnInd- PwrInd- RBE+ FLReset- DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- RlxdOrd+ ExtTag+ PhantFunc- AuxPwr- NoSnoop+ MaxPayload 128 bytes, MaxReadReq 512 bytes DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend- LnkCap: Port #0, Speed 2.5GT/s, Width x16, ASPM L0s L1, Latency L0 <512ns, L1 <4us ClockPM- Suprise- LLActRep- BwNot- LnkCtl: ASPM Disabled; RCB 128 bytes Disabled- Retrain- CommClk- ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- LnkSta: Speed 2.5GT/s, Width x16, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt- Capabilities: [100] Virtual Channel <?> Capabilities: [128] Power Budgeting <?> Capabilities: [600] Vendor Specific Information <?> Kernel driver in use: nvidia Kernel modules: nvidia, nvidiafb 00: de 10 02 04 07 00 10 00 a1 00 00 03 00 00 00 00 10: 00 00 00 df 0c 00 00 c0 00 00 00 00 04 00 00 dc 20: 00 00 00 00 01 ec 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 60 00 00 00 00 00 00 00 0b 01 00 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 01 00 00 00 01 00 00 00 ce d6 23 00 00 00 00 00 60: 01 68 02 00 00 00 00 00 05 78 80 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 10 00 01 00 e0 84 00 00 80: 10 29 00 00 01 3d 01 00 08 00 01 11 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 100: 02 00 81 12 00 00 00 00 00 00 00 00 00 00 00 00 110: 00 00 00 00 01 00 00 80 00 00 00 00 00 00 00 00 120: 00 00 00 00 00 00 00 00 04 00 01 60 00 00 00 00 130: 21 81 07 00 00 00 00 00 00 00 00 10 00 00 ff 33 140: 00 00 01 00 10 00 00 00 ff ff ff ff 1b 00 00 83 150: 10 fe 00 60 00 00 00 00 02 01 00 00 21 81 07 00 160: 21 81 05 00 02 80 03 00 02 80 01 00 06 80 1f 00 170: 06 80 1d 00 00 00 00 00 00 00 00 00 00 00 00 00 180: 00 00 00 00 00 00 00 00 01 00 00 00 07 00 00 d0 190: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 1a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 1b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 1c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 1d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 1e0: 14 00 00 00 14 00 00 00 14 00 00 00 00 00 00 00 1f0: 14 00 00 01 00 00 00 00 00 00 00 00 00 00 00 00 200: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 210: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 220: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 230: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 240: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 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3 8

Re: [flashrom] [PATCH] MCP67 SPI detection/debugging
by Carl-Daniel Hailfinger 04 Dec '09

04 Dec '09

Hi Alex, On 04.12.2009 13:51, Alessandro Polverini wrote: > may I use a standard flashrom (0.9.1) to capture the output or you > need latest one with this patch applied? I think you need latest flashrom for this to work. If this is indeed a machine which you can't power off because it acts as a server, tests with this patch are still useful in theory, but the results might be garbage. Not sure yet. I can't make any guarantees, but the patch should be safe to test (unless the GPIO read has side effects, but that is unlikely). Regards, Carl-Daniel > Carl-Daniel Hailfinger wrote: >> First attempt at shedding some light on the MCP67 SPI situation. >> Huge thanks to Michael Karcher for reverse engineering the chipset and >> writing a spec. Due to this, we were able to use the chinese wall >> technique for 100% clean room reverse engineering. >> >> This patch doesn't touch any of the new registers, it only reads them. >> Assuming that read has no side effects, this patch is a no-op and safe. >> >> We need "flashrom -V" output from MCP67 boards with SPI flash and from >> boards with LPC flash. Note: That output is only helpful if it is >> created with patched flashrom and if is from the first run of flashrom >> after a cold boot (reset or Ctrl-Alt-Del is not sufficient). I hope to >> see a pattern based on which we can detect which flash type is present >> on the board. >> >> Alex, we need this output (as described above) from your Asus M2N68-VM >> board. >> >> I'd like to merge this ASAP and then ping everyone who had this chipset >> to get flashrom -V output. >> >> Signed-off-by: Carl-Daniel Hailfinger >> <c-d.hailfinger.devel.2006(a)gmx.net> -- Developer quote of the month: "We are juggling too many chainsaws and flaming arrows and tigers."

1 0

Re: [flashrom] Unable to flash bios on a Asus M2N68-VM
by Carl-Daniel Hailfinger 04 Dec '09

04 Dec '09

Hi Alex, I found a few high-resolution photos for the M2N68-VM. It is the 8-pin chip in a socket with a yellow dot in the middle of the lower edge of the board here: http://img24.imageshack.us/img24/7444/m2n68vmfull2.jpg It is the 8-pin chip in a socket with a blue dot in the lower left corner of the image here: http://img524.imageshack.us/img524/9926/img1447r.jpg Probably a MX 25L8005 chip if the photos are any indication. Regards, Carl-Daniel On 04.12.2009 09:05, Alessandro Polverini wrote: > powering off my server is not very practical at the moment, I've a lot > of tasks running on it. > I could try to see inside it without powering it off, but I need some > hint on where to look. > I found this picture of the mainboard: > http://www.asus.com/websites/Global/products/TtvnYkYtXtRgFXG3/TtjG7ja5aSlRe… > > maybe you are to understand which chip it may be? -- Developer quote of the month: "We are juggling too many chainsaws and flaming arrows and tigers."

1 0

acer extensa
by Charlie Watson 03 Dec '09

03 Dec '09

I was updating my Acer Extensa 5630z with the latest update vs 1.36 and webshots desktop interupted the update. Acer's winflash only works in Windows and restarted the computer automatically (wouldnt even let me cancel). I cannot boot to windows anymore. cant even boot to my miniPE rescue disk. luckily i can at least boot to ubuntu but im not that good with linux. Could someone make a zip file that i could extract to my usb memory and try to flash it back? http://gd.panam.acer.com/home/ i want to try and put 1.30 back on it. i tried using wine but that didnt work. _________________________________________________________________ Chat with Messenger straight from your Hotmail inbox. http://www.microsoft.com/windows/windowslive/hotmail_bl1/hotmail_bl1.aspx?o…

4 7

[Patch] Boards: Add general nVidia MCP gpio routine.
by Luc Verhaegen 03 Dec '09

03 Dec '09

2 2

[commit] r792 - trunk
by svn＠flashrom.org 03 Dec '09

03 Dec '09

Author: libv Date: 2009-12-03 13:25:34 +0100 (Thu, 03 Dec 2009) New Revision: 792 Modified: trunk/board_enable.c Log: Boards: Add general nVidia MCP gpio routine. Turns out that the AMD 8111 datasheet describes this bit of the MCP perfectly. Signed-off-by: Luc Verhaegen <libv(a)skynet.be> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: trunk/board_enable.c =================================================================== --- trunk/board_enable.c 2009-12-01 12:55:18 UTC (rev 791) +++ trunk/board_enable.c 2009-12-03 12:25:34 UTC (rev 792) @@ -415,76 +415,65 @@ } /** - * No docs, so we are just guessing that these might be individual gpio lines. + * Very similar to AMD 8111 IO Hub. */ -static void nvidia_mcp_gpio_raise(struct pci_dev *dev, uint8_t offset) +static int nvidia_mcp_gpio_set(int gpio, int raise) { + struct pci_dev *dev; uint16_t base; uint8_t tmp; - base = pci_read_long(dev, 0x64) & 0x0000FF00; /* System control area */ + if ((gpio < 0) || (gpio > 31)) { + fprintf(stderr, "\nERROR: unsupported GPIO: %d.\n", gpio); + return -1; + } - base += 0xC0; - - /* if anyone knows more about nvidia mcps, feel free to explain this */ - tmp = INB(base + offset); - tmp &= ~0x0F; - tmp |= 0x05; - OUTB(tmp, base + offset); -} - -/** - * Suited for the Gigabyte GA-K8N-SLI: CK804 southbridge. - */ -static int board_ga_k8n_sli(const char *name) -{ - struct pci_dev *dev; - - dev = pci_dev_find(0x10DE, 0x0050); /* NVIDIA CK804 LPC */ - if (!dev) { - fprintf(stderr, "\nERROR: NVIDIA LPC bridge not found.\n"); + dev = pci_dev_find_vendorclass(0x10DE, 0x0C05); + switch (dev->device_id) { + case 0x0030: /* CK804 */ + case 0x0050: /* MCP04 */ + case 0x0060: /* MCP2 */ + break; + default: + fprintf(stderr, "\nERROR: no nVidia SMBus controller found.\n"); return -1; } - nvidia_mcp_gpio_raise(dev, 0x21); + base = pci_read_long(dev, 0x64) & 0x0000FF00; /* System control area */ + base += 0xC0; + tmp = INB(base + gpio); + tmp &= ~0x0F; /* null lower nibble */ + tmp |= 0x04; /* gpio -> output. */ + if (raise) + tmp |= 0x01; + OUTB(tmp, base + gpio); + return 0; } /** * Suited for ASUS P5ND2-SLI Deluxe: LGA775 + nForce4 SLI + MCP04. */ -static int board_asus_p5nd2_sli(const char *name) +static int nvidia_mcp_gpio10_raise(const char *name) { - struct pci_dev *dev; + return nvidia_mcp_gpio_set(0x10, 1); +} - dev = pci_dev_find(0x10DE, 0x0030); /* NVIDIA nForce4 ISA Bridge */ - if (!dev) { - fprintf(stderr, "\nERROR: NVIDIA ISA bridge not found.\n"); - return -1; - } - - nvidia_mcp_gpio_raise(dev, 0x10); - - return 0; +/** + * Suited for the Gigabyte GA-K8N-SLI: CK804 southbridge. + */ +static int nvidia_mcp_gpio21_raise(const char *name) +{ + return nvidia_mcp_gpio_set(0x21, 0x01); } /** * Suited for EPoX EP-8RDA3+: Socket A + nForce2 Ultra 400 + MCP2. */ -static int board_epox_ep_8rda3plus(const char *name) +static int nvidia_mcp_gpio31_raise(const char *name) { - struct pci_dev *dev; - - dev = pci_dev_find(0x10DE, 0x0060); /* NVIDIA nForce2 ISA Bridge */ - if (!dev) { - fprintf(stderr, "\nERROR: NVIDIA ISA bridge not found.\n"); - return -1; - } - - nvidia_mcp_gpio_raise(dev, 0x31); - - return 0; + return nvidia_mcp_gpio_set(0x31, 0x01); } static int board_hp_dl145_g3_enable(const char *name) @@ -1152,16 +1141,16 @@ {0x8086, 0x1A30, 0x1043, 0x8025, 0x8086, 0x244B, 0x104D, 0x80F0, NULL, NULL, "ASUS", "P4B266-LM", intel_ich_gpio21_raise}, {0x8086, 0x2570, 0x1043, 0x80F2, 0x105A, 0x3373, 0x1043, 0x80F5, NULL, NULL, "ASUS", "P4P800-E Deluxe", intel_ich_gpio21_raise}, {0x10B9, 0x1541, 0, 0, 0x10B9, 0x1533, 0, 0, "asus", "p5a", "ASUS", "P5A", board_asus_p5a}, - {0x10DE, 0x0030, 0x1043, 0x818a, 0x8086, 0x100E, 0x1043, 0x80EE, NULL, NULL, "ASUS", "P5ND2-SLI Deluxe", board_asus_p5nd2_sli}, + {0x10DE, 0x0030, 0x1043, 0x818a, 0x8086, 0x100E, 0x1043, 0x80EE, NULL, NULL, "ASUS", "P5ND2-SLI Deluxe", nvidia_mcp_gpio10_raise}, {0x1106, 0x3149, 0x1565, 0x3206, 0x1106, 0x3344, 0x1565, 0x1202, NULL, NULL, "Biostar", "P4M80-M4", it8705_rom_write_enable}, {0x8086, 0x3590, 0x1028, 0x016c, 0x1000, 0x0030, 0x1028, 0x016c, NULL, NULL, "Dell", "PowerEdge 1850", intel_ich_gpio23_raise}, {0x1106, 0x3038, 0x1019, 0x0996, 0x1106, 0x3177, 0x1019, 0x0996, NULL, NULL, "Elitegroup", "K7VTA3", it8705f_write_enable_2e}, {0x1106, 0x3177, 0x1106, 0x3177, 0x1106, 0x3059, 0x1695, 0x3005, NULL, NULL, "EPoX", "EP-8K5A2", w836xx_memw_enable_2e}, - {0x10EC, 0x8139, 0x1695, 0x9001, 0x11C1, 0x5811, 0x1695, 0x9015, NULL, NULL, "EPoX", "EP-8RDA3+", board_epox_ep_8rda3plus}, + {0x10EC, 0x8139, 0x1695, 0x9001, 0x11C1, 0x5811, 0x1695, 0x9015, NULL, NULL, "EPoX", "EP-8RDA3+", nvidia_mcp_gpio31_raise}, {0x8086, 0x7110, 0, 0, 0x8086, 0x7190, 0, 0, "epox", "ep-bx3", "EPoX", "EP-BX3", board_epox_ep_bx3}, {0x1039, 0x0761, 0, 0, 0, 0, 0, 0, "gigabyte", "2761gxdk", "GIGABYTE", "GA-2761GXDK", it87xx_probe_spi_flash}, {0x1106, 0x3227, 0x1458, 0x5001, 0x10ec, 0x8139, 0x1458, 0xe000, NULL, NULL, "GIGABYTE", "GA-7VT600", it8705_rom_write_enable}, - {0x10DE, 0x0050, 0x1458, 0x0C11, 0x10DE, 0x005e, 0x1458, 0x5000, NULL, NULL, "GIGABYTE", "GA-K8N-SLI", board_ga_k8n_sli}, + {0x10DE, 0x0050, 0x1458, 0x0C11, 0x10DE, 0x005e, 0x1458, 0x5000, NULL, NULL, "GIGABYTE", "GA-K8N-SLI", nvidia_mcp_gpio21_raise}, {0x10de, 0x0360, 0, 0, 0, 0, 0, 0, "gigabyte", "m57sli", "GIGABYTE", "GA-M57SLI-S4", it87xx_probe_spi_flash}, {0x10de, 0x03e0, 0, 0, 0, 0, 0, 0, "gigabyte", "m61p", "GIGABYTE", "GA-M61P-S3", it87xx_probe_spi_flash}, {0x1002, 0x4398, 0x1458, 0x5004, 0x1002, 0x4391, 0x1458, 0xb000, NULL, NULL, "GIGABYTE", "GA-MA78G-DS3H", it87xx_probe_spi_flash},

1 0

[PATCH] Boards: Add general nVidia MCP gpio routine.
by Luc Verhaegen 03 Dec '09

03 Dec '09

Turns out that the AMD 8111 datasheet describes this bit of the MCP perfectly. Signed-off-by: Luc Verhaegen <libv(a)skynet.be> --- board_enable.c | 87 ++++++++++++++++++++++++------------------------------- 1 files changed, 38 insertions(+), 49 deletions(-) diff --git a/board_enable.c b/board_enable.c index 44b1a67..96d764f 100644 --- a/board_enable.c +++ b/board_enable.c @@ -415,38 +415,39 @@ static int board_shuttle_fn25(const char *name) } /** - * No docs, so we are just guessing that these might be individual gpio lines. + * Very similar to AMD 8111 IO Hub. */ -static void nvidia_mcp_gpio_raise(struct pci_dev *dev, uint8_t offset) +static int nvidia_mcp_gpio_set(int gpio, int raise) { + struct pci_dev *dev; uint16_t base; uint8_t tmp; - base = pci_read_long(dev, 0x64) & 0x0000FF00; /* System control area */ - - base += 0xC0; - - /* if anyone knows more about nvidia mcps, feel free to explain this */ - tmp = INB(base + offset); - tmp &= ~0x0F; - tmp |= 0x05; - OUTB(tmp, base + offset); -} - -/** - * Suited for the Gigabyte GA-K8N-SLI: CK804 southbridge. - */ -static int board_ga_k8n_sli(const char *name) -{ - struct pci_dev *dev; + if ((gpio < 0) || (gpio > 31)) { + fprintf(stderr, "\nERROR: unsupported GPIO: %d.\n", gpio); + return -1; + } - dev = pci_dev_find(0x10DE, 0x0050); /* NVIDIA CK804 LPC */ - if (!dev) { - fprintf(stderr, "\nERROR: NVIDIA LPC bridge not found.\n"); + dev = pci_dev_find_vendorclass(0x10DE, 0x0C05); + switch (dev->device_id) { + case 0x0030: /* CK804 */ + case 0x0050: /* MCP04 */ + case 0x0060: /* MCP2 */ + break; + default: + fprintf(stderr, "\nERROR: no nVidia SMBus controller found.\n"); return -1; } - nvidia_mcp_gpio_raise(dev, 0x21); + base = pci_read_long(dev, 0x64) & 0x0000FF00; /* System control area */ + base += 0xC0; + + tmp = INB(base + gpio); + tmp &= ~0x0F; /* null lower nibble */ + tmp |= 0x04; /* gpio -> output. */ + if (raise) + tmp |= 0x01; + OUTB(tmp, base + gpio); return 0; } @@ -454,37 +455,25 @@ static int board_ga_k8n_sli(const char *name) /** * Suited for ASUS P5ND2-SLI Deluxe: LGA775 + nForce4 SLI + MCP04. */ -static int board_asus_p5nd2_sli(const char *name) +static int nvidia_mcp_gpio10_raise(const char *name) { - struct pci_dev *dev; - - dev = pci_dev_find(0x10DE, 0x0030); /* NVIDIA nForce4 ISA Bridge */ - if (!dev) { - fprintf(stderr, "\nERROR: NVIDIA ISA bridge not found.\n"); - return -1; - } - - nvidia_mcp_gpio_raise(dev, 0x10); + return nvidia_mcp_gpio_set(0x10, 1); +} - return 0; +/** + * Suited for the Gigabyte GA-K8N-SLI: CK804 southbridge. + */ +static int nvidia_mcp_gpio21_raise(const char *name) +{ + return nvidia_mcp_gpio_set(0x21, 0x01); } /** * Suited for EPoX EP-8RDA3+: Socket A + nForce2 Ultra 400 + MCP2. */ -static int board_epox_ep_8rda3plus(const char *name) +static int nvidia_mcp_gpio31_raise(const char *name) { - struct pci_dev *dev; - - dev = pci_dev_find(0x10DE, 0x0060); /* NVIDIA nForce2 ISA Bridge */ - if (!dev) { - fprintf(stderr, "\nERROR: NVIDIA ISA bridge not found.\n"); - return -1; - } - - nvidia_mcp_gpio_raise(dev, 0x31); - - return 0; + return nvidia_mcp_gpio_set(0x31, 0x01); } static int board_hp_dl145_g3_enable(const char *name) @@ -1152,16 +1141,16 @@ struct board_pciid_enable board_pciid_enables[] = { {0x8086, 0x1A30, 0x1043, 0x8025, 0x8086, 0x244B, 0x104D, 0x80F0, NULL, NULL, "ASUS", "P4B266-LM", intel_ich_gpio21_raise}, {0x8086, 0x2570, 0x1043, 0x80F2, 0x105A, 0x3373, 0x1043, 0x80F5, NULL, NULL, "ASUS", "P4P800-E Deluxe", intel_ich_gpio21_raise}, {0x10B9, 0x1541, 0, 0, 0x10B9, 0x1533, 0, 0, "asus", "p5a", "ASUS", "P5A", board_asus_p5a}, - {0x10DE, 0x0030, 0x1043, 0x818a, 0x8086, 0x100E, 0x1043, 0x80EE, NULL, NULL, "ASUS", "P5ND2-SLI Deluxe", board_asus_p5nd2_sli}, + {0x10DE, 0x0030, 0x1043, 0x818a, 0x8086, 0x100E, 0x1043, 0x80EE, NULL, NULL, "ASUS", "P5ND2-SLI Deluxe", nvidia_mcp_gpio10_raise}, {0x1106, 0x3149, 0x1565, 0x3206, 0x1106, 0x3344, 0x1565, 0x1202, NULL, NULL, "Biostar", "P4M80-M4", it8705_rom_write_enable}, {0x8086, 0x3590, 0x1028, 0x016c, 0x1000, 0x0030, 0x1028, 0x016c, NULL, NULL, "Dell", "PowerEdge 1850", intel_ich_gpio23_raise}, {0x1106, 0x3038, 0x1019, 0x0996, 0x1106, 0x3177, 0x1019, 0x0996, NULL, NULL, "Elitegroup", "K7VTA3", it8705f_write_enable_2e}, {0x1106, 0x3177, 0x1106, 0x3177, 0x1106, 0x3059, 0x1695, 0x3005, NULL, NULL, "EPoX", "EP-8K5A2", w836xx_memw_enable_2e}, - {0x10EC, 0x8139, 0x1695, 0x9001, 0x11C1, 0x5811, 0x1695, 0x9015, NULL, NULL, "EPoX", "EP-8RDA3+", board_epox_ep_8rda3plus}, + {0x10EC, 0x8139, 0x1695, 0x9001, 0x11C1, 0x5811, 0x1695, 0x9015, NULL, NULL, "EPoX", "EP-8RDA3+", nvidia_mcp_gpio31_raise}, {0x8086, 0x7110, 0, 0, 0x8086, 0x7190, 0, 0, "epox", "ep-bx3", "EPoX", "EP-BX3", board_epox_ep_bx3}, {0x1039, 0x0761, 0, 0, 0, 0, 0, 0, "gigabyte", "2761gxdk", "GIGABYTE", "GA-2761GXDK", it87xx_probe_spi_flash}, {0x1106, 0x3227, 0x1458, 0x5001, 0x10ec, 0x8139, 0x1458, 0xe000, NULL, NULL, "GIGABYTE", "GA-7VT600", it8705_rom_write_enable}, - {0x10DE, 0x0050, 0x1458, 0x0C11, 0x10DE, 0x005e, 0x1458, 0x5000, NULL, NULL, "GIGABYTE", "GA-K8N-SLI", board_ga_k8n_sli}, + {0x10DE, 0x0050, 0x1458, 0x0C11, 0x10DE, 0x005e, 0x1458, 0x5000, NULL, NULL, "GIGABYTE", "GA-K8N-SLI", nvidia_mcp_gpio21_raise}, {0x10de, 0x0360, 0, 0, 0, 0, 0, 0, "gigabyte", "m57sli", "GIGABYTE", "GA-M57SLI-S4", it87xx_probe_spi_flash}, {0x10de, 0x03e0, 0, 0, 0, 0, 0, 0, "gigabyte", "m61p", "GIGABYTE", "GA-M61P-S3", it87xx_probe_spi_flash}, {0x1002, 0x4398, 0x1458, 0x5004, 0x1002, 0x4391, 0x1458, 0xb000, NULL, NULL, "GIGABYTE", "GA-MA78G-DS3H", it87xx_probe_spi_flash}, -- 1.6.0.2 --CE+1k2dSO48ffgeK--

1 0

[PATCH] Board: Add Tyan S2915.
by Luc Verhaegen 03 Dec '09

03 Dec '09

Signed-off-by: Luc Verhaegen <libv(a)skynet.be> --- board_enable.c | 19 +++++++++++++++++++ 1 files changed, 19 insertions(+), 0 deletions(-) diff --git a/board_enable.c b/board_enable.c index 44b1a67..5d8ac92 100644 --- a/board_enable.c +++ b/board_enable.c @@ -434,6 +434,24 @@ static void nvidia_mcp_gpio_raise(struct pci_dev *dev, uint8_t offset) } /** + * Suited for the Tyan S2915: nVidia MCP55. + */ +static int board_tyan_s2915(const char *name) +{ + struct pci_dev *dev; + + dev = pci_dev_find(0x10DE, 0x0368); /* NVIDIA MCP55 SMBus */ + if (!dev) { + fprintf(stderr, "\nERROR: nVidia MCP55 SMBus not found.\n"); + return -1; + } + + nvidia_mcp_gpio_raise(dev, 0x04); + + return 0; +} + +/** * Suited for the Gigabyte GA-K8N-SLI: CK804 southbridge. */ static int board_ga_k8n_sli(const char *name) @@ -1186,6 +1204,7 @@ struct board_pciid_enable board_pciid_enables[] = { {0x10DE, 0x0050, 0x1297, 0x5036, 0x1412, 0x1724, 0x1297, 0x5036, NULL, NULL, "Shuttle", "FN25", board_shuttle_fn25}, {0x1106, 0x3038, 0x0925, 0x1234, 0x1106, 0x3058, 0x15DD, 0x7609, NULL, NULL, "Soyo", "SY-7VCA", board_soyo_sy_7vca}, {0x8086, 0x1076, 0x8086, 0x1176, 0x1106, 0x3059, 0x10f1, 0x2498, NULL, NULL, "Tyan", "S2498 (Tomcat K7M)", board_asus_a7v8x_mx}, + {0x10DE, 0x0369, 0x10F1, 0x2915, 0x10DE, 0x0364, 0x10F1, 0x2915, NULL, NULL, "Tyan", "S2915", board_tyan_s2915}, {0x1106, 0x0314, 0x1106, 0xaa08, 0x1106, 0x3227, 0x1106, 0xAA08, NULL, NULL, "VIA", "EPIA-CN", board_via_epia_sp}, {0x1106, 0x3177, 0x1106, 0xAA01, 0x1106, 0x3123, 0x1106, 0xAA01, NULL, NULL, "VIA", "EPIA M/MII/...", board_via_epia_m}, {0x1106, 0x0259, 0x1106, 0x3227, 0x1106, 0x3065, 0x1106, 0x3149, "via", "epia-n", "VIA", "EPIA-N/NL", board_via_epia_n}, /* TODO: remove coreboot ids */ -- 1.6.0.2 --gKMricLos+KVdGMg--

1 0

Is K7S6A supported by flashrom?
by spirals 02 Dec '09

02 Dec '09

Hi, Ran flashrom and it reports "No EEPROM/flash device found", same with -m ecs:k7s5a. Any suggestions how I can test further. I am running Lenny and my cpu [an AMD 2600] is being mis-reported as 1406? regards, Dave (dja.)

4 6

Re: [flashrom] [coreboot] We have a FOSDEM DevRoom!
by Luc Verhaegen 02 Dec '09

02 Dec '09

On Wed, Dec 02, 2009 at 11:09:04PM +0000, joe(a)settoplinux.org wrote: > > According to the wiki it looks like you want to get into bios security a bit. > This may be an opritune time to introduce SerialICE??? If we can get Stepan to talk about it on FOSDEM, sure :) Luc Verhaegen.

1 0

Unsupportet motherboard Shuttle FS51
by Emil Oehlschläger 02 Dec '09

02 Dec '09

Hi, carldani asked me to send this Mail - so i did. Both files attached to this mail explain themselfs i think and here is link to the motherboard: http://eu.shuttle.com/archive/en/fs51.htm#mainboardfs5 Thanks and good luck, Emil

2 1

Something went terribly wrong...
by Andrea Cucchi 02 Dec '09

02 Dec '09

Here it is what happened andrea@andrea-desktop:~/Scrivania$ sudo flashrom -w W7046IM7.21C flashrom v0.9.1-r706 No coreboot table found. Found chipset "Intel ICH6/ICH6R", enabling flash write... OK. This chipset supports the following protocols: Non-SPI. Disabling flash write protection for board "MSI MS-7046"... OK. Calibrating delay loop... OK. Found chip "Winbond W39V040FA" (512 KB, FWH) at physical address 0xfff80000. Flash image seems to be a legacy BIOS. Disabling checks. Writing flash chip... ERASE FAILED at 0x00000000! Expected=0xff, Read=0x49, failed byte count from 0x00000000-0x0007ffff: 0x53e8d ERASE FAILED! ERASE FAILED! FAILED! Your flash chip is in an unknown state. Get help on IRC at irc.freenode.net channel #flashrom or mail flashrom(a)flashrom.org ------------------------------------------------------------ DO NOT REBOOT OR POWEROFF! I can see only now that I did not write the "v" on the command line, dammit, please help needed. Thank you very much for your atenction in advance.

3 2

[PATCH] Board: Add Abit AN-M2.
by Luc Verhaegen 02 Dec '09

02 Dec '09

--- board_enable.c | 1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/board_enable.c b/board_enable.c index 39cdadc..3af8f05 100644 --- a/board_enable.c +++ b/board_enable.c @@ -1174,6 +1174,7 @@ static int board_asus_a7v600x(const char *name) /* Please keep this list alphabetically ordered by vendor/board name. */ struct board_pciid_enable board_pciid_enables[] = { /* first pci-id set [4], second pci-id set [4], coreboot id [2], vendor name board name flash enable */ + {0x10DE, 0x0547, 0x147B, 0x1C2F, 0x10DE, 0x0548, 0x147B, 0x1C2F, NULL, NULL, "Abit", "AN-M2", nvidia_mcp_gpio2_raise}, {0x8086, 0x2926, 0x147b, 0x1084, 0x11ab, 0x4364, 0x147b, 0x1084, NULL, NULL, "Abit", "IP35", intel_ich_gpio16_raise}, {0x105a, 0x0d30, 0x105a, 0x4d33, 0x8086, 0x1130, 0x8086, 0, NULL, NULL, "Acorp", "6A815EPD", board_acorp_6a815epd}, {0x8086, 0x24D4, 0x1849, 0x24D0, 0x8086, 0x24D5, 0x1849, 0x9739, NULL, NULL, "ASRock", "P4i65GV", intel_ich_gpio23_raise}, -- 1.6.0.2 --17pEHd4RhPHOinZp--

1 0

[PATCH] Board: Add Abit AN-M2.
by Luc Verhaegen 02 Dec '09

02 Dec '09

--- board_enable.c | 19 +++++++++++++++++++ 1 files changed, 19 insertions(+), 0 deletions(-) diff --git a/board_enable.c b/board_enable.c index 44b1a67..2773473 100644 --- a/board_enable.c +++ b/board_enable.c @@ -434,6 +434,24 @@ static void nvidia_mcp_gpio_raise(struct pci_dev *dev, uint8_t offset) } /** + * Suited for the Abit AN-M2: nVidia MCP67. + */ +static int board_abit_an_m2(const char *name) +{ + struct pci_dev *dev; + + dev = pci_dev_find(0x10DE, 0x0542); /* nVidia MCP67 SMBus */ + if (!dev) { + fprintf(stderr, "\nERROR: nVidia MCP67 SMBUS not found.\n"); + return -1; + } + + nvidia_mcp_gpio_raise(dev, 0x02); + + return 0; +} + +/** * Suited for the Gigabyte GA-K8N-SLI: CK804 southbridge. */ static int board_ga_k8n_sli(const char *name) @@ -1137,6 +1155,7 @@ static int board_asus_a7v600x(const char *name) /* Please keep this list alphabetically ordered by vendor/board name. */ struct board_pciid_enable board_pciid_enables[] = { /* first pci-id set [4], second pci-id set [4], coreboot id [2], vendor name board name flash enable */ + {0x10DE, 0x0547, 0x147B, 0x1C2F, 0x10DE, 0x0548, 0x147B, 0x1C2F, NULL, NULL, "Abit", "AN-M2", board_abit_an_m2}, {0x8086, 0x2926, 0x147b, 0x1084, 0x11ab, 0x4364, 0x147b, 0x1084, NULL, NULL, "Abit", "IP35", intel_ich_gpio16_raise}, {0x8086, 0x1130, 0, 0, 0x105a, 0x0d30, 0x105a, 0x4d33, "acorp", "6a815epd", "Acorp", "6A815EPD", board_acorp_6a815epd}, {0x8086, 0x24D4, 0x1849, 0x24D0, 0x8086, 0x24D5, 0x1849, 0x9739, NULL, NULL, "ASRock", "P4i65GV", intel_ich_gpio23_raise}, -- 1.6.0.2 --0F1p//8PRICkK4MW--

1 0

We have a FOSDEM DevRoom!
by Luc Verhaegen 02 Dec '09

02 Dec '09

The kind FOSDEM organizers have given us a DevRoom on saturday the 6th of February, as requested. We got room AW.124, in the AW building on the other side of the campus road from the main building. A "smallish" room at 60 seats, the perfect size for coreboot, and we will have like a window for ventilation and such, which is a nice luxury. Some key european developers are already coming; Carl-Daniel Hailfinger, Peter Stuge and Rudolf Marek, and i hope many more will spend a bit of time and a bit of money (FOSDEM is all free, but travel costs money) on coming to the greatest open source event in europe. We have a total of 6 slots available, two of which should be filled with an "introductory" talk about coreboot and one about flashrom. Introductory here means "this is what $project is, and now we dive straight into the gory details." So there are 4 more which i would like to see filled up in the next month. The page where fosdem info will be kept for coreboot is: http://www.coreboot.org/FOSDEM_2010 Hope to see many of you there! Luc Verhaegen.

4 5

Verbose output of lspci, superiotool and flashrom - AsRock P55 Pro (unsupported)
by Adrian Glaubitz 02 Dec '09

02 Dec '09

Hi, here's the verbose output of lspci, flashrom (r791) and superiotool for the AsRock P55 Pro. The mainboard is not yet supported. root@karl:..src/flashrom> ./flashrom -V > flashrom_p55pro.txt root@karl:..src/flashrom> superiotool -dV > superiotool_p55pro.txt root@karl:..src/flashrom> lspci -nnvvvxxx > lspci_p55pro.txt Adrian

1 0

Mark three boards "known good"
by Idwer Vollering 01 Dec '09

01 Dec '09

See patch. http://www.flashrom.org/pipermail/flashrom/2009-November/000937.html http://www.flashrom.org/pipermail/flashrom/2009-November/000965.html http://www.flashrom.org/pipermail/flashrom/2009-November/001059.html

2 3

[commit] r791 - trunk
by svn＠flashrom.org 01 Dec '09

01 Dec '09

Author: uwe Date: 2009-12-01 13:55:18 +0100 (Tue, 01 Dec 2009) New Revision: 791 Modified: trunk/print.c trunk/print_wiki.c Log: Mark the following boards as OK (no board-enable needed): - AsRock K8S8X (reported by Adrian Glaubitz <adrian.glaubitz(a)gmail.com>) http://www.flashrom.org/pipermail/flashrom/2009-November/000937.html - ASUS K8V-X SE (reported by Adrian Glaubitz <adrian.glaubitz(a)gmail.com>) http://www.flashrom.org/pipermail/flashrom/2009-November/000965.html - DFI Blood-Iron P35 T2RL (reported by Erno Vaurio <ernovaur(a)gmail.com>) http://www.flashrom.org/pipermail/flashrom/2009-November/001059.html Signed-off-by: Idwer Vollering <vidwer(a)gmail.com> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/print.c =================================================================== --- trunk/print.c 2009-11-29 01:19:25 UTC (rev 790) +++ trunk/print.c 2009-12-01 12:55:18 UTC (rev 791) @@ -252,6 +252,7 @@ { "Advantech", "PCM-5820", }, { "ASI", "MB-5BLMP", }, { "ASRock", "A770CrossFire", }, + { "ASRock", "K8S8X", }, { "ASUS", "A7N8X Deluxe", }, { "ASUS", "A7N8X-E Deluxe", }, { "ASUS", "A7V400-MX", }, @@ -265,6 +266,7 @@ { "ASUS", "A8V-E SE", }, { "ASUS", "K8V", }, { "ASUS", "K8V SE Deluxe", }, + { "ASUS", "K8V-X SE", }, { "ASUS", "M2A-MX", }, { "ASUS", "M2A-VM", }, { "ASUS", "M2N-E", }, @@ -281,6 +283,7 @@ { "ASUS", "P6T Deluxe V2", }, { "A-Trend", "ATC-6220", }, { "BCOM", "WinNET100", }, + { "DFI", "Blood-Iron P35 T2RL", }, { "Elitegroup", "K7S5A", }, { "Elitegroup", "P6VAP-A+", }, { "GIGABYTE", "GA-6BXC", }, Modified: trunk/print_wiki.c =================================================================== --- trunk/print_wiki.c 2009-11-29 01:19:25 UTC (rev 790) +++ trunk/print_wiki.c 2009-12-01 12:55:18 UTC (rev 791) @@ -104,6 +104,7 @@ { "Advantech", "PCM-5820", "http://www.emacinc.com/sbc_pc_compatible/pcm_5820.htm" }, { "ASI", "MB-5BLMP", "http://www.hojerteknik.com/winnet.htm" }, { "ASRock", "A770CrossFire", "http://www.asrock.com/mb/overview.asp?Model=A770CrossFire&s=AM2\%2b" }, + { "ASRock", "K8S8X", "http://www.asrock.com/mb/overview.asp?Model=K8S8X" }, { "ASUS", "A7N8X Deluxe", "http://www.asus.com/Product.aspx?P_ID=wAsRYm41KTp78MFC" }, { "ASUS", "A7N8X-E Deluxe", "http://www.asus.com/products.aspx?l1=3&l2=13&l3=56&l4=0&model=217&modelmenu…" }, { "ASUS", "A7V400-MX", "http://www.asus.com.tw/products.aspx?l1=3&l2=13&l3=63&l4=0&model=228&modelm…" }, @@ -117,6 +118,7 @@ { "ASUS", "A8V-E SE", "http://www.asus.com.tw/products.aspx?l1=3&l2=15&l3=143&l4=0&model=576&model…" }, { "ASUS", "K8V", "http://www.asus.com/product.aspx?P_ID=fG2KZOWF7v6MRFRm" }, { "ASUS", "K8V SE Deluxe", "http://www.asus.com/product.aspx?P_ID=65HeDI8XM1u6Uy6o" }, + { "ASUS", "K8V-X SE", "http://asus.com/product.aspx?P_ID=lzDXlbBVHkdckHVr" }, { "ASUS", "M2A-MX", "http://www.asus.com/products.aspx?l1=3&l2=101&l3=583&l4=0&model=1909&modelm…" }, { "ASUS", "M2A-VM", "http://www.asus.com.tw/products.aspx?l1=3&l2=101&l3=496&l4=0&model=1568&mod…" }, { "ASUS", "M2N-E", "http://www.asus.com/products.aspx?l1=3&l2=101&l3=308&l4=0&model=1181&modelm…" }, @@ -133,6 +135,7 @@ { "ASUS", "P6T Deluxe V2", "http://www.asus.com/product.aspx?P_ID=iRlP8RG9han6saZx" }, { "A-Trend", "ATC-6220", "http://www.motherboard.cz/mb/atrend/atc6220.htm" }, { "BCOM", "WinNET100", "http://www.coreboot.org/BCOM_WINNET100" }, + { "DFI", "Blood-Iron P35 T2RL", "http://lp.lanparty.com.tw/portal/CM/cmproduct/XX_cmproddetail/XX_WbProdsWin…" }, { "Elitegroup", "K7S5A", "http://www.ecs.com.tw/ECSWebSite/Products/ProductsDetail.aspx?detailid=279&…" }, { "Elitegroup", "P6VAP-A+", "http://www.ecs.com.tw/ECSWebSite/Products/ProductsDetail.aspx?detailid=117&…" }, { "GIGABYTE", "GA-6BXC", "http://www.gigabyte.com.tw/Products/Motherboard/Products_Spec.aspx?ClassVal…" }, @@ -282,6 +285,7 @@ const struct board_info_notes boards_notes[] = { /* Verified working boards that don't need write-enables. */ { "ASI", "MB-5BLMP", "Used in the IGEL WinNET III thin client." }, + { "ASRock", "K8S8X", "The Super I/O isn't found on this board. See http://www.flashrom.org/pipermail/flashrom/2009-November/000937.html." }, { "ASUS", "A8V-E SE", "See http://www.coreboot.org/pipermail/coreboot/2007-October/026496.html." }, { "ASUS", "M2A-VM", "See http://www.coreboot.org/pipermail/coreboot/2007-September/025281.html." }, { "BCOM", "WinNET100", "Used in the IGEL-316 thin client." },

1 0

[PATCH] TotalPhase Cheetah support stub
by Carl-Daniel Hailfinger 29 Nov '09

29 Nov '09

I wrote this Cheetah support stub months ago and carried it forward over various interface changes. I don't have the hardware, so I'm not really motivated to finish this. This patch does: - Hook up Cheetah support in the generic code - Make sure it is disabled by default (zero footprint in the binary) - Provide some #if 0 code as a good starting point - Provide a compilable skeleton to be filled in TODO for anyone who cares about Cheetah support: - Implement cheetah_spi_init - Implement cheetah_spi_shutdown - Add an #include for the cheetah headers - Change #if 0 to #if 1. Given that this patch makes sure to have zero impact on the binary (because it is compiled out by default) and because it lowers the barrier for someone else to come and implement the rest of cheetah support, I'm for merging. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-cheetah/flashrom.8 =================================================================== --- flashrom-cheetah/flashrom.8 (Revision 777) +++ flashrom-cheetah/flashrom.8 (Arbeitskopie) @@ -154,6 +154,8 @@ .sp .BR "* buspiratespi" " (for flash ROMs attached to a Bus Pirate)" .sp +.BR "* cheetah" " (for flash ROMs attached to a TotalPhase Cheetah SPI programmer)" +.sp The dummy programmer has an optional parameter specifying the bus types it should support. For that you have to use the .B "flashrom -p dummy:type" Index: flashrom-cheetah/flash.h =================================================================== --- flashrom-cheetah/flash.h (Revision 777) +++ flashrom-cheetah/flash.h (Arbeitskopie) @@ -107,6 +107,9 @@ #if BUSPIRATE_SPI_SUPPORT == 1 PROGRAMMER_BUSPIRATESPI, #endif +#if CHEETAH_SUPPORT == 1 + PROGRAMMER_CHEETAH, +#endif PROGRAMMER_INVALID /* This must always be the last entry. */ }; @@ -497,6 +500,14 @@ int buspirate_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); int buspirate_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len); +/* cheetah.c */ +int cheetah_spi_init(void); +int cheetah_spi_shutdown(void); +int cheetah_spi_command(unsigned int writecnt, unsigned int readcnt, + const unsigned char *writearr, unsigned char *readarr); +int cheetah_spi_write_256(struct flashchip *flash, uint8_t *buf); +int cheetah_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len); + /* flashrom.c */ extern char *programmer_param; extern int verbose; @@ -538,6 +549,9 @@ #if FT2232_SPI_SUPPORT == 1 SPI_CONTROLLER_FT2232, #endif +#if CHEETAH_SUPPORT == 1 + SPI_CONTROLLER_CHEETAH, +#endif #if DUMMY_SUPPORT == 1 SPI_CONTROLLER_DUMMY, #endif Index: flashrom-cheetah/spi.c =================================================================== --- flashrom-cheetah/spi.c (Revision 777) +++ flashrom-cheetah/spi.c (Arbeitskopie) @@ -91,6 +91,15 @@ }, #endif +#if CHEETAH_SUPPORT == 1 + { /* SPI_CONTROLLER_CHEETAH */ + .command = cheetah_spi_command, + .multicommand = default_spi_send_multicommand, + .read = cheetah_spi_read, + .write_256 = spi_chip_write_1, + }, +#endif + #if DUMMY_SUPPORT == 1 { /* SPI_CONTROLLER_DUMMY */ .command = dummy_spi_send_command, @@ -316,6 +325,9 @@ #if FT2232_SPI_SUPPORT == 1 case SPI_CONTROLLER_FT2232: #endif +#if CHEETAH_SUPPORT == 1 + case SPI_CONTROLLER_CHEETAH: +#endif #if DUMMY_SUPPORT == 1 case SPI_CONTROLLER_DUMMY: #endif Index: flashrom-cheetah/Makefile =================================================================== --- flashrom-cheetah/Makefile (Revision 777) +++ flashrom-cheetah/Makefile (Arbeitskopie) @@ -71,6 +71,9 @@ # Bitbanging SPI infrastructure is not used yet. CONFIG_BITBANG_SPI ?= no +# Cheetah support is unfinished. +CONFIG_CHEETAH ?= no + # Always enable 3Com NICs for now. CONFIG_NIC3COM ?= yes @@ -108,6 +111,11 @@ OBJS += bitbang_spi.o endif +ifeq ($(CONFIG_CHEETAH), yes) +FEATURE_CFLAGS += -D'CHEETAH_SUPPORT=1' +OBJS += cheetah.o +endif + ifeq ($(CONFIG_NIC3COM), yes) FEATURE_CFLAGS += -D'NIC3COM_SUPPORT=1' OBJS += nic3com.o Index: flashrom-cheetah/cheetah.c =================================================================== --- flashrom-cheetah/cheetah.c (Revision 0) +++ flashrom-cheetah/cheetah.c (Revision 0) @@ -0,0 +1,72 @@ +/* + * This file is part of the flashrom project. + * + * Copyright (C) 2009 Carl-Daniel Hailfinger + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * As a special exception, you may also incorporate this code into programs + * licensed under later versions of the GNU GPL provided your changes to + * this code are made available under the same conditions as the original code. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <string.h> +#include <stdlib.h> +#include "flash.h" + +int cheetah_spi_init(void) +{ + printf("Cheetah support not yet implemented completely.\n"); + buses_supported = CHIP_BUSTYPE_SPI; + spi_controller = SPI_CONTROLLER_CHEETAH; + return 0; +} + +int cheetah_spi_shutdown(void) +{ + return 0; +} + +int cheetah_spi_command(unsigned int writecnt, unsigned int readcnt, + const unsigned char *writearr, unsigned char *readarr) +{ + unsigned char *bufout = malloc(writecnt + readcnt); + unsigned char *bufin = malloc(writecnt + readcnt); + memcpy(bufout, writearr, writecnt); + /* Shift out 0x00 while reading data. */ + memset(bufout + writecnt, 0x00, readcnt); + /* Make sure any non-read data is 0xff. */ + memset(bufin + writecnt, 0xff, readcnt); +#if 0 + ch_spi_queue_clear(handle); + ch_spi_queue_oe(handle, 1); + ch_spi_queue_ss(handle, 1); + ch_spi_queue_array(handle, writecnt + readcnt, bufout); + ch_spi_queue_ss(handle, 0); + ch_spi_queue_oe(handle, 0); + ch_spi_batch_shift(handle, writecnt + readcnt, bufin); + ch_spi_queue_clear(handle); +#endif + memcpy(readarr, bufin + writecnt, readcnt); + free(bufout); + free(bufin); + return 0; +} + +int cheetah_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len) +{ + /* Maximum read length is 256 bytes. */ + return spi_read_chunked(flash, buf, start, len, 256); +} + +/* We could do 256-byte writes, but for now we use the generic 1-byte code. */ Index: flashrom-cheetah/flashrom.c =================================================================== --- flashrom-cheetah/flashrom.c (Revision 777) +++ flashrom-cheetah/flashrom.c (Arbeitskopie) @@ -223,6 +223,25 @@ }, #endif +#if CHEETAH_SUPPORT == 1 + { + .name = "cheetah", + .init = cheetah_spi_init, + .shutdown = cheetah_spi_shutdown, + .map_flash_region = dummy_map, + .unmap_flash_region = dummy_unmap, + .chip_readb = noop_chip_readb, + .chip_readw = fallback_chip_readw, + .chip_readl = fallback_chip_readl, + .chip_readn = fallback_chip_readn, + .chip_writeb = noop_chip_writeb, + .chip_writew = fallback_chip_writew, + .chip_writel = fallback_chip_writel, + .chip_writen = fallback_chip_writen, + .delay = internal_delay, + }, +#endif + {}, /* This entry corresponds to PROGRAMMER_INVALID. */ }; -- Developer quote of the month: "We are juggling too many chainsaws and flaming arrows and tigers."

2 3

SST SST49LF160C not working
by Kevin O'Connor 29 Nov '09

29 Nov '09

Hi, I have an "SST SST49LF160C" part that I've tried to use in my epia-cn board (Jetway). Reading seems to work okay, but erase and write fail. My other parts (winbond based bios savior, a winbond chip, and an "SST SST49LF080A") all work okay in the board. Attached are some logs. These were taken over ssh and without the bios savior installed. I tried writing and erasing on the console and see the same failure. On IRC, Uwe mentioned there may be a problem with the southbridge only mapping 1MB. Also, with Uwe's advise, I tried writing a variety of images (eg, all 0xff, all 0x00, etc.) but no luck. -Kevin

1 0

[commit] r790 - trunk
by svn＠flashrom.org 28 Nov '09

28 Nov '09

Author: libv Date: 2009-11-29 02:19:25 +0100 (Sun, 29 Nov 2009) New Revision: 790 Modified: trunk/board_enable.c Log: Board enable for Shuttle AK31. All AK31 versions, 1.x, 2.x and 3.x are supported by this board enable. Sadly this board can not be autodetected. Re-uses the epox ep 8k5a2 board enable, which now lost its check for the VT8235 ISA bridge and got renamed to w836xx_memw_enable_2e. Signed-off-by: Luc Verhaegen <libv(a)skynet.be> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Mateusz Murawski <matowy(a)tlen.pl> Modified: trunk/board_enable.c =================================================================== --- trunk/board_enable.c 2009-11-28 21:12:58 UTC (rev 789) +++ trunk/board_enable.c 2009-11-29 01:19:25 UTC (rev 790) @@ -297,18 +297,13 @@ } /** - * Suited for EPoX EP-8K5A2 and Albatron PM266A Pro. + * Suited for: + * - EPoX EP-8K5A2: VIA KT333 + VT8235. + * - Albatron PM266A Pro: VIA P4M266A + VT8235. + * - Shuttle AK31 (all versions): VIA KT266 + VT8233. */ -static int board_epox_ep_8k5a2(const char *name) +static int w836xx_memw_enable_2e(const char *name) { - struct pci_dev *dev; - - dev = pci_dev_find(0x1106, 0x3177); /* VT8235 ISA bridge */ - if (!dev) { - fprintf(stderr, "\nERROR: VT8235 ISA bridge not found.\n"); - return -1; - } - w836xx_memw_enable(0x2E); return 0; @@ -1146,7 +1141,7 @@ {0x8086, 0x1130, 0, 0, 0x105a, 0x0d30, 0x105a, 0x4d33, "acorp", "6a815epd", "Acorp", "6A815EPD", board_acorp_6a815epd}, {0x8086, 0x24D4, 0x1849, 0x24D0, 0x8086, 0x24D5, 0x1849, 0x9739, NULL, NULL, "ASRock", "P4i65GV", intel_ich_gpio23_raise}, {0x1022, 0x746B, 0x1022, 0x36C0, 0, 0, 0, 0, "AGAMI", "ARUMA", "agami", "Aruma", w83627hf_gpio24_raise_2e}, - {0x1106, 0x3177, 0x17F2, 0x3177, 0x1106, 0x3148, 0x17F2, 0x3148, NULL, NULL, "Albatron", "PM266A*", board_epox_ep_8k5a2}, + {0x1106, 0x3177, 0x17F2, 0x3177, 0x1106, 0x3148, 0x17F2, 0x3148, NULL, NULL, "Albatron", "PM266A", w836xx_memw_enable_2e}, {0x1106, 0x3205, 0x1106, 0x3205, 0x10EC, 0x8139, 0xA0A0, 0x0477, NULL, NULL, "AOpen", "vKM400Am-S", board_aopen_vkm400}, {0x1022, 0x2090, 0, 0, 0x1022, 0x2080, 0, 0, "artecgroup", "dbe61", "Artec Group", "DBE61", board_artecgroup_dbe6x}, {0x1022, 0x2090, 0, 0, 0x1022, 0x2080, 0, 0, "artecgroup", "dbe62", "Artec Group", "DBE62", board_artecgroup_dbe6x}, @@ -1161,7 +1156,7 @@ {0x1106, 0x3149, 0x1565, 0x3206, 0x1106, 0x3344, 0x1565, 0x1202, NULL, NULL, "Biostar", "P4M80-M4", it8705_rom_write_enable}, {0x8086, 0x3590, 0x1028, 0x016c, 0x1000, 0x0030, 0x1028, 0x016c, NULL, NULL, "Dell", "PowerEdge 1850", intel_ich_gpio23_raise}, {0x1106, 0x3038, 0x1019, 0x0996, 0x1106, 0x3177, 0x1019, 0x0996, NULL, NULL, "Elitegroup", "K7VTA3", it8705f_write_enable_2e}, - {0x1106, 0x3177, 0x1106, 0x3177, 0x1106, 0x3059, 0x1695, 0x3005, NULL, NULL, "EPoX", "EP-8K5A2", board_epox_ep_8k5a2}, + {0x1106, 0x3177, 0x1106, 0x3177, 0x1106, 0x3059, 0x1695, 0x3005, NULL, NULL, "EPoX", "EP-8K5A2", w836xx_memw_enable_2e}, {0x10EC, 0x8139, 0x1695, 0x9001, 0x11C1, 0x5811, 0x1695, 0x9015, NULL, NULL, "EPoX", "EP-8RDA3+", board_epox_ep_8rda3plus}, {0x8086, 0x7110, 0, 0, 0x8086, 0x7190, 0, 0, "epox", "ep-bx3", "EPoX", "EP-BX3", board_epox_ep_bx3}, {0x1039, 0x0761, 0, 0, 0, 0, 0, 0, "gigabyte", "2761gxdk", "GIGABYTE", "GA-2761GXDK", it87xx_probe_spi_flash}, @@ -1186,6 +1181,7 @@ {0x1106, 0x0571, 0x1462, 0x7120, 0x1106, 0x3065, 0x1462, 0x7120, NULL, NULL, "MSI", "MS-6712 (KT4V)", board_msi_kt4v}, {0x8086, 0x2658, 0x1462, 0x7046, 0x1106, 0x3044, 0x1462, 0x046d, NULL, NULL, "MSI", "MS-7046", intel_ich_gpio19_raise}, {0x10de, 0x005e, 0, 0, 0, 0, 0, 0, "msi", "k8n-neo3", "MSI", "MS-7135 (K8N Neo3)", w83627thf_gpio4_4_raise_4e}, + {0x1106, 0x3099, 0, 0, 0x1106, 0x3074, 0, 0, "shuttle", "ak31", "Shuttle", "AK31", w836xx_memw_enable_2e}, {0x1106, 0x3104, 0x1297, 0xa238, 0x1106, 0x3059, 0x1297, 0xc063, NULL, NULL, "Shuttle", "AK38N", it8705f_write_enable_2e}, {0x10DE, 0x0050, 0x1297, 0x5036, 0x1412, 0x1724, 0x1297, 0x5036, NULL, NULL, "Shuttle", "FN25", board_shuttle_fn25}, {0x1106, 0x3038, 0x0925, 0x1234, 0x1106, 0x3058, 0x15DD, 0x7609, NULL, NULL, "Soyo", "SY-7VCA", board_soyo_sy_7vca},

1 0

non-working board report for Asrock K7S41GX with flashrom r711
by Putlinuxonit 28 Nov '09

28 Nov '09

Hi, Just want to report a non-working board - the Asrock K7S41GX, tested with flashrom r711 and superiotool r4623. first some brief details ... Board: Asrock K7S1GX Bios Vendor: AMI Bios Version: P1.90 root@ubuntu:~# lspci 00:00.0 Host bridge: Silicon Integrated Systems [SiS] 741/741GX/M741 Host (rev 03) 00:01.0 PCI bridge: Silicon Integrated Systems [SiS] SiS AGP Port (virtual PCI-to-PCI bridge) 00:02.0 ISA bridge: Silicon Integrated Systems [SiS] SiS963 [MuTIOL Media IO] (rev 25) 00:02.1 SMBus: Silicon Integrated Systems [SiS] SiS961/2 SMBus Controller 00:02.5 IDE interface: Silicon Integrated Systems [SiS] 5513 [IDE] 00:02.7 Multimedia audio controller: Silicon Integrated Systems [SiS] AC'97 Sound Controller (rev a0) 00:03.0 USB Controller: Silicon Integrated Systems [SiS] USB 1.1 Controller (rev 0f) 00:03.1 USB Controller: Silicon Integrated Systems [SiS] USB 1.1 Controller (rev 0f) 00:03.2 USB Controller: Silicon Integrated Systems [SiS] USB 2.0 Controller 00:04.0 Ethernet controller: Silicon Integrated Systems [SiS] SiS900 PCI Fast Ethernet (rev 90) 01:00.0 VGA compatible controller: Silicon Integrated Systems [SiS] 661/741/760 PCI/AGP or 662/761Gx PCIE VGA Display Adapter flashrom v0.9.1-r711 No coreboot table found. This chipset supports the following protocols: Non-SPI. WARNING: No chipset found. Flash detection will most likely fail. Calibrating delay loop... OK. No EEPROM/flash device found. If you know which flash chip you have, and if this version of flashrom supports a similar flash chip, you can try to force read your chip. Run: flashrom -f -r -c similar_supported_flash_chip filename Note: flashrom can never write when the flash chip isn't found automatically. root@ubuntu:~# ./superiotool/superiotool superiotool r4623 Found Winbond W83697HF/F/HG (id=0x60, rev=0x12) at 0x2e Cheers, -- Udu Ogah .~~~~~~~~~~.

3 6

[Patch] Boards: Fix up MSI KT4V.
by Luc Verhaegen 28 Nov '09

28 Nov '09

Luc Verhaegen.

2 2

[commit] r789 - trunk
by svn＠flashrom.org 28 Nov '09

28 Nov '09

Author: libv Date: 2009-11-28 22:12:58 +0100 (Sat, 28 Nov 2009) New Revision: 789 Modified: trunk/board_enable.c Log: Boards: Fix up MSI KT4V board enable. * Add autodetection and remove match strings. * Make use of vt823x_set_all_writes_to_lpc. Signed-off-by: Luc Verhaegen <libv(a)skynet.be> Acked-by: Sean Nelson <audiohacked(a)gmail.com> Modified: trunk/board_enable.c =================================================================== --- trunk/board_enable.c 2009-11-28 18:26:21 UTC (rev 788) +++ trunk/board_enable.c 2009-11-28 21:12:58 UTC (rev 789) @@ -874,12 +874,10 @@ * Suited for: * - MSI KT4V and KT4V-L: AMD K7 + VIA KT400 + VT8235 * - MSI KT4 Ultra: AMD K7 + VIA KT400 + VT8235 - * - MSI KT3 Ultra2: AMD K7 + VIA KT333 + VT8235 */ static int board_msi_kt4v(const char *name) { struct pci_dev *dev; - uint8_t val; dev = pci_dev_find(0x1106, 0x3177); /* VT8235 ISA bridge */ if (!dev) { @@ -887,9 +885,7 @@ return -1; } - val = pci_read_byte(dev, 0x59); - val &= 0x0c; - pci_write_byte(dev, 0x59, val); + vt823x_set_all_writes_to_lpc(dev); vt823x_gpio_set(dev, 12, 1); w836xx_memw_enable(0x2E); @@ -1187,7 +1183,7 @@ {0x8086, 0x2411, 0x8086, 0x2411, 0x8086, 0x7125, 0x0e11, 0xb165, NULL, NULL, "Mitac", "6513WU", board_mitac_6513wu}, {0x13f6, 0x0111, 0x1462, 0x5900, 0x1106, 0x3177, 0x1106, 0, "msi", "kt4ultra", "MSI", "MS-6590 (KT4 Ultra)",board_msi_kt4v}, {0x1106, 0x3149, 0x1462, 0x7094, 0x10ec, 0x8167, 0x1462, 0x094c, NULL, NULL, "MSI", "MS-6702E (K8T Neo2-F)",w83627thf_gpio4_4_raise_2e}, - {0x1106, 0x0571, 0x1462, 0x7120, 0, 0, 0, 0, "msi", "kt4v", "MSI", "MS-6712 (KT4V)", board_msi_kt4v}, + {0x1106, 0x0571, 0x1462, 0x7120, 0x1106, 0x3065, 0x1462, 0x7120, NULL, NULL, "MSI", "MS-6712 (KT4V)", board_msi_kt4v}, {0x8086, 0x2658, 0x1462, 0x7046, 0x1106, 0x3044, 0x1462, 0x046d, NULL, NULL, "MSI", "MS-7046", intel_ich_gpio19_raise}, {0x10de, 0x005e, 0, 0, 0, 0, 0, 0, "msi", "k8n-neo3", "MSI", "MS-7135 (K8N Neo3)", w83627thf_gpio4_4_raise_4e}, {0x1106, 0x3104, 0x1297, 0xa238, 0x1106, 0x3059, 0x1297, 0xc063, NULL, NULL, "Shuttle", "AK38N", it8705f_write_enable_2e},

1 0

[PATCH] Boards: Fix up MSI KT4V board enable.
by Luc Verhaegen 28 Nov '09

28 Nov '09

* Add autodetection and remove match strings. * Make use of vt823x_set_all_writes_to_lpc. Signed-off-by: Luc Verhaegen <libv(a)skynet.be> --- board_enable.c | 8 ++------ 1 files changed, 2 insertions(+), 6 deletions(-) diff --git a/board_enable.c b/board_enable.c index e6d37c1..2c1d8b5 100644 --- a/board_enable.c +++ b/board_enable.c @@ -874,12 +874,10 @@ static int board_aopen_vkm400(const char *name) * Suited for: * - MSI KT4V and KT4V-L: AMD K7 + VIA KT400 + VT8235 * - MSI KT4 Ultra: AMD K7 + VIA KT400 + VT8235 - * - MSI KT3 Ultra2: AMD K7 + VIA KT333 + VT8235 */ static int board_msi_kt4v(const char *name) { struct pci_dev *dev; - uint8_t val; dev = pci_dev_find(0x1106, 0x3177); /* VT8235 ISA bridge */ if (!dev) { @@ -887,9 +885,7 @@ static int board_msi_kt4v(const char *name) return -1; } - val = pci_read_byte(dev, 0x59); - val &= 0x0c; - pci_write_byte(dev, 0x59, val); + vt823x_set_all_writes_to_lpc(dev); vt823x_gpio_set(dev, 12, 1); w836xx_memw_enable(0x2E); @@ -1187,7 +1183,7 @@ struct board_pciid_enable board_pciid_enables[] = { {0x8086, 0x2411, 0x8086, 0x2411, 0x8086, 0x7125, 0x0e11, 0xb165, NULL, NULL, "Mitac", "6513WU", board_mitac_6513wu}, {0x13f6, 0x0111, 0x1462, 0x5900, 0x1106, 0x3177, 0x1106, 0, "msi", "kt4ultra", "MSI", "MS-6590 (KT4 Ultra)",board_msi_kt4v}, {0x1106, 0x3149, 0x1462, 0x7094, 0x10ec, 0x8167, 0x1462, 0x094c, NULL, NULL, "MSI", "MS-6702E (K8T Neo2-F)",w83627thf_gpio4_4_raise_2e}, - {0x1106, 0x0571, 0x1462, 0x7120, 0, 0, 0, 0, "msi", "kt4v", "MSI", "MS-6712 (KT4V)", board_msi_kt4v}, + {0x1106, 0x0571, 0x1462, 0x7120, 0x1106, 0x3065, 0x1462, 0x7120, NULL, NULL, "MSI", "MS-6712 (KT4V)", board_msi_kt4v}, {0x8086, 0x2658, 0x1462, 0x7046, 0x1106, 0x3044, 0x1462, 0x046d, NULL, NULL, "MSI", "MS-7046", intel_ich_gpio19_raise}, {0x10de, 0x005e, 0, 0, 0, 0, 0, 0, "msi", "k8n-neo3", "MSI", "MS-7135 (K8N Neo3)", w83627thf_gpio4_4_raise_4e}, {0x1106, 0x3104, 0x1297, 0xa238, 0x1106, 0x3059, 0x1297, 0xc063, NULL, NULL, "Shuttle", "AK38N", it8705f_write_enable_2e}, -- 1.6.0.2 --vtzGhvizbBRQ85DL--

1 0

[PATCH] Board: Make Acorp 6A815EPD autodetectable.
by Luc Verhaegen 28 Nov '09

28 Nov '09

Add subsystem id for hostbridge match for Acorp 6A815EPD; even though it reads "intel", NULL, this, together with the promise ultra100 chip and subsystem ids, should form a unique enough match for us to depend upon. This version swaps both id blocks around to pass through board id matching code unharmed. Future board id matching code will no longer stop such things, but for now, we need to still do this. Signed-off-by: Luc Verhaegen <libv(a)skynet.be> --- board_enable.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/board_enable.c b/board_enable.c index e6d37c1..aa18e71 100644 --- a/board_enable.c +++ b/board_enable.c @@ -1147,7 +1147,7 @@ static int board_asus_a7v600x(const char *name) struct board_pciid_enable board_pciid_enables[] = { /* first pci-id set [4], second pci-id set [4], coreboot id [2], vendor name board name flash enable */ {0x8086, 0x2926, 0x147b, 0x1084, 0x11ab, 0x4364, 0x147b, 0x1084, NULL, NULL, "Abit", "IP35", intel_ich_gpio16_raise}, - {0x8086, 0x1130, 0, 0, 0x105a, 0x0d30, 0x105a, 0x4d33, "acorp", "6a815epd", "Acorp", "6A815EPD", board_acorp_6a815epd}, + {0x105a, 0x0d30, 0x105a, 0x4d33, 0x8086, 0x1130, 0x8086, 0, NULL, NULL, "Acorp", "6A815EPD", board_acorp_6a815epd}, {0x8086, 0x24D4, 0x1849, 0x24D0, 0x8086, 0x24D5, 0x1849, 0x9739, NULL, NULL, "ASRock", "P4i65GV", intel_ich_gpio23_raise}, {0x1022, 0x746B, 0x1022, 0x36C0, 0, 0, 0, 0, "AGAMI", "ARUMA", "agami", "Aruma", w83627hf_gpio24_raise_2e}, {0x1106, 0x3177, 0x17F2, 0x3177, 0x1106, 0x3148, 0x17F2, 0x3148, NULL, NULL, "Albatron", "PM266A*", board_epox_ep_8k5a2}, -- 1.6.0.2 --tKW2IUtsqtDRztdT--

1 0

[commit] r788 - trunk
by svn＠flashrom.org 28 Nov '09

28 Nov '09

Author: libv Date: 2009-11-28 19:26:21 +0100 (Sat, 28 Nov 2009) New Revision: 788 Modified: trunk/board_enable.c Log: Boards: Add Asus P4B266LM (Sony Vaio PCV-RX650). Signed-off-by: Luc Verhaegen <libv(a)skynet.be> Acked-by: Allan Bjorklund <abjork(a)speakeasy.net> Modified: trunk/board_enable.c =================================================================== --- trunk/board_enable.c 2009-11-28 18:16:31 UTC (rev 787) +++ trunk/board_enable.c 2009-11-28 18:26:21 UTC (rev 788) @@ -770,7 +770,9 @@ } /** - * Suited for Asus P4P800-E Deluxe: Intel socket478 + 865PE + ICH5R. + * Suited for: + * - Asus P4B266LM (Sony Vaio PCV-RX650): socket478 + 845D + ICH2. + * - Asus P4P800-E Deluxe: Intel socket478 + 865PE + ICH5R. */ static int intel_ich_gpio21_raise(const char *name) { @@ -1156,6 +1158,7 @@ {0x1106, 0x3189, 0x1043, 0x807F, 0x1106, 0x3177, 0x1043, 0x808C, NULL, NULL, "ASUS", "A7V8X", board_asus_a7v8x}, {0x1106, 0x3177, 0x1043, 0x80A1, 0x1106, 0x3205, 0x1043, 0x8118, NULL, NULL, "ASUS", "A7V8X-MX SE", board_asus_a7v8x_mx}, {0x8086, 0x1a30, 0x1043, 0x8070, 0x8086, 0x244b, 0x1043, 0x8028, NULL, NULL, "ASUS", "P4B266", intel_ich_gpio22_raise}, + {0x8086, 0x1A30, 0x1043, 0x8025, 0x8086, 0x244B, 0x104D, 0x80F0, NULL, NULL, "ASUS", "P4B266-LM", intel_ich_gpio21_raise}, {0x8086, 0x2570, 0x1043, 0x80F2, 0x105A, 0x3373, 0x1043, 0x80F5, NULL, NULL, "ASUS", "P4P800-E Deluxe", intel_ich_gpio21_raise}, {0x10B9, 0x1541, 0, 0, 0x10B9, 0x1533, 0, 0, "asus", "p5a", "ASUS", "P5A", board_asus_p5a}, {0x10DE, 0x0030, 0x1043, 0x818a, 0x8086, 0x100E, 0x1043, 0x80EE, NULL, NULL, "ASUS", "P5ND2-SLI Deluxe", board_asus_p5nd2_sli},

1 0

[commit] r787 - trunk
by svn＠flashrom.org 28 Nov '09

28 Nov '09

Author: libv Date: 2009-11-28 19:16:31 +0100 (Sat, 28 Nov 2009) New Revision: 787 Modified: trunk/board_enable.c Log: Boards: Add board match for Asrock P4i65GV. Signed-off-by: Luc Verhaegen <libv(a)skynet.be> Acked-by: Idwer Vollering <vidwer(a)gmail.com> Modified: trunk/board_enable.c =================================================================== --- trunk/board_enable.c 2009-11-28 18:07:51 UTC (rev 786) +++ trunk/board_enable.c 2009-11-28 18:16:31 UTC (rev 787) @@ -786,7 +786,9 @@ } /** - * Suited for Dell Poweredge 1850: Intel PPGA604 + E7520 + ICH5R. + * Suited for: + * - Dell Poweredge 1850: Intel PPGA604 + E7520 + ICH5R. + * - ASRock P4i65GV: Intel Socket478 + 865GV + ICH5R. */ static int intel_ich_gpio23_raise(const char *name) { @@ -1144,6 +1146,7 @@ /* first pci-id set [4], second pci-id set [4], coreboot id [2], vendor name board name flash enable */ {0x8086, 0x2926, 0x147b, 0x1084, 0x11ab, 0x4364, 0x147b, 0x1084, NULL, NULL, "Abit", "IP35", intel_ich_gpio16_raise}, {0x8086, 0x1130, 0, 0, 0x105a, 0x0d30, 0x105a, 0x4d33, "acorp", "6a815epd", "Acorp", "6A815EPD", board_acorp_6a815epd}, + {0x8086, 0x24D4, 0x1849, 0x24D0, 0x8086, 0x24D5, 0x1849, 0x9739, NULL, NULL, "ASRock", "P4i65GV", intel_ich_gpio23_raise}, {0x1022, 0x746B, 0x1022, 0x36C0, 0, 0, 0, 0, "AGAMI", "ARUMA", "agami", "Aruma", w83627hf_gpio24_raise_2e}, {0x1106, 0x3177, 0x17F2, 0x3177, 0x1106, 0x3148, 0x17F2, 0x3148, NULL, NULL, "Albatron", "PM266A*", board_epox_ep_8k5a2}, {0x1106, 0x3205, 0x1106, 0x3205, 0x10EC, 0x8139, 0xA0A0, 0x0477, NULL, NULL, "AOpen", "vKM400Am-S", board_aopen_vkm400},

1 0

[commit] r786 - trunk
by svn＠flashrom.org 28 Nov '09

28 Nov '09

Author: libv Date: 2009-11-28 19:07:51 +0100 (Sat, 28 Nov 2009) New Revision: 786 Modified: trunk/board_enable.c Log: Boards: provide enormous intel_ich_gpio_set function. This code sets gpio lines on random intel ichs. Detects all currently known intel ICHs, checks gpio lines, and then sets them accordingly. Signed-off-by: Luc Verhaegen <libv(a)skynet.be> Acked-by: Idwer Vollering <vidwer(a)gmail.com> Modified: trunk/board_enable.c =================================================================== --- trunk/board_enable.c 2009-11-27 17:49:42 UTC (rev 785) +++ trunk/board_enable.c 2009-11-28 18:07:51 UTC (rev 786) @@ -523,32 +523,6 @@ } /** - * Suited for Acorp 6A815EPD. - */ -static int board_acorp_6a815epd(const char *name) -{ - struct pci_dev *dev; - uint16_t port; - uint8_t val; - - dev = pci_dev_find(0x8086, 0x2440); /* Intel ICH2 LPC */ - if (!dev) { - fprintf(stderr, "\nERROR: ICH2 LPC bridge not found.\n"); - return -1; - } - - /* Use GPIOBASE register to find where the GPIO is mapped. */ - port = (pci_read_word(dev, 0x58) & 0xFFC0) + 0xE; - - val = INB(port); - val |= 0x80; /* Top Block Lock -- pin 8 of PLCC32 */ - val |= 0x40; /* Lower Blocks Lock -- pin 7 of PLCC32 */ - OUTB(val, port); - - return 0; -} - -/** * Suited for Artec Group DBE61 and DBE62. */ static int board_artecgroup_dbe6x(const char *name) @@ -590,105 +564,262 @@ } /** - * Set the specified GPIO on the specified ICHx southbridge to high. - * - * @param name The name of this board. - * @param ich_vendor PCI vendor ID of the specified ICHx southbridge. - * @param ich_device PCI device ID of the specified ICHx southbridge. - * @param gpiobase_reg GPIOBASE register offset in the LPC bridge. - * @param gp_lvl Offset of GP_LVL register in I/O space, relative to GPIOBASE. - * @param gp_lvl_bitmask GP_LVL bitmask (set GPIO bits to 1, all others to 0). - * @param gpio_bit The bit (GPIO) which shall be set to high. - * @return If the write-enable was successful return 0, otherwise return -1. + * Set a GPIO line on a given intel ICH LPC controller. */ -static int ich_gpio_raise(const char *name, uint16_t ich_vendor, - uint16_t ich_device, uint8_t gpiobase_reg, - uint8_t gp_lvl, uint32_t gp_lvl_bitmask, - unsigned int gpio_bit) +static int intel_ich_gpio_set(int gpio, int raise) { + /* table mapping the different intel ICH LPC chipsets. */ + static struct { + uint16_t id; + uint8_t base_reg; + uint32_t bank0; + uint32_t bank1; + uint32_t bank2; + } intel_ich_gpio_table[] = { + {0x2410, 0x58, 0x0FE30000, 0, 0}, /* 82801AA (ICH) */ + {0x2420, 0x58, 0x0FE30000, 0, 0}, /* 82801AB (ICH0) */ + {0x2440, 0x58, 0x1BFF391B, 0, 0}, /* 82801BA (ICH2) */ + {0x244C, 0x58, 0x1A23399B, 0, 0}, /* 82801BAM (ICH2M) */ + {0x2450, 0x58, 0x1BFF0000, 0, 0}, /* 82801E (C-ICH) */ + {0x2480, 0x58, 0x1BFF0000, 0x00000FFF, 0}, /* 82801CA (ICH3-S) */ + {0x248C, 0x58, 0x1A230000, 0x00000FFF, 0}, /* 82801CAM (ICH3-M) */ + {0x24C0, 0x58, 0x1BFF0000, 0x00000FFF, 0}, /* 82801DB/DBL (ICH4/ICH4-L) */ + {0x24CC, 0x58, 0x1A030000, 0x00000FFF, 0}, /* 82801DBM (ICH4-M) */ + {0x24D0, 0x58, 0x1BFF0000, 0x00030305, 0}, /* 82801EB/ER (ICH5/ICH5R) */ + {0x2640, 0x48, 0x1BFF0000, 0x00030307, 0}, /* 82801FB/FR (ICH6/ICH6R) */ + {0x2641, 0x48, 0x1BFF0000, 0x00030307, 0}, /* 82801FBM (ICH6M) */ + {0x27B8, 0x48, 0xFFFFFFFF, 0x000300FF, 0}, /* 82801GB/GR (ICH7 Family) */ + {0x27B9, 0x48, 0xFFEBFFFE, 0x000300FE, 0}, /* 82801GBM (ICH7-M) */ + {0x27BD, 0x48, 0xFFEBFFFE, 0x000300FE, 0}, /* 82801GHM (ICH7-M DH) */ + {0x2810, 0x48, 0xFFFFFFFF, 0x00FF0FFF, 0}, /* 82801HB/HR (ICH8/R) */ + {0x2811, 0x48, 0xFFFFFFFF, 0x00FF0FFF, 0}, /* 82801HBM (ICH8M-E) */ + {0x2812, 0x48, 0xFFFFFFFF, 0x00FF0FFF, 0}, /* 82801HH (ICH8DH) */ + {0x2814, 0x48, 0xFFFFFFFF, 0x00FF0FFF, 0}, /* 82801HO (ICH8DO) */ + {0x2815, 0x48, 0xFFFFFFFF, 0x00FF0FFF, 0}, /* 82801HEM (ICH8M) */ + {0x2912, 0x48, 0xFFFFFFFF, 0x00FFFFFF, 0}, /* 82801IH (ICH9DH) */ + {0x2914, 0x48, 0xFFFFFFFF, 0x00FFFFFF, 0}, /* 82801IO (ICH9DO) */ + {0x2916, 0x48, 0xFFFFFFFF, 0x00FFFFFF, 0}, /* 82801IR (ICH9R) */ + {0x2917, 0x48, 0xFFFFFFFF, 0x00FFFFFF, 0}, /* 82801IEM (ICH9M-E) */ + {0x2918, 0x48, 0xFFFFFFFF, 0x00FFFFFF, 0}, /* 82801IB (ICH9) */ + {0x2919, 0x48, 0xFFFFFFFF, 0x00FFFFFF, 0}, /* 82801IBM (ICH9M) */ + {0x3A14, 0x48, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000100}, /* 82801JDO (ICH10DO) */ + {0x3A16, 0x48, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000100}, /* 82801JIR (ICH10R) */ + {0x3A18, 0x48, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000100}, /* 82801JIB (ICH10) */ + {0x3A1A, 0x48, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000100}, /* 82801JD (ICH10D) */ + {0, 0, 0, 0, 0} /* end marker */ + }; + struct pci_dev *dev; - uint16_t gpiobar; - uint32_t reg32; + uint16_t base; + uint32_t tmp; + int i, allowed; - dev = pci_dev_find(ich_vendor, ich_device); /* Intel ICHx LPC */ + /* First, look for a known LPC bridge */ + for (dev = pacc->devices; dev; dev = dev->next) + if ((dev->vendor_id == 0x8086) && + (dev->device_class == 0x0601)) { /* ISA Bridge */ + /* Is this device in our list? */ + for (i = 0; intel_ich_gpio_table[i].id; i++) + if (dev->device_id == intel_ich_gpio_table[i].id) + break; + + if (intel_ich_gpio_table[i].id) + break; + } + if (!dev) { - fprintf(stderr, "\nERROR: ICHx LPC dev %4x:%4x not found.\n", - ich_vendor, ich_device); + fprintf(stderr, "\nERROR: No Known Intel LPC Bridge found.\n"); return -1; } - /* Use GPIOBASE register to find the I/O space for GPIO. */ - gpiobar = pci_read_word(dev, gpiobase_reg) & gp_lvl_bitmask; + /* According to the datasheets, all intel ICHs have the gpio bar 5:1 + strapped to zero. From some mobile ich9 version on, this becomes + 6:1. The mask below catches all. */ + base = pci_read_word(dev, intel_ich_gpio_table[i].base_reg) & 0xFFC0; - /* Set specified GPIO to high. */ - reg32 = INL(gpiobar + gp_lvl); - reg32 |= (1 << gpio_bit); - OUTL(reg32, gpiobar + gp_lvl); + /* check whether the line is allowed */ + if (gpio < 32) + allowed = (intel_ich_gpio_table[i].bank0 >> gpio) & 0x01; + else if (gpio < 64) + allowed = (intel_ich_gpio_table[i].bank1 >> (gpio - 32)) & 0x01; + else + allowed = (intel_ich_gpio_table[i].bank2 >> (gpio - 64)) & 0x01; + if (!allowed) { + fprintf(stderr, "\nERROR: This Intel LPC Bridge does not allow" + " setting GPIO%02d\n", gpio); + return -1; + } + + printf("\nIntel ICH LPC Bridge: %sing GPIO%02d.\n", + raise ? "Rais" : "Dropp", gpio); + + if (gpio < 32) { + /* Set line to GPIO */ + tmp = INL(base); + /* ICH/ICH0 multiplexes 27/28 on the line set. */ + if ((gpio == 28) && + ((dev->device_id == 0x2410) || (dev->device_id == 0x2420))) + tmp |= 1 << 27; + else + tmp |= 1 << gpio; + OUTL(tmp, base); + + /* As soon as we are talking to ICH8 and above, this register + decides whether we can set the gpio or not. */ + if (dev->device_id > 0x2800) { + tmp = INL(base); + if (!(tmp & (1 << gpio))) { + fprintf(stderr, "\nERROR: This Intel LPC Bridge" + " does not allow setting GPIO%02d\n", + gpio); + return -1; + } + } + + /* Set GPIO to OUTPUT */ + tmp = INL(base + 0x04); + tmp &= ~(1 << gpio); + OUTL(tmp, base + 0x04); + + /* Raise GPIO line */ + tmp = INL(base + 0x0C); + if (raise) + tmp |= 1 << gpio; + else + tmp &= ~(1 << gpio); + OUTL(tmp, base + 0x0C); + } else if (gpio < 64) { + gpio -= 32; + + /* Set line to GPIO */ + tmp = INL(base + 0x30); + tmp |= 1 << gpio; + OUTL(tmp, base + 0x30); + + /* As soon as we are talking to ICH8 and above, this register + decides whether we can set the gpio or not. */ + if (dev->device_id > 0x2800) { + tmp = INL(base + 30); + if (!(tmp & (1 << gpio))) { + fprintf(stderr, "\nERROR: This Intel LPC Bridge" + " does not allow setting GPIO%02d\n", + gpio + 32); + return -1; + } + } + + /* Set GPIO to OUTPUT */ + tmp = INL(base + 0x34); + tmp &= ~(1 << gpio); + OUTL(tmp, base + 0x34); + + /* Raise GPIO line */ + tmp = INL(base + 0x38); + if (raise) + tmp |= 1 << gpio; + else + tmp &= ~(1 << gpio); + OUTL(tmp, base + 0x38); + } else { + gpio -= 64; + + /* Set line to GPIO */ + tmp = INL(base + 0x40); + tmp |= 1 << gpio; + OUTL(tmp, base + 0x40); + + tmp = INL(base + 40); + if (!(tmp & (1 << gpio))) { + fprintf(stderr, "\nERROR: This Intel LPC Bridge does " + "not allow setting GPIO%02d\n", gpio + 64); + return -1; + } + + /* Set GPIO to OUTPUT */ + tmp = INL(base + 0x44); + tmp &= ~(1 << gpio); + OUTL(tmp, base + 0x44); + + /* Raise GPIO line */ + tmp = INL(base + 0x48); + if (raise) + tmp |= 1 << gpio; + else + tmp &= ~(1 << gpio); + OUTL(tmp, base + 0x48); + } + return 0; } /** - * Suited for ASUS P4B266. + * Suited for Abit IP35: Intel P35 + ICH9R. */ -static int ich2_gpio22_raise(const char *name) +static int intel_ich_gpio16_raise(const char *name) { - return ich_gpio_raise(name, 0x8086, 0x2440, 0x58, 0x0c, 0xffc0, 22); + return intel_ich_gpio_set(16, 1); } /** - * Suited for the Dell PowerEdge 1850. All parameters except the last one are - * documented in the public Intel 82801EB ICH5 / 82801ER ICH5R datasheet. The - * last parameter (GPIO number) has to be in the range [16,31] according to - * said Intel datasheet and was found by exhaustive search. + * Suited for MSI MS-7046: LGA775 + 915P + ICH6. */ -static int ich5_gpio23_raise(const char *name) +static int intel_ich_gpio19_raise(const char *name) { - return ich_gpio_raise(name, 0x8086, 0x24d0, 0x58, 0x0c, 0xffc0, 23); + return intel_ich_gpio_set(19, 1); } /** - * Suited for MSI MS-7046. + * Suited for Asus P4P800-E Deluxe: Intel socket478 + 865PE + ICH5R. */ -static int ich6_gpio19_raise(const char *name) +static int intel_ich_gpio21_raise(const char *name) { - return ich_gpio_raise(name, 0x8086, 0x2640, 0x48, 0x0c, 0xffc0, 19); + return intel_ich_gpio_set(21, 1); } -static int board_kontron_986lcd_m(const char *name) +/** + * Suited for ASUS P4B266: socket478 + intel 845D + ICH2. + */ +static int intel_ich_gpio22_raise(const char *name) { - struct pci_dev *dev; - uint16_t gpiobar; - uint32_t val; + return intel_ich_gpio_set(22, 1); +} -#define ICH7_GPIO_LVL2 0x38 +/** + * Suited for Dell Poweredge 1850: Intel PPGA604 + E7520 + ICH5R. + */ +static int intel_ich_gpio23_raise(const char *name) +{ + return intel_ich_gpio_set(23, 1); +} - dev = pci_dev_find(0x8086, 0x27b8); /* Intel ICH7 LPC */ - if (!dev) { - // This will never happen on this board - fprintf(stderr, "\nERROR: ICH7 LPC bridge not found.\n"); - return -1; - } +/** + * Suited for Acorp 6A815EPD: socket 370 + intel 815 + ICH2. + */ +static int board_acorp_6a815epd(const char *name) +{ + int ret; - /* Use GPIOBASE register to find where the GPIO is mapped. */ - gpiobar = pci_read_word(dev, 0x48) & 0xfffc; + /* Lower Blocks Lock -- pin 7 of PLCC32 */ + ret = intel_ich_gpio_set(22, 1); + if (!ret) /* Top Block Lock -- pin 8 of PLCC32 */ + ret = intel_ich_gpio_set(23, 1); - val = INL(gpiobar + ICH7_GPIO_LVL2); /* GP_LVL2 */ - printf_debug("\nGPIOBAR=0x%04x GP_LVL: 0x%08x\n", gpiobar, val); + return ret; +} - /* bit 2 (0x04) = 0 #TBL --> bootblock locking = 1 - * bit 2 (0x04) = 1 #TBL --> bootblock locking = 0 - * bit 3 (0x08) = 0 #WP --> block locking = 1 - * bit 3 (0x08) = 1 #WP --> block locking = 0 - * - * To enable full block locking, you would do: - * val &= ~ ((1 << 2) | (1 << 3)); - */ - val |= (1 << 2) | (1 << 3); +/** + * Suited for Kontron 986LCD-M: socket478 + 915GM + ICH7R. + */ +static int board_kontron_986lcd_m(const char *name) +{ + int ret; - OUTL(val, gpiobar + ICH7_GPIO_LVL2); + ret = intel_ich_gpio_set(34, 1); /* #TBL */ + if (!ret) + ret = intel_ich_gpio_set(35, 1); /* #WP */ - return 0; + return ret; } /** @@ -881,32 +1012,6 @@ } /** - * Suited for Abit IP35: Intel P35 + ICH9R. - */ -static int board_abit_ip35(const char *name) -{ - struct pci_dev *dev; - uint16_t base; - uint8_t tmp; - - dev = pci_dev_find(0x8086, 0x2916); /* Intel ICH9R LPC Interface */ - if (!dev) { - fprintf(stderr, "\nERROR: Intel ICH9R LPC not found.\n"); - return -1; - } - - /* get LPC GPIO base */ - base = pci_read_long(dev, 0x48) & 0x0000FFC0; - - /* Raise GPIO 16 */ - tmp = INB(base + 0x0E); - tmp |= 0x01; - OUTB(tmp, base + 0x0E); - - return 0; -} - -/** * Suited for Asus A7V8X: VIA KT400 + VT8235 + IT8703F-A */ static int board_asus_a7v8x(const char *name) @@ -1009,32 +1114,6 @@ } /** - * Suited for Asus P4P800-E Deluxe: Intel Intel 865PE + ICH5R. - */ -static int board_asus_p4p800(const char *name) -{ - struct pci_dev *dev; - uint16_t base; - uint8_t tmp; - - dev = pci_dev_find(0x8086, 0x24D0); /* Intel ICH5R ISA Bridge */ - if (!dev) { - fprintf(stderr, "\nERROR: Intel ICH5R ISA Bridge not found.\n"); - return -1; - } - - /* get PM IO base */ - base = pci_read_long(dev, 0x58) & 0x0000FFC0; - - /* Raise GPIO 21 */ - tmp = INB(base + 0x0E); - tmp |= 0x20; - OUTB(tmp, base + 0x0E); - - return 0; -} - -/** * Below is the list of boards which need a special "board enable" code in * flashrom before their ROM chip can be accessed/written to. * @@ -1063,7 +1142,7 @@ /* Please keep this list alphabetically ordered by vendor/board name. */ struct board_pciid_enable board_pciid_enables[] = { /* first pci-id set [4], second pci-id set [4], coreboot id [2], vendor name board name flash enable */ - {0x8086, 0x2926, 0x147b, 0x1084, 0x11ab, 0x4364, 0x147b, 0x1084, NULL, NULL, "Abit", "IP35", board_abit_ip35}, + {0x8086, 0x2926, 0x147b, 0x1084, 0x11ab, 0x4364, 0x147b, 0x1084, NULL, NULL, "Abit", "IP35", intel_ich_gpio16_raise}, {0x8086, 0x1130, 0, 0, 0x105a, 0x0d30, 0x105a, 0x4d33, "acorp", "6a815epd", "Acorp", "6A815EPD", board_acorp_6a815epd}, {0x1022, 0x746B, 0x1022, 0x36C0, 0, 0, 0, 0, "AGAMI", "ARUMA", "agami", "Aruma", w83627hf_gpio24_raise_2e}, {0x1106, 0x3177, 0x17F2, 0x3177, 0x1106, 0x3148, 0x17F2, 0x3148, NULL, NULL, "Albatron", "PM266A*", board_epox_ep_8k5a2}, @@ -1073,12 +1152,12 @@ {0x1106, 0x3189, 0x1043, 0x807F, 0x1106, 0x3065, 0x1043, 0x80ED, NULL, NULL, "ASUS", "A7V600-X", board_asus_a7v600x}, {0x1106, 0x3189, 0x1043, 0x807F, 0x1106, 0x3177, 0x1043, 0x808C, NULL, NULL, "ASUS", "A7V8X", board_asus_a7v8x}, {0x1106, 0x3177, 0x1043, 0x80A1, 0x1106, 0x3205, 0x1043, 0x8118, NULL, NULL, "ASUS", "A7V8X-MX SE", board_asus_a7v8x_mx}, - {0x8086, 0x1a30, 0x1043, 0x8070, 0x8086, 0x244b, 0x1043, 0x8028, NULL, NULL, "ASUS", "P4B266", ich2_gpio22_raise}, - {0x8086, 0x2570, 0x1043, 0x80F2, 0x105A, 0x3373, 0x1043, 0x80F5, NULL, NULL, "ASUS", "P4P800-E Deluxe", board_asus_p4p800}, + {0x8086, 0x1a30, 0x1043, 0x8070, 0x8086, 0x244b, 0x1043, 0x8028, NULL, NULL, "ASUS", "P4B266", intel_ich_gpio22_raise}, + {0x8086, 0x2570, 0x1043, 0x80F2, 0x105A, 0x3373, 0x1043, 0x80F5, NULL, NULL, "ASUS", "P4P800-E Deluxe", intel_ich_gpio21_raise}, {0x10B9, 0x1541, 0, 0, 0x10B9, 0x1533, 0, 0, "asus", "p5a", "ASUS", "P5A", board_asus_p5a}, {0x10DE, 0x0030, 0x1043, 0x818a, 0x8086, 0x100E, 0x1043, 0x80EE, NULL, NULL, "ASUS", "P5ND2-SLI Deluxe", board_asus_p5nd2_sli}, {0x1106, 0x3149, 0x1565, 0x3206, 0x1106, 0x3344, 0x1565, 0x1202, NULL, NULL, "Biostar", "P4M80-M4", it8705_rom_write_enable}, - {0x8086, 0x3590, 0x1028, 0x016c, 0x1000, 0x0030, 0x1028, 0x016c, NULL, NULL, "Dell", "PowerEdge 1850", ich5_gpio23_raise}, + {0x8086, 0x3590, 0x1028, 0x016c, 0x1000, 0x0030, 0x1028, 0x016c, NULL, NULL, "Dell", "PowerEdge 1850", intel_ich_gpio23_raise}, {0x1106, 0x3038, 0x1019, 0x0996, 0x1106, 0x3177, 0x1019, 0x0996, NULL, NULL, "Elitegroup", "K7VTA3", it8705f_write_enable_2e}, {0x1106, 0x3177, 0x1106, 0x3177, 0x1106, 0x3059, 0x1695, 0x3005, NULL, NULL, "EPoX", "EP-8K5A2", board_epox_ep_8k5a2}, {0x10EC, 0x8139, 0x1695, 0x9001, 0x11C1, 0x5811, 0x1695, 0x9015, NULL, NULL, "EPoX", "EP-8RDA3+", board_epox_ep_8rda3plus}, @@ -1103,7 +1182,7 @@ {0x13f6, 0x0111, 0x1462, 0x5900, 0x1106, 0x3177, 0x1106, 0, "msi", "kt4ultra", "MSI", "MS-6590 (KT4 Ultra)",board_msi_kt4v}, {0x1106, 0x3149, 0x1462, 0x7094, 0x10ec, 0x8167, 0x1462, 0x094c, NULL, NULL, "MSI", "MS-6702E (K8T Neo2-F)",w83627thf_gpio4_4_raise_2e}, {0x1106, 0x0571, 0x1462, 0x7120, 0, 0, 0, 0, "msi", "kt4v", "MSI", "MS-6712 (KT4V)", board_msi_kt4v}, - {0x8086, 0x2658, 0x1462, 0x7046, 0x1106, 0x3044, 0x1462, 0x046d, NULL, NULL, "MSI", "MS-7046", ich6_gpio19_raise}, + {0x8086, 0x2658, 0x1462, 0x7046, 0x1106, 0x3044, 0x1462, 0x046d, NULL, NULL, "MSI", "MS-7046", intel_ich_gpio19_raise}, {0x10de, 0x005e, 0, 0, 0, 0, 0, 0, "msi", "k8n-neo3", "MSI", "MS-7135 (K8N Neo3)", w83627thf_gpio4_4_raise_4e}, {0x1106, 0x3104, 0x1297, 0xa238, 0x1106, 0x3059, 0x1297, 0xc063, NULL, NULL, "Shuttle", "AK38N", it8705f_write_enable_2e}, {0x10DE, 0x0050, 0x1297, 0x5036, 0x1412, 0x1724, 0x1297, 0x5036, NULL, NULL, "Shuttle", "FN25", board_shuttle_fn25},

1 0

Re: [flashrom] Flashrom MSI KT4V support.
by Luc Verhaegen 28 Nov '09

28 Nov '09

On Sun, Oct 18, 2009 at 06:33:11PM -0700, Sean Nelson wrote: > the "anomaly" is the code for my board to enable flash writing. That's > the reason why it's has it's own board enable arguments in flashrom. > > Sadly I don't remember what I did with the board since I upgraded the > machine to a NForce4 set. If I find it, i'll try to send you the dumps > you need. > > On Sat, Oct 17, 2009 at 2:58 PM, Luc Verhaegen <libv(a)skynet.be> wrote: > > Hi Sean, > > > > I have some questions about your kt4v/kt4ultra board enable: > > > > 1) I am about to move some code from many vt823x based board > > enables to the chipset enable. Your board enable has some "similar" > > code, but not quite, and it now forms the only anomaly. > > > > Can you send me the output of: > > dd if=/dev/mem of=/tmp/kt4v_system.rom bs=64k count=1 skip=15 > > so i can have a dig through the top segment of your AMI BIOS to verify > > this code? > > > > 2) I am about to tighten up the board enable matching table. > > * both the coreboot ids will disappear. > > * we need a second set for the kt4v. > > Can you send in lspci -vvnnxxx on both boards? > > > > Thanks, > > > > Luc Verhaegen. > > The anomalies are the following: * it touches the register that vt823x based board enables often touch. but instead of clearing the 1 bit, it clears all except two. * it provides coreboot ids while it can match the one board just fine. * it provides no full set of pciids for the second board. Luc Verhaegen.

2 4

No EEPROM found (Sony Vaio VGN-FE21S)
by Stefan Reinauer 27 Nov '09

27 Nov '09

Any ideas? superiotool finds nothing on this machine. It's i945/ICH7 -- coresystems GmbH • Brahmsstr. 16 • D-79104 Freiburg i. Br. Tel.: +49 761 7668825 • Fax: +49 761 7664613 Email: info(a)coresystems.de • http://www.coresystems.de/ Registergericht: Amtsgericht Freiburg • HRB 7656 Geschäftsführer: Stefan Reinauer • Ust-IdNr.: DE245674866

4 12

Migrate towards common JEDEC functions
by Michael Karcher 27 Nov '09

27 Nov '09

Use common jedec functionality where appropriate. The deleted function in en29f002a.c is reintroduced as write_by_byte_jedec in jedec.c as it contains no chip-specific instructions. It is not yet used in other chip drivers, as key addresses (0x2AAA/0x5555) are often specified with less bits. After crosschecking datasheets, most of the fixmes can probably be resolved as indicated in them, causing significant code reduction. Similar analysis should be performed for the read id stuff. Signed-off-by: flashrom(a)mkarcher.dialup.fu-berlin.de Index: flash.h =================================================================== --- flash.h (Revision 784) +++ flash.h (Arbeitskopie) @@ -653,6 +653,7 @@ int probe_jedec(struct flashchip *flash); int erase_chip_jedec(struct flashchip *flash); int write_jedec(struct flashchip *flash, uint8_t *buf); +int write_by_byte_jedec(struct flashchip *flash, uint8_t *buf); int erase_sector_jedec(struct flashchip *flash, unsigned int page, unsigned int pagesize); int erase_block_jedec(struct flashchip *flash, unsigned int page, unsigned int blocksize); int write_sector_jedec(chipaddr bios, uint8_t *src, Index: en29f002a.c =================================================================== --- en29f002a.c (Revision 784) +++ en29f002a.c (Arbeitskopie) @@ -87,39 +87,3 @@ return 0; } - -/* The EN29F002 chip needs repeated single byte writing, no block writing. */ -int write_en29f002a(struct flashchip *flash, uint8_t *buf) -{ - int i; - int total_size = flash->total_size * 1024; - chipaddr bios = flash->virtual_memory; - chipaddr dst = bios; - - //chip_writeb(0xF0, bios); - programmer_delay(10); - if (erase_chip_jedec(flash)) { - fprintf(stderr, "ERASE FAILED!\n"); - return -1; - } - - printf("Programming page: "); - for (i = 0; i < total_size; i++) { - /* write to the sector */ - if ((i & 0xfff) == 0) - printf("address: 0x%08lx", (unsigned long)i); - chip_writeb(0xAA, bios + 0x5555); - chip_writeb(0x55, bios + 0x2AAA); - chip_writeb(0xA0, bios + 0x5555); - chip_writeb(*buf++, dst++); - - /* wait for Toggle bit ready */ - toggle_ready_jedec(dst); - - if ((i & 0xfff) == 0) - printf("\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b"); - } - - printf("\n"); - return 0; -} Index: jedec.c =================================================================== --- jedec.c (Revision 784) +++ jedec.c (Arbeitskopie) @@ -353,3 +353,31 @@ return failed; } + +int write_by_byte_jedec(struct flashchip *flash, uint8_t * buf) +{ + int i; + int total_size = flash->total_size * 1024; + chipaddr bios = flash->virtual_memory; + chipaddr dst = bios; + + programmer_delay(10); + if (erase_chip_jedec(flash)) { + fprintf(stderr, "ERASE FAILED!\n"); + return -1; + } + + printf("Programming page: "); + for (i = 0; i < flash->total_size; i++) { + if ((i & 0x3) == 0) + printf("address: 0x%08lx", (unsigned long)i * 1024); + + write_sector_jedec(bios, buf + i * 1024, dst + i * 1024) + + if ((i & 0x3) == 0) + printf("\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b"); + } + + printf("\n"); + return 0; +} Index: pm29f002.c =================================================================== --- pm29f002.c (Revision 784) +++ pm29f002.c (Arbeitskopie) @@ -20,18 +20,22 @@ #include "flash.h" +/* if erase_chip_jedec/write_sector_jedec is used, + this is write_by_byte_jedec */ int write_pm29f002(struct flashchip *flash, uint8_t *buf) { int i, total_size = flash->total_size * 1024; chipaddr bios = flash->virtual_memory; chipaddr dst = bios; - /* Pm29F002T/B use the same erase method... */ + /* Pm29F002T/B use the same erase method... + FIXME: use erase_chip_jedec? */ if (erase_29f040b(flash)) { fprintf(stderr, "ERASE FAILED!\n"); return -1; } + /* FIXME: use write_sector_jedec? */ printf("Programming page: "); for (i = 0; i < total_size; i++) { if ((i & 0xfff) == 0) Index: flashchips.c =================================================================== --- flashchips.c (Revision 784) +++ flashchips.c (Arbeitskopie) @@ -81,7 +81,7 @@ .probe = probe_jedec, .probe_timing = TIMING_ZERO, .erase = erase_chip_jedec, - .write = write_en29f002a, + .write = write_by_byte_jedec, .read = read_memmapped, }, @@ -97,7 +97,7 @@ .probe = probe_jedec, .probe_timing = TIMING_ZERO, .erase = erase_chip_jedec, - .write = write_en29f002a, + .write = write_by_byte_jedec, .read = read_memmapped, }, @@ -1075,7 +1075,7 @@ .probe = probe_jedec, .probe_timing = TIMING_ZERO, /* Datasheet has no timing info specified */ .erase = erase_chip_jedec, - .write = write_en29f002a, + .write = write_by_byte_jedec, .read = read_memmapped, }, @@ -1091,7 +1091,7 @@ .probe = probe_jedec, .probe_timing = TIMING_ZERO, /* Datasheet has no timing info specified */ .erase = erase_chip_jedec, - .write = write_en29f002a, + .write = write_by_byte_jedec, .read = read_memmapped, }, Index: m29f002.c =================================================================== --- m29f002.c (Revision 784) +++ m29f002.c (Arbeitskopie) @@ -45,6 +45,7 @@ chipaddr dst = bios + start; /* erase */ + /* FIXME: use erase_sector_jedec? */ chip_writeb(0xaa, bios + 0x555); chip_writeb(0x55, bios + 0xaaa); chip_writeb(0x80, bios + 0x555); @@ -59,6 +60,7 @@ } /* program */ + /* FIXME: use write_sector_jedec? */ while (size--) { chip_writeb(0xaa, bios + 0x555); chip_writeb(0x55, bios + 0xaaa); Index: am29f040b.c =================================================================== --- am29f040b.c (Revision 784) +++ am29f040b.c (Arbeitskopie) @@ -20,6 +20,8 @@ #include "flash.h" +/* FIMXE: check that the 2 second delay is really needed. + Use erase_sector_jedec if not? */ static int erase_sector_29f040b(struct flashchip *flash, unsigned long address) { int page_size = flash->page_size; @@ -44,6 +46,7 @@ return 0; } +/* FIXME: use write_sector_jedec? */ static int write_sector_29f040b(chipaddr bios, uint8_t *src, chipaddr dst, unsigned int page_size) { @@ -91,6 +94,7 @@ return 0; } +/* FIXME: use erase_chip_jedec */ int erase_29f040b(struct flashchip *flash) { int total_size = flash->total_size * 1024; Index: mx29f002.c =================================================================== --- mx29f002.c (Revision 784) +++ mx29f002.c (Arbeitskopie) @@ -43,6 +43,8 @@ return 0; } +/* FIXME: Use erase_chip_jedec? + * (does not send 0xF0 (exit ID mode) and uses 0x5555/0x2AAA adresses) */ int erase_29f002(struct flashchip *flash) { chipaddr bios = flash->virtual_memory; @@ -65,6 +67,8 @@ return 0; } +/* FIXME: If erase_29f002 has been replaced by erase_chip_jedec, this + function is write_by_byte_jedec */ int write_29f002(struct flashchip *flash, uint8_t *buf) { int i; @@ -83,14 +87,8 @@ /* write to the sector */ if ((i & 0xfff) == 0) printf("address: 0x%08lx", (unsigned long)i); - chip_writeb(0xAA, bios + 0x5555); - chip_writeb(0x55, bios + 0x2AAA); - chip_writeb(0xA0, bios + 0x5555); - chip_writeb(*buf++, dst++); + write_byte_program_jedec(bios, buf++, dst++); - /* wait for Toggle bit ready */ - toggle_ready_jedec(dst); - if ((i & 0xfff) == 0) printf("\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b"); } Index: m29f400bt.c =================================================================== --- m29f400bt.c (Revision 784) +++ m29f400bt.c (Arbeitskopie) @@ -20,6 +20,7 @@ #include "flash.h" +/* FIXME: use write_sector_jedec? */ void write_page_m29f400bt(chipaddr bios, uint8_t *src, chipaddr dst, int page_size) { @@ -74,6 +75,7 @@ return 0; } +/* FIXME: Use erase_chip_jedec? */ int erase_m29f400bt(struct flashchip *flash) { chipaddr bios = flash->virtual_memory; @@ -96,6 +98,7 @@ return 0; } +/* FIXME: Use erase_sector_jedec? */ int block_erase_m29f400bt(struct flashchip *flash, int start, int len) { chipaddr bios = flash->virtual_memory;

4 6

[commit] r785 - trunk
by svn＠flashrom.org 27 Nov '09

27 Nov '09

Author: hailfinger Date: 2009-11-27 18:49:42 +0100 (Fri, 27 Nov 2009) New Revision: 785 Modified: trunk/am29f040b.c trunk/en29f002a.c trunk/flash.h trunk/flashchips.c trunk/jedec.c trunk/m29f002.c trunk/m29f400bt.c trunk/mx29f002.c trunk/pm29f002.c Log: Use common jedec functionality where appropriate. The deleted function in en29f002a.c is reintroduced as write_by_byte_jedec in jedec.c as it contains no chip-specific instructions. It is not yet used in other chip drivers, as key addresses (0x2AAA/0x5555) are often specified with less bits. After crosschecking datasheets, most of the fixmes can probably be resolved as indicated in them, causing significant code reduction. The common JEDEC code for bytewise programming does not program 0xFF at all. The chips that had a dedicated bytewise flash function which has been changed to write_jedec_1 thus changed flashing behaviour and the "write" test flag has been removed. This applies to: AMD Am29F002BB/Am29F002NBB AMD Am29F002BT/Am29F002NBT (TEST_OK_PREW before) AMIC A29002B AMIC A29002T (TEST_OK_PREW before) EON EN29F002(A)(N)B EON EN29F002(A)(N)T (TEST_OK_PREW before) Macronix MX29F001B (TEST_OK_PREW before) Macronix MX29F001T (TEST_OK_PREW before) Macronix MX29F002B Macronix MX29F002T (TEST_OK_PREW before) Macronix MX29LV040 Similar analysis should be performed for the read id stuff. Signed-off-by: Michael Karcher <flashrom(a)mkarcher.dialup.fu-berlin.de> Acked-by: Sean Nelson <audiohacked(a)gmail.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: trunk/am29f040b.c =================================================================== --- trunk/am29f040b.c 2009-11-26 16:51:39 UTC (rev 784) +++ trunk/am29f040b.c 2009-11-27 17:49:42 UTC (rev 785) @@ -20,6 +20,8 @@ #include "flash.h" +/* FIMXE: check that the 2 second delay is really needed. + Use erase_sector_jedec if not? */ static int erase_sector_29f040b(struct flashchip *flash, unsigned long address) { int page_size = flash->page_size; @@ -44,6 +46,7 @@ return 0; } +/* FIXME: use write_sector_jedec? */ static int write_sector_29f040b(chipaddr bios, uint8_t *src, chipaddr dst, unsigned int page_size) { @@ -91,6 +94,7 @@ return 0; } +/* FIXME: use erase_chip_jedec? */ int erase_29f040b(struct flashchip *flash) { int total_size = flash->total_size * 1024; Modified: trunk/en29f002a.c =================================================================== --- trunk/en29f002a.c 2009-11-26 16:51:39 UTC (rev 784) +++ trunk/en29f002a.c 2009-11-27 17:49:42 UTC (rev 785) @@ -87,39 +87,3 @@ return 0; } - -/* The EN29F002 chip needs repeated single byte writing, no block writing. */ -int write_en29f002a(struct flashchip *flash, uint8_t *buf) -{ - int i; - int total_size = flash->total_size * 1024; - chipaddr bios = flash->virtual_memory; - chipaddr dst = bios; - - //chip_writeb(0xF0, bios); - programmer_delay(10); - if (erase_chip_jedec(flash)) { - fprintf(stderr, "ERASE FAILED!\n"); - return -1; - } - - printf("Programming page: "); - for (i = 0; i < total_size; i++) { - /* write to the sector */ - if ((i & 0xfff) == 0) - printf("address: 0x%08lx", (unsigned long)i); - chip_writeb(0xAA, bios + 0x5555); - chip_writeb(0x55, bios + 0x2AAA); - chip_writeb(0xA0, bios + 0x5555); - chip_writeb(*buf++, dst++); - - /* wait for Toggle bit ready */ - toggle_ready_jedec(dst); - - if ((i & 0xfff) == 0) - printf("\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b"); - } - - printf("\n"); - return 0; -} Modified: trunk/flash.h =================================================================== --- trunk/flash.h 2009-11-26 16:51:39 UTC (rev 784) +++ trunk/flash.h 2009-11-27 17:49:42 UTC (rev 785) @@ -653,6 +653,7 @@ int probe_jedec(struct flashchip *flash); int erase_chip_jedec(struct flashchip *flash); int write_jedec(struct flashchip *flash, uint8_t *buf); +int write_jedec_1(struct flashchip *flash, uint8_t *buf); int erase_sector_jedec(struct flashchip *flash, unsigned int page, unsigned int pagesize); int erase_block_jedec(struct flashchip *flash, unsigned int page, unsigned int blocksize); int write_sector_jedec(chipaddr bios, uint8_t *src, Modified: trunk/flashchips.c =================================================================== --- trunk/flashchips.c 2009-11-26 16:51:39 UTC (rev 784) +++ trunk/flashchips.c 2009-11-27 17:49:42 UTC (rev 785) @@ -81,7 +81,7 @@ .probe = probe_jedec, .probe_timing = TIMING_ZERO, .erase = erase_chip_jedec, - .write = write_en29f002a, + .write = write_jedec_1, .read = read_memmapped, }, @@ -93,11 +93,11 @@ .model_id = AM_29F002BT, .total_size = 256, .page_size = 256, - .tested = TEST_OK_PREW, + .tested = TEST_OK_PRE, .probe = probe_jedec, .probe_timing = TIMING_ZERO, .erase = erase_chip_jedec, - .write = write_en29f002a, + .write = write_jedec_1, .read = read_memmapped, }, @@ -739,7 +739,7 @@ .probe = probe_29f002, .probe_timing = TIMING_IGNORED, /* routine don't use probe_timing (mx29f002.c) */ .erase = erase_29f002, - .write = write_29f002, + .write = write_jedec_1, .read = read_memmapped, }, @@ -751,11 +751,11 @@ .model_id = AMIC_A29002T, .total_size = 256, .page_size = 64 * 1024, - .tested = TEST_OK_PREW, + .tested = TEST_OK_PRE, .probe = probe_29f002, .probe_timing = TIMING_IGNORED, /* routine don't use probe_timing (mx29f002.c) */ .erase = erase_29f002, - .write = write_29f002, + .write = write_jedec_1, .read = read_memmapped, }, @@ -1075,7 +1075,7 @@ .probe = probe_jedec, .probe_timing = TIMING_ZERO, /* Datasheet has no timing info specified */ .erase = erase_chip_jedec, - .write = write_en29f002a, + .write = write_jedec_1, .read = read_memmapped, }, @@ -1087,11 +1087,11 @@ .model_id = EN_29F002T, .total_size = 256, .page_size = 256, - .tested = TEST_OK_PREW, + .tested = TEST_OK_PRE, .probe = probe_jedec, .probe_timing = TIMING_ZERO, /* Datasheet has no timing info specified */ .erase = erase_chip_jedec, - .write = write_en29f002a, + .write = write_jedec_1, .read = read_memmapped, }, @@ -1518,11 +1518,11 @@ .model_id = MX_29F001B, .total_size = 128, .page_size = 32 * 1024, - .tested = TEST_OK_PREW, + .tested = TEST_OK_PRE, .probe = probe_29f002, .probe_timing = TIMING_IGNORED, /* routine don't use probe_timing (mx29f002.c) */ .erase = erase_29f002, - .write = write_29f002, + .write = write_jedec_1, .read = read_memmapped, }, @@ -1534,11 +1534,11 @@ .model_id = MX_29F001T, .total_size = 128, .page_size = 32 * 1024, - .tested = TEST_OK_PREW, + .tested = TEST_OK_PRE, .probe = probe_29f002, .probe_timing = TIMING_IGNORED, /* routine don't use probe_timing (mx29f002.c) */ .erase = erase_29f002, - .write = write_29f002, + .write = write_jedec_1, .read = read_memmapped, }, @@ -1554,7 +1554,7 @@ .probe = probe_29f002, .probe_timing = TIMING_IGNORED, /* routine don't use probe_timing (mx29f002.c) */ .erase = erase_29f002, - .write = write_29f002, + .write = write_jedec_1, .read = read_memmapped, }, @@ -1566,11 +1566,11 @@ .model_id = MX_29F002T, .total_size = 256, .page_size = 64 * 1024, - .tested = TEST_OK_PREW, + .tested = TEST_OK_PRE, .probe = probe_29f002, .probe_timing = TIMING_IGNORED, /* routine don't use probe_timing (mx29f002.c) */ .erase = erase_29f002, - .write = write_29f002, + .write = write_jedec_1, .read = read_memmapped, }, @@ -1586,7 +1586,7 @@ .probe = probe_29f002, .probe_timing = TIMING_IGNORED, /* routine don't use probe_timing (mx29f002.c) */ .erase = erase_29f002, - .write = write_29f002, + .write = write_jedec_1, .read = read_memmapped, }, Modified: trunk/jedec.c =================================================================== --- trunk/jedec.c 2009-11-26 16:51:39 UTC (rev 784) +++ trunk/jedec.c 2009-11-27 17:49:42 UTC (rev 785) @@ -353,3 +353,30 @@ return failed; } + +int write_jedec_1(struct flashchip *flash, uint8_t * buf) +{ + int i; + chipaddr bios = flash->virtual_memory; + chipaddr dst = bios; + + programmer_delay(10); + if (erase_flash(flash)) { + fprintf(stderr, "ERASE FAILED!\n"); + return -1; + } + + printf("Programming page: "); + for (i = 0; i < flash->total_size; i++) { + if ((i & 0x3) == 0) + printf("address: 0x%08lx", (unsigned long)i * 1024); + + write_sector_jedec(bios, buf + i * 1024, dst + i * 1024, 1024); + + if ((i & 0x3) == 0) + printf("\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b"); + } + + printf("\n"); + return 0; +} Modified: trunk/m29f002.c =================================================================== --- trunk/m29f002.c 2009-11-26 16:51:39 UTC (rev 784) +++ trunk/m29f002.c 2009-11-27 17:49:42 UTC (rev 785) @@ -45,6 +45,7 @@ chipaddr dst = bios + start; /* erase */ + /* FIXME: use erase_sector_jedec? */ chip_writeb(0xaa, bios + 0x555); chip_writeb(0x55, bios + 0xaaa); chip_writeb(0x80, bios + 0x555); @@ -59,6 +60,7 @@ } /* program */ + /* FIXME: use write_sector_jedec? */ while (size--) { chip_writeb(0xaa, bios + 0x555); chip_writeb(0x55, bios + 0xaaa); Modified: trunk/m29f400bt.c =================================================================== --- trunk/m29f400bt.c 2009-11-26 16:51:39 UTC (rev 784) +++ trunk/m29f400bt.c 2009-11-27 17:49:42 UTC (rev 785) @@ -20,6 +20,12 @@ #include "flash.h" +/* WARNING! + This chip uses the standard JEDEC Addresses in 16-bit mode as word + addresses. In byte mode, 0xAAA has to be used instead of 0x555 and + 0x555 instead of 0x2AA. Do *not* blindly replace with standard JEDEC + functions. */ + void write_page_m29f400bt(chipaddr bios, uint8_t *src, chipaddr dst, int page_size) { Modified: trunk/mx29f002.c =================================================================== --- trunk/mx29f002.c 2009-11-26 16:51:39 UTC (rev 784) +++ trunk/mx29f002.c 2009-11-27 17:49:42 UTC (rev 785) @@ -43,6 +43,9 @@ return 0; } +/* FIXME: Use erase_chip_jedec? + * erase_29f002 uses shorter addresses, sends F0 (exit ID mode) and + * and has a bigger delay before polling the toggle bit */ int erase_29f002(struct flashchip *flash) { chipaddr bios = flash->virtual_memory; @@ -64,37 +67,3 @@ } return 0; } - -int write_29f002(struct flashchip *flash, uint8_t *buf) -{ - int i; - int total_size = flash->total_size * 1024; - chipaddr bios = flash->virtual_memory; - chipaddr dst = bios; - - chip_writeb(0xF0, bios); - programmer_delay(10); - if (erase_29f002(flash)) { - fprintf(stderr, "ERASE FAILED!\n"); - return -1; - } - printf("Programming page: "); - for (i = 0; i < total_size; i++) { - /* write to the sector */ - if ((i & 0xfff) == 0) - printf("address: 0x%08lx", (unsigned long)i); - chip_writeb(0xAA, bios + 0x5555); - chip_writeb(0x55, bios + 0x2AAA); - chip_writeb(0xA0, bios + 0x5555); - chip_writeb(*buf++, dst++); - - /* wait for Toggle bit ready */ - toggle_ready_jedec(dst); - - if ((i & 0xfff) == 0) - printf("\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b"); - } - printf("\n"); - - return 0; -} Modified: trunk/pm29f002.c =================================================================== --- trunk/pm29f002.c 2009-11-26 16:51:39 UTC (rev 784) +++ trunk/pm29f002.c 2009-11-27 17:49:42 UTC (rev 785) @@ -20,18 +20,20 @@ #include "flash.h" +/* if write_sector_jedec is used, + this is write_jedec_1 */ int write_pm29f002(struct flashchip *flash, uint8_t *buf) { int i, total_size = flash->total_size * 1024; chipaddr bios = flash->virtual_memory; chipaddr dst = bios; - /* Pm29F002T/B use the same erase method... */ - if (erase_29f040b(flash)) { + if (erase_flash(flash)) { fprintf(stderr, "ERASE FAILED!\n"); return -1; } + /* FIXME: use write_sector_jedec? */ printf("Programming page: "); for (i = 0; i < total_size; i++) { if ((i & 0xfff) == 0)

1 0

Re: [flashrom] BIOS Flash Help
by Carl-Daniel Hailfinger 27 Nov '09

27 Nov '09

[Please keep flashrom(a)flashrom.org in CC so others can learn as well. Thanks.] On 27.11.2009 04:29, Cory Cline wrote: > This is indeed a laptop. I did not realize the limitations extended that far. With all my research, I should of known that. Hey, it's not your fault that you own a laptop. > So if it's not too much to ask, how should I go about this flash? And to be clear, I dont want anyone to do it for me. I only wish someone to teach me to fish as the saying goes. > We are happy about everyone who wants to join flashrom development. That said, adding support for your embedded controller (if flash really is connected to it, and it looks like it is) is not an easy project. We usually recommend easy starter projects to get familiar with flashrom. Here is a writeup about how to add support for your laptop. I created it right now, and decided to publish it in the wiki so others can read it as well. http://www.flashrom.org/Supported_hardware#Unsupported_Laptops.2FNotebooks.… Regards, Carl-Daniel -- Developer quote of the month: "We are juggling too many chainsaws and flaming arrows and tigers."

1 0

BIOS Flash Help
by Cory Cline 26 Nov '09

26 Nov '09

I was instructed by idwer at #flashrom to mail these command outputs to you. I just wish to learn how to update my BIOS. Chipset:AMD SB600 BIOS Update: http://global-download.acer.com/GDFiles%5CBIOS/BIOS/BIOS_Acer_1.0_A_A.zip?a… $flashrom -V flashrom v0.9.1-r710 No coreboot table found. Found chipset "AMD SB600", enabling flash write... SPI base address is at 0x0 ROM strap override is not active OK. This chipset supports the following protocols: LPC,FWH. Calibrating delay loop... 196M loops per second, 100 myus = 93 us. OK. Probing for AMD Am29F010A/B, 128 KB: skipped. Host bus type LPC,FWH and chip bus type Parallel are incompatible. Probing for AMD Am29F002(N)BB, 256 KB: skipped. Host bus type LPC,FWH and chip bus type Parallel are incompatible. Probing for AMD Am29F002(N)BT, 256 KB: skipped. Host bus type LPC,FWH and chip bus type Parallel are incompatible. Probing for AMD Am29F016D, 2048 KB: skipped. Host bus type LPC,FWH and chip bus type Parallel are incompatible. Probing for AMD Am29F040B, 512 KB: skipped. Host bus type LPC,FWH and chip bus type Parallel are incompatible. Probing for AMD Am29F080B, 1024 KB: skipped. Host bus type LPC,FWH and chip bus type Parallel are incompatible. Probing for AMD Am29LV040B, 512 KB: skipped. Host bus type LPC,FWH and chip bus type Parallel are incompatible. Probing for AMD Am29LV081B, 1024 KB: skipped. Host bus type LPC,FWH and chip bus type Parallel are incompatible. Probing for ASD AE49F2008, 256 KB: skipped. Host bus type LPC,FWH and chip bus type Parallel are incompatible. Probing for Atmel AT25DF021, 256 KB: skipped. Host bus type LPC,FWH and chip bus type SPI are incompatible. Probing for Atmel AT25DF041A, 512 KB: skipped. Host bus type LPC,FWH and chip bus type SPI are incompatible. Probing for Atmel AT25DF081, 1024 KB: skipped. Host bus type LPC,FWH and chip bus type SPI are incompatible. Probing for Atmel AT25DF161, 2048 KB: skipped. Host bus type LPC,FWH and chip bus type SPI are incompatible. Probing for Atmel AT25DF321, 4096 KB: skipped. Host bus type LPC,FWH and chip bus type SPI are incompatible. Probing for Atmel AT25DF321A, 4096 KB: skipped. Host bus type LPC,FWH and chip bus type SPI are incompatible. Probing for Atmel AT25DF641, 8192 KB: skipped. Host bus type LPC,FWH and chip bus type SPI are incompatible. Probing for Atmel AT25F512B, 64 KB: skipped. Host bus type LPC,FWH and chip bus type SPI are incompatible. Probing for Atmel AT25FS010, 128 KB: skipped. Host bus type LPC,FWH and chip bus type SPI are incompatible. Probing for Atmel AT25FS040, 512 KB: skipped. Host bus type LPC,FWH and chip bus type SPI are incompatible. Probing for Atmel AT26DF041, 512 KB: skipped. Host bus type LPC,FWH and chip bus type SPI are incompatible. Probing for Atmel AT26DF081A, 1024 KB: skipped. Host bus type LPC,FWH and chip bus type SPI are incompatible. Probing for Atmel AT26DF161, 2048 KB: skipped. Host bus type LPC,FWH and chip bus type SPI are incompatible. Probing for Atmel AT26DF161A, 2048 KB: skipped. Host bus type LPC,FWH and chip bus type SPI are incompatible. Probing for Atmel AT26F004, 512 KB: skipped. Host bus type LPC,FWH and chip bus type SPI are incompatible. Probing for Atmel AT29C512, 64 KB: skipped. Host bus type LPC,FWH and chip bus type Parallel are incompatible. Probing for Atmel AT29C010A, 128 KB: skipped. Host bus type LPC,FWH and chip bus type Parallel are incompatible. Probing for Atmel AT29C020, 256 KB: skipped. Host bus type LPC,FWH and chip bus type Parallel are incompatible. Probing for Atmel AT29C040A, 512 KB: skipped. Host bus type LPC,FWH and chip bus type Parallel are incompatible. Probing for Atmel AT45CS1282, 16896 KB: skipped. Host bus type LPC,FWH and chip bus type SPI are incompatible. Probing for Atmel AT45DB011D, 128 KB: skipped. Host bus type LPC,FWH and chip bus type SPI are incompatible. Probing for Atmel AT45DB021D, 256 KB: skipped. Host bus type LPC,FWH and chip bus type SPI are incompatible. Probing for Atmel AT45DB041D, 512 KB: skipped. Host bus type LPC,FWH and chip bus type SPI are incompatible. Probing for Atmel AT45DB081D, 1024 KB: skipped. Host bus type LPC,FWH and chip bus type SPI are incompatible. Probing for Atmel AT45DB161D, 2048 KB: skipped. Host bus type LPC,FWH and chip bus type SPI are incompatible. Probing for Atmel AT45DB321C, 4224 KB: skipped. Host bus type LPC,FWH and chip bus type SPI are incompatible. Probing for Atmel AT45DB321D, 4096 KB: skipped. Host bus type LPC,FWH and chip bus type SPI are incompatible. Probing for Atmel AT45DB642D, 8192 KB: skipped. Host bus type LPC,FWH and chip bus type SPI are incompatible. Probing for Atmel AT49BV512, 64 KB: skipped. Host bus type LPC,FWH and chip bus type Parallel are incompatible. Probing for Atmel AT49F002(N), 256 KB: skipped. Host bus type LPC,FWH and chip bus type Parallel are incompatible. Probing for Atmel AT49F002(N)T, 256 KB: skipped. Host bus type LPC,FWH and chip bus type Parallel are incompatible. Probing for AMIC A25L40P, 512 KB: skipped. Host bus type LPC,FWH and chip bus type SPI are incompatible. Probing for AMIC A29002B, 256 KB: skipped. Host bus type LPC,FWH and chip bus type Parallel are incompatible. Probing for AMIC A29002T, 256 KB: skipped. Host bus type LPC,FWH and chip bus type Parallel are incompatible. Probing for AMIC A29040B, 512 KB: skipped. Host bus type LPC,FWH and chip bus type Parallel are incompatible. Probing for AMIC A49LF040A, 512 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0x81, id2 0x6e, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for EMST F49B002UA, 256 KB: skipped. Host bus type LPC,FWH and chip bus type Parallel are incompatible. Probing for Eon EN25B05, 64 KB: skipped. Host bus type LPC,FWH and chip bus type SPI are incompatible. Probing for Eon EN25B10, 128 KB: skipped. Host bus type LPC,FWH and chip bus type SPI are incompatible. Probing for Eon EN25B20, 256 KB: skipped. Host bus type LPC,FWH and chip bus type SPI are incompatible. Probing for Eon EN25B40, 512 KB: skipped. Host bus type LPC,FWH and chip bus type SPI are incompatible. Probing for Eon EN25B80, 1024 KB: skipped. Host bus type LPC,FWH and chip bus type SPI are incompatible. Probing for Eon EN25B16, 2048 KB: skipped. Host bus type LPC,FWH and chip bus type SPI are incompatible. Probing for Eon EN25B32, 4096 KB: skipped. Host bus type LPC,FWH and chip bus type SPI are incompatible. Probing for Eon EN25B64, 8192 KB: skipped. Host bus type LPC,FWH and chip bus type SPI are incompatible. Probing for Eon EN25D16, 2048 KB: skipped. Host bus type LPC,FWH and chip bus type SPI are incompatible. Probing for Eon EN25F05, 64 KB: skipped. Host bus type LPC,FWH and chip bus type SPI are incompatible. Probing for Eon EN25F10, 128 KB: skipped. Host bus type LPC,FWH and chip bus type SPI are incompatible. Probing for Eon EN25F20, 256 KB: skipped. Host bus type LPC,FWH and chip bus type SPI are incompatible. Probing for Eon EN25F40, 512 KB: skipped. Host bus type LPC,FWH and chip bus type SPI are incompatible. Probing for Eon EN25F80, 1024 KB: skipped. Host bus type LPC,FWH and chip bus type SPI are incompatible. Probing for Eon EN25F16, 2048 KB: skipped. Host bus type LPC,FWH and chip bus type SPI are incompatible. Probing for Eon EN25F32, 4096 KB: skipped. Host bus type LPC,FWH and chip bus type SPI are incompatible. Probing for EON EN29F002(A)(N)B, 256 KB: skipped. Host bus type LPC,FWH and chip bus type Parallel are incompatible. Probing for EON EN29F002(A)(N)T, 256 KB: skipped. Host bus type LPC,FWH and chip bus type Parallel are incompatible. Probing for Fujitsu MBM29F004BC, 512 KB: skipped. Host bus type LPC,FWH and chip bus type Parallel are incompatible. Probing for Fujitsu MBM29F004TC, 512 KB: skipped. Host bus type LPC,FWH and chip bus type Parallel are incompatible. Probing for Fujitsu MBM29F400BC, 512 KB: skipped. Host bus type LPC,FWH and chip bus type Parallel are incompatible. Probing for Fujitsu MBM29F400TC, 512 KB: skipped. Host bus type LPC,FWH and chip bus type Parallel are incompatible. Probing for Intel 28F001BX-B, 128 KB: skipped. Host bus type LPC,FWH and chip bus type Parallel are incompatible. Probing for Intel 28F001BX-T, 128 KB: skipped. Host bus type LPC,FWH and chip bus type Parallel are incompatible. Probing for Intel 82802AB, 512 KB: probe_82802ab: id1 0x81, id2 0x6e Probing for Intel 82802AC, 1024 KB: probe_82802ab: id1 0x02, id2 0x10 Probing for Macronix MX25L512, 64 KB: skipped. Host bus type LPC,FWH and chip bus type SPI are incompatible. Probing for Macronix MX25L1005, 128 KB: skipped. Host bus type LPC,FWH and chip bus type SPI are incompatible. Probing for Macronix MX25L2005, 256 KB: skipped. Host bus type LPC,FWH and chip bus type SPI are incompatible. Probing for Macronix MX25L4005, 512 KB: skipped. Host bus type LPC,FWH and chip bus type SPI are incompatible. Probing for Macronix MX25L8005, 1024 KB: skipped. Host bus type LPC,FWH and chip bus type SPI are incompatible. Probing for Macronix MX25L1605, 2048 KB: skipped. Host bus type LPC,FWH and chip bus type SPI are incompatible. Probing for Macronix MX25L1635D, 2048 KB: skipped. Host bus type LPC,FWH and chip bus type SPI are incompatible. Probing for Macronix MX25L3205, 4096 KB: skipped. Host bus type LPC,FWH and chip bus type SPI are incompatible. Probing for Macronix MX25L3235D, 4096 KB: skipped. Host bus type LPC,FWH and chip bus type SPI are incompatible. Probing for Macronix MX25L6405, 8192 KB: skipped. Host bus type LPC,FWH and chip bus type SPI are incompatible. Probing for Macronix MX25L12805, 16384 KB: skipped. Host bus type LPC,FWH and chip bus type SPI are incompatible. Probing for Macronix MX29F001B, 128 KB: skipped. Host bus type LPC,FWH and chip bus type Parallel are incompatible. Probing for Macronix MX29F001T, 128 KB: skipped. Host bus type LPC,FWH and chip bus type Parallel are incompatible. Probing for Macronix MX29F002B, 256 KB: skipped. Host bus type LPC,FWH and chip bus type Parallel are incompatible. Probing for Macronix MX29F002T, 256 KB: skipped. Host bus type LPC,FWH and chip bus type Parallel are incompatible. Probing for Macronix MX29LV040, 512 KB: skipped. Host bus type LPC,FWH and chip bus type Parallel are incompatible. Probing for Numonyx M25PE10, 128 KB: skipped. Host bus type LPC,FWH and chip bus type SPI are incompatible. Probing for Numonyx M25PE20, 256 KB: skipped. Host bus type LPC,FWH and chip bus type SPI are incompatible. Probing for Numonyx M25PE40, 256 KB: skipped. Host bus type LPC,FWH and chip bus type SPI are incompatible. Probing for Numonyx M25PE80, 1024 KB: skipped. Host bus type LPC,FWH and chip bus type SPI are incompatible. Probing for Numonyx M25PE16, 2048 KB: skipped. Host bus type LPC,FWH and chip bus type SPI are incompatible. Probing for PMC Pm25LV010, 128 KB: skipped. Host bus type LPC,FWH and chip bus type SPI are incompatible. Probing for PMC Pm25LV016B, 2048 KB: skipped. Host bus type LPC,FWH and chip bus type SPI are incompatible. Probing for PMC Pm25LV020, 256 KB: skipped. Host bus type LPC,FWH and chip bus type SPI are incompatible. Probing for PMC Pm25LV040, 512 KB: skipped. Host bus type LPC,FWH and chip bus type SPI are incompatible. Probing for PMC Pm25LV080B, 1024 KB: skipped. Host bus type LPC,FWH and chip bus type SPI are incompatible. Probing for PMC Pm25LV512, 64 KB: skipped. Host bus type LPC,FWH and chip bus type SPI are incompatible. Probing for PMC Pm29F0002T, 256 KB: skipped. Host bus type LPC,FWH and chip bus type Parallel are incompatible. Probing for PMC Pm29F0002B, 256 KB: skipped. Host bus type LPC,FWH and chip bus type Parallel are incompatible. Probing for PMC Pm39LV010, 128 KB: skipped. Host bus type LPC,FWH and chip bus type Parallel are incompatible. Probing for PMC Pm49FL002, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm49FL004, 512 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0x81, id2 0x6e, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Sharp LHF00L04, 1024 KB: probe_lhf00l04: id1 0x02, id2 0x10 Probing for Spansion S25FL016A, 2048 KB: skipped. Host bus type LPC,FWH and chip bus type SPI are incompatible. Probing for SST SST25VF016B, 2048 KB: skipped. Host bus type LPC,FWH and chip bus type SPI are incompatible. Probing for SST SST25VF032B, 4096 KB: skipped. Host bus type LPC,FWH and chip bus type SPI are incompatible. Probing for SST SST25VF040B, 512 KB: skipped. Host bus type LPC,FWH and chip bus type SPI are incompatible. Probing for SST SST25VF040.REMS, 512 KB: skipped. Host bus type LPC,FWH and chip bus type SPI are incompatible. Probing for SST SST25VF040B.REMS, 512 KB: skipped. Host bus type LPC,FWH and chip bus type SPI are incompatible. Probing for SST SST25VF080B, 1024 KB: skipped. Host bus type LPC,FWH and chip bus type SPI are incompatible. Probing for SST SST28SF040A, 512 KB: skipped. Host bus type LPC,FWH and chip bus type Parallel are incompatible. Probing for SST SST29EE010, 128 KB: skipped. Host bus type LPC,FWH and chip bus type Parallel are incompatible. Probing for SST SST29LE010, 128 KB: skipped. Host bus type LPC,FWH and chip bus type Parallel are incompatible. Probing for SST SST29EE020A, 256 KB: skipped. Host bus type LPC,FWH and chip bus type Parallel are incompatible. Probing for SST SST29LE020, 256 KB: skipped. Host bus type LPC,FWH and chip bus type Parallel are incompatible. Probing for SST SST39SF010A, 128 KB: skipped. Host bus type LPC,FWH and chip bus type Parallel are incompatible. Probing for SST SST39SF020A, 256 KB: skipped. Host bus type LPC,FWH and chip bus type Parallel are incompatible. Probing for SST SST39SF040, 512 KB: skipped. Host bus type LPC,FWH and chip bus type Parallel are incompatible. Probing for SST SST39VF512, 64 KB: skipped. Host bus type LPC,FWH and chip bus type Parallel are incompatible. Probing for SST SST39VF010, 128 KB: skipped. Host bus type LPC,FWH and chip bus type Parallel are incompatible. Probing for SST SST39VF020, 256 KB: skipped. Host bus type LPC,FWH and chip bus type Parallel are incompatible. Probing for SST SST39VF040, 512 KB: skipped. Host bus type LPC,FWH and chip bus type Parallel are incompatible. Probing for SST SST39VF080, 1024 KB: skipped. Host bus type LPC,FWH and chip bus type Parallel are incompatible. Probing for SST SST49LF002A/B, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF003A/B, 384 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF004A/B, 512 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0x81, id2 0x6e, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF004C, 512 KB: probe_49lfxxxc: id1 0x81, id2 0x6e Probing for SST SST49LF008A, 1024 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0x02, id2 0x10, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF008C, 1024 KB: probe_49lfxxxc: id1 0x02, id2 0x10 Probing for SST SST49LF016C, 2048 KB: probe_49lfxxxc: id1 0xff, id2 0xff Probing for SST SST49LF020, 256 KB: probe_jedec: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF020A, 256 KB: probe_jedec: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF040, 512 KB: probe_jedec: id1 0x81, id2 0x6e, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF040B, 512 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0x81, id2 0x6e, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF080A, 1024 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0x02, id2 0x10, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF160C, 2048 KB: probe_49lfxxxc: id1 0xff, id2 0xff Probing for ST M25P05-A, 64 KB: skipped. Host bus type LPC,FWH and chip bus type SPI are incompatible. Probing for ST M25P05.RES, 64 KB: skipped. Host bus type LPC,FWH and chip bus type SPI are incompatible. Probing for ST M25P10-A, 128 KB: skipped. Host bus type LPC,FWH and chip bus type SPI are incompatible. Probing for ST M25P10.RES, 128 KB: skipped. Host bus type LPC,FWH and chip bus type SPI are incompatible. Probing for ST M25P20, 256 KB: skipped. Host bus type LPC,FWH and chip bus type SPI are incompatible. Probing for ST M25P40, 512 KB: skipped. Host bus type LPC,FWH and chip bus type SPI are incompatible. Probing for ST M25P40-old, 512 KB: skipped. Host bus type LPC,FWH and chip bus type SPI are incompatible. Probing for ST M25P80, 1024 KB: skipped. Host bus type LPC,FWH and chip bus type SPI are incompatible. Probing for ST M25P16, 2048 KB: skipped. Host bus type LPC,FWH and chip bus type SPI are incompatible. Probing for ST M25P32, 4096 KB: skipped. Host bus type LPC,FWH and chip bus type SPI are incompatible. Probing for ST M25P64, 8192 KB: skipped. Host bus type LPC,FWH and chip bus type SPI are incompatible. Probing for ST M25P128, 16384 KB: skipped. Host bus type LPC,FWH and chip bus type SPI are incompatible. Probing for ST M29F002B, 256 KB: skipped. Host bus type LPC,FWH and chip bus type Parallel are incompatible. Probing for ST M29F002T/NT, 256 KB: skipped. Host bus type LPC,FWH and chip bus type Parallel are incompatible. Probing for ST M29F040B, 512 KB: skipped. Host bus type LPC,FWH and chip bus type Parallel are incompatible. Probing for ST M29F400BT, 512 KB: skipped. Host bus type LPC,FWH and chip bus type Parallel are incompatible. Probing for ST M29W010B, 128 KB: skipped. Host bus type LPC,FWH and chip bus type Parallel are incompatible. Probing for ST M29W040B, 512 KB: skipped. Host bus type LPC,FWH and chip bus type Parallel are incompatible. Probing for ST M50FLW040A, 512 KB: probe_stm50flw0x0x: id1 0x81, id2 0x6e Probing for ST M50FLW040B, 512 KB: probe_stm50flw0x0x: id1 0x81, id2 0x6e Probing for ST M50FLW080A, 1024 KB: probe_stm50flw0x0x: id1 0x02, id2 0x10 Probing for ST M50FLW080B, 1024 KB: probe_stm50flw0x0x: id1 0x02, id2 0x10 Probing for ST M50FW002, 256 KB: probe_49lfxxxc: id1 0xff, id2 0xff Probing for ST M50FW016, 2048 KB: probe_82802ab: id1 0xff, id2 0xff Probing for ST M50FW040, 512 KB: probe_82802ab: id1 0x81, id2 0x6e Probing for ST M50FW080, 1024 KB: probe_82802ab: id1 0x02, id2 0x10 Probing for ST M50LPW116, 2048 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SyncMOS S29C31004T, 512 KB: skipped. Host bus type LPC,FWH and chip bus type Parallel are incompatible. Probing for SyncMOS S29C51001T, 128 KB: skipped. Host bus type LPC,FWH and chip bus type Parallel are incompatible. Probing for SyncMOS S29C51002T, 256 KB: skipped. Host bus type LPC,FWH and chip bus type Parallel are incompatible. Probing for SyncMOS S29C51004T, 512 KB: skipped. Host bus type LPC,FWH and chip bus type Parallel are incompatible. Probing for TI TMS29F002RB, 256 KB: skipped. Host bus type LPC,FWH and chip bus type Parallel are incompatible. Probing for TI TMS29F002RT, 256 KB: skipped. Host bus type LPC,FWH and chip bus type Parallel are incompatible. Probing for Winbond W25x10, 128 KB: skipped. Host bus type LPC,FWH and chip bus type SPI are incompatible. Probing for Winbond W25x20, 256 KB: skipped. Host bus type LPC,FWH and chip bus type SPI are incompatible. Probing for Winbond W25x40, 512 KB: skipped. Host bus type LPC,FWH and chip bus type SPI are incompatible. Probing for Winbond W25x80, 1024 KB: skipped. Host bus type LPC,FWH and chip bus type SPI are incompatible. Probing for Winbond W25x16, 2048 KB: skipped. Host bus type LPC,FWH and chip bus type SPI are incompatible. Probing for Winbond W29C011, 128 KB: skipped. Host bus type LPC,FWH and chip bus type Parallel are incompatible. Probing for Winbond W29C020C, 256 KB: skipped. Host bus type LPC,FWH and chip bus type Parallel are incompatible. Probing for Winbond W29C040P, 512 KB: skipped. Host bus type LPC,FWH and chip bus type Parallel are incompatible. Probing for Winbond W29EE011, 128 KB: skipped. Host bus type LPC,FWH and chip bus type Parallel are incompatible. Probing for Winbond W39V040A, 512 KB: probe_jedec: id1 0x81, id2 0x6e, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040B, 512 KB: probe_jedec: id1 0x81, id2 0x6e, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040C, 512 KB: probe_w39v040c: id1 0x81, id2 0x6e, id1 parity violation Probing for Winbond W39V040FA, 512 KB: probe_jedec: id1 0x81, id2 0x6e, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V080A, 1024 KB: probe_jedec: id1 0x02, id2 0x10, id1 is normal flash content, id2 is normal flash content Probing for Winbond W49F002U, 256 KB: skipped. Host bus type LPC,FWH and chip bus type Parallel are incompatible. Probing for Winbond W49V002A, 256 KB: probe_jedec: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W49V002FA, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V080FA, 1024 KB: probe_winbond_fwhub: id1 0x2, id2 0x10 Probing for Winbond W39V080FA (dual mode), 512 KB: probe_winbond_fwhub: id1 0x81, id2 0x6e Probing for Atmel unknown Atmel SPI chip, 0 KB: skipped. Host bus type LPC,FWH and chip bus type SPI are incompatible. Probing for EON unknown EON SPI chip, 0 KB: skipped. Host bus type LPC,FWH and chip bus type SPI are incompatible. Probing for Macronix unknown Macronix SPI chip, 0 KB: skipped. Host bus type LPC,FWH and chip bus type SPI are incompatible. Probing for PMC unknown PMC SPI chip, 0 KB: skipped. Host bus type LPC,FWH and chip bus type SPI are incompatible. Probing for SST unknown SST SPI chip, 0 KB: skipped. Host bus type LPC,FWH and chip bus type SPI are incompatible. Probing for ST unknown ST SPI chip, 0 KB: skipped. Host bus type LPC,FWH and chip bus type SPI are incompatible. No EEPROM/flash device found. If you know which flash chip you have, and if this version of flashrom supports a similar flash chip, you can try to force read your chip. Run: flashrom -f -r -c similar_supported_flash_chip filename Note: flashrom can never write when the flash chip isn't found automatically. $ lspci -nnvvvxxx 00:00.0 Host bridge [0600]: ATI Technologies Inc RS690 Host Bridge [1002:7910] Subsystem: Gateway 2000 Device [107b:0184] Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap- 66MHz+ UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort+ >SERR- <PERR- INTx- Latency: 64 00: 02 10 10 79 06 00 20 22 00 00 00 06 00 40 00 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 7b 10 84 01 30: 00 00 00 00 c4 00 00 00 00 00 00 00 00 00 00 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 42 20 05 00 50: 7b 10 84 01 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 8f 04 00 00 00 02 20 00 e8 f8 01 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 40 45 00 00 95 00 07 03 20 05 10 00 12 26 00 10 90: 00 00 00 b0 40 c4 40 e4 00 c0 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 07 01 00 00 49 01 10 07 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 08 00 94 01 60 20 11 11 d0 00 00 00 d0: 25 05 65 00 02 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 01 00 00 00 b0 ff bf f0: 00 00 00 00 00 80 80 00 00 00 00 00 00 00 00 00 00:01.0 PCI bridge [0604]: ATI Technologies Inc RS690 PCI to PCI Bridge (Internal gfx) [1002:7912] (prog-if 00 [Normal decode]) Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz+ UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 64 Bus: primary=00, secondary=01, subordinate=01, sec-latency=64 I/O behind bridge: 00009000-00009fff Memory behind bridge: f0000000-f01fffff Prefetchable memory behind bridge: 00000000d0000000-00000000dfffffff Secondary status: 66MHz+ FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- <SERR- <PERR- BridgeCtl: Parity- SERR- NoISA+ VGA+ MAbort- >Reset- FastB2B- PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- Capabilities: [44] HyperTransport: MSI Mapping Enable+ Fixed+ Capabilities: [b0] Subsystem: ATI Technologies Inc RS690 PCI to PCI Bridge (Internal gfx) [1002:7912] 00: 02 10 12 79 07 00 30 02 00 00 04 06 00 40 01 00 10: 00 00 00 00 00 00 00 00 00 01 01 40 91 91 20 02 20: 00 f0 10 f0 01 d0 f1 df 00 00 00 00 00 00 00 00 30: 00 00 00 00 44 00 00 00 00 00 00 00 ff 00 0c 00 40: 00 00 00 00 08 b0 03 a8 00 00 00 00 02 10 12 79 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 0d 00 00 00 02 10 12 79 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:06.0 PCI bridge [0604]: ATI Technologies Inc RS690 PCI to PCI Bridge (PCI Express Port 2) [1002:7916] (prog-if 00 [Normal decode]) Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+ Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0, Cache Line Size: 32 bytes Bus: primary=00, secondary=02, subordinate=04, sec-latency=0 I/O behind bridge: 0000f000-00000fff Memory behind bridge: f0200000-f02fffff Prefetchable memory behind bridge: 00000000fff00000-00000000000fffff Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort+ <SERR- <PERR- BridgeCtl: Parity- SERR- NoISA+ VGA- MAbort- >Reset- FastB2B- PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- Capabilities: [50] Power Management version 3 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- Capabilities: [58] Express (v1) Root Port (Slot+), MSI 00 DevCap: MaxPayload 128 bytes, PhantFunc 0, Latency L0s <64ns, L1 <1us ExtTag+ RBE+ FLReset- DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop+ MaxPayload 128 bytes, MaxReadReq 128 bytes DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend- LnkCap: Port #3, Speed 2.5GT/s, Width x1, ASPM L0s L1, Latency L0 <64ns, L1 <1us ClockPM- Surprise- LLActRep+ BwNot- LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- Retrain- CommClk+ ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- LnkSta: Speed 2.5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive+ BWMgmt- ABWMgmt- SltCap: AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug- Surpise- Slot # 6, PowerLimit 25.000000; Interlock- NoCompl- SltCtl: Enable: AttnBtn- PwrFlt- MRL- PresDet- CmdCplt- HPIrq- LinkChg- Control: AttnInd Off, PwrInd Off, Power- Interlock- SltSta: Status: AttnBtn- PowerFlt- MRL- CmdCplt- PresDet+ Interlock- Changed: MRL- PresDet+ LinkState- RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna- CRSVisible- RootCap: CRSVisible- RootSta: PME ReqID 0000, PMEStatus- PMEPending- Capabilities: [80] MSI: Enable+ Count=1/1 Maskable- 64bit- Address: fee0100c Data: 4149 Capabilities: [b0] Subsystem: Gateway 2000 Device [107b:0184] Capabilities: [b8] HyperTransport: MSI Mapping Enable+ Fixed+ Capabilities: [100] Virtual Channel <?> Kernel driver in use: pcieport-driver 00: 02 10 16 79 07 04 10 00 00 00 04 06 08 00 01 00 10: 00 00 00 00 00 00 00 00 00 02 04 00 f1 01 00 20 20: 20 f0 20 f0 f1 ff 01 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 50 00 00 00 00 00 00 00 ff 00 04 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 01 58 03 c8 00 00 00 00 10 80 41 01 20 80 00 00 60: 10 08 00 00 11 0c 10 03 40 00 11 30 80 0c 30 00 70: c0 03 48 00 00 00 01 00 00 00 00 00 00 00 00 00 80: 05 b0 01 00 0c 10 e0 fe 49 41 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 0d b8 00 00 7b 10 84 01 08 00 03 a8 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 ff ff ff ff 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:07.0 PCI bridge [0604]: ATI Technologies Inc RS690 PCI to PCI Bridge (PCI Express Port 3) [1002:7917] (prog-if 00 [Normal decode]) Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+ Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0, Cache Line Size: 32 bytes Bus: primary=00, secondary=05, subordinate=07, sec-latency=0 I/O behind bridge: 0000a000-0000afff Memory behind bridge: c0000000-c00fffff Prefetchable memory behind bridge: 00000000cfd00000-00000000cfdfffff Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- <SERR- <PERR- BridgeCtl: Parity- SERR- NoISA+ VGA- MAbort- >Reset- FastB2B- PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- Capabilities: [50] Power Management version 3 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- Capabilities: [58] Express (v1) Root Port (Slot+), MSI 00 DevCap: MaxPayload 128 bytes, PhantFunc 0, Latency L0s <64ns, L1 <1us ExtTag+ RBE+ FLReset- DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop+ MaxPayload 128 bytes, MaxReadReq 128 bytes DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend- LnkCap: Port #4, Speed 2.5GT/s, Width x1, ASPM L0s L1, Latency L0 <64ns, L1 <1us ClockPM- Surprise- LLActRep+ BwNot- LnkCtl: ASPM L1 Enabled; RCB 64 bytes Disabled- Retrain- CommClk+ ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- LnkSta: Speed 2.5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive+ BWMgmt- ABWMgmt- SltCap: AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug- Surpise- Slot # 6, PowerLimit 25.000000; Interlock- NoCompl- SltCtl: Enable: AttnBtn- PwrFlt- MRL- PresDet- CmdCplt- HPIrq- LinkChg- Control: AttnInd Off, PwrInd Off, Power- Interlock- SltSta: Status: AttnBtn- PowerFlt- MRL- CmdCplt- PresDet+ Interlock- Changed: MRL- PresDet+ LinkState- RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna- CRSVisible- RootCap: CRSVisible- RootSta: PME ReqID 0000, PMEStatus- PMEPending- Capabilities: [80] MSI: Enable+ Count=1/1 Maskable- 64bit- Address: fee0100c Data: 4151 Capabilities: [b0] Subsystem: Gateway 2000 Device [107b:0184] Capabilities: [b8] HyperTransport: MSI Mapping Enable+ Fixed+ Capabilities: [100] Virtual Channel <?> Kernel driver in use: pcieport-driver 00: 02 10 17 79 07 04 10 00 00 00 04 06 08 00 01 00 10: 00 00 00 00 00 00 00 00 00 05 07 00 a1 a1 00 00 20: 00 c0 00 c0 d1 cf d1 cf 00 00 00 00 00 00 00 00 30: 00 00 00 00 50 00 00 00 00 00 00 00 ff 00 04 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 01 58 03 c8 00 00 00 00 10 80 41 01 20 80 00 00 60: 10 08 00 00 11 0c 10 04 42 00 11 30 80 0c 30 00 70: c0 03 48 00 00 00 01 00 00 00 00 00 00 00 00 00 80: 05 b0 01 00 0c 10 e0 fe 51 41 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 0d b8 00 00 7b 10 84 01 08 00 03 a8 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 ff ff ff ff 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:12.0 SATA controller [0106]: ATI Technologies Inc SB600 Non-Raid-5 SATA [1002:4380] (prog-if 01 [AHCI 1.0]) Subsystem: Gateway 2000 Device [107b:0184] Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz+ UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 64 Interrupt: pin A routed to IRQ 22 Region 0: I/O ports at 8440 [size=8] Region 1: I/O ports at 8434 [size=4] Region 2: I/O ports at 8438 [size=8] Region 3: I/O ports at 8430 [size=4] Region 4: I/O ports at 8400 [size=16] Region 5: Memory at f0507000 (32-bit, non-prefetchable) [size=1K] Capabilities: [60] Power Management version 2 Flags: PMEClk- DSI+ D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- Kernel driver in use: ahci 00: 02 10 80 43 07 00 30 02 00 01 06 01 00 40 00 00 10: 41 84 00 00 35 84 00 00 39 84 00 00 31 84 00 00 20: 01 84 00 00 00 70 50 f0 00 00 00 00 7b 10 84 01 30: 00 00 00 00 60 00 00 00 00 00 00 00 0b 01 00 00 40: 10 00 8a 02 01 00 10 00 01 00 00 00 00 00 00 00 50: 05 00 84 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 01 00 22 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 12 00 10 00 0f 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 06 00 00 2c de 21 b4 00 de 21 b4 00 90: de 21 b4 00 de 21 b4 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 b8 00 00 00 00 00 00 00 b8 00 00 b0: 00 00 00 00 00 b8 00 00 00 00 00 00 00 b8 00 00 c0: 00 20 00 00 80 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:13.0 USB Controller [0c03]: ATI Technologies Inc SB600 USB (OHCI0) [1002:4387] (prog-if 10 [OHCI]) Subsystem: Gateway 2000 Device [107b:0184] Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV+ VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap- 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 64, Cache Line Size: 32 bytes Interrupt: pin A routed to IRQ 16 Region 0: Memory at f0504000 (32-bit, non-prefetchable) [size=4K] Kernel driver in use: ohci_hcd 00: 02 10 87 43 17 00 a0 02 00 10 03 0c 08 40 80 00 10: 00 40 50 f0 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 7b 10 84 01 30: 00 00 00 00 00 00 00 00 00 00 00 00 0b 01 00 00 40: 80 1f 00 00 0a 84 b7 18 07 35 00 00 00 00 00 00 50: 00 98 00 00 00 00 00 00 ff ff ff ff ff 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 ff 00 00 80 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:13.1 USB Controller [0c03]: ATI Technologies Inc SB600 USB (OHCI1) [1002:4388] (prog-if 10 [OHCI]) Subsystem: Gateway 2000 Device [107b:0184] Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV+ VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap- 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 64, Cache Line Size: 32 bytes Interrupt: pin B routed to IRQ 17 Region 0: Memory at f0505000 (32-bit, non-prefetchable) [size=4K] Kernel driver in use: ohci_hcd 00: 02 10 88 43 17 00 a0 02 00 10 03 0c 08 40 00 00 10: 00 50 50 f0 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 7b 10 84 01 30: 00 00 00 00 00 00 00 00 00 00 00 00 0b 02 00 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:13.4 USB Controller [0c03]: ATI Technologies Inc SB600 USB (OHCI4) [1002:438b] (prog-if 10 [OHCI]) Subsystem: Gateway 2000 Device [107b:0184] Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV+ VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap- 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 64, Cache Line Size: 32 bytes Interrupt: pin C routed to IRQ 18 Region 0: Memory at f0506000 (32-bit, non-prefetchable) [size=4K] Kernel driver in use: ohci_hcd 00: 02 10 8b 43 17 00 a0 02 00 10 03 0c 08 40 00 00 10: 00 60 50 f0 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 7b 10 84 01 30: 00 00 00 00 00 00 00 00 00 00 00 00 0b 03 00 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:13.5 USB Controller [0c03]: ATI Technologies Inc SB600 USB Controller (EHCI) [1002:4386] (prog-if 20 [EHCI]) Subsystem: Gateway 2000 Device [107b:0184] Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV+ VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 64, Cache Line Size: 64 bytes Interrupt: pin D routed to IRQ 19 Region 0: Memory at f0507400 (32-bit, non-prefetchable) [size=256] Capabilities: [c0] Power Management version 2 Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot+,D3cold-) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- Bridge: PM- B3+ Capabilities: [e4] Debug port: BAR=1 offset=00e0 Kernel driver in use: ehci_hcd 00: 02 10 86 43 17 00 b0 02 00 20 03 0c 10 40 00 00 10: 00 74 50 f0 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 7b 10 84 01 30: 00 00 00 00 c0 00 00 00 00 00 00 00 0b 04 00 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 40 00 0e 08 00 00 00 00 00 00 00 00 00 00 00 00 60: 20 20 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 01 00 00 01 00 00 08 c0 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 01 e4 02 7e 00 00 40 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 0a 00 e0 20 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:14.0 SMBus [0c05]: ATI Technologies Inc SBx00 SMBus Controller [1002:4385] (rev 14) Subsystem: ATI Technologies Inc SBx00 SMBus Controller [1002:4385] Control: I/O+ Mem+ BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz+ UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Region 0: I/O ports at 8410 [size=16] Capabilities: [b0] HyperTransport: MSI Mapping Enable- Fixed+ Kernel driver in use: piix4_smbus 00: 02 10 85 43 03 00 30 02 14 00 05 0c 00 00 80 00 10: 11 84 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 02 10 85 43 30: 00 00 00 00 b0 00 00 00 00 00 00 00 00 00 00 00 40: d4 bb 00 04 00 00 00 00 0f ff 00 00 00 00 00 00 50: f0 01 f0 0e f0 0f f0 0f 51 80 f0 0f 00 00 00 00 60: 01 00 07 00 bf fd de 8f 27 90 00 00 20 00 00 00 70: 00 01 00 00 08 00 c0 fe ff 6f 00 00 00 00 f0 0e 80: 78 0a f0 0f 00 00 00 00 00 00 00 00 8c 00 00 80 90: 11 84 00 00 fd ce ff 00 00 00 00 00 00 00 00 00 a0: 00 00 ff ff ff ff f0 08 02 fd 02 02 14 79 20 18 b0: 08 00 02 a8 00 00 00 00 00 00 00 00 f0 0f 08 1a c0: 7d db b6 ed 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 01 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 20 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: d8 0c 00 00 7f 08 00 00 00 00 00 00 aa 00 10 01 00:14.1 IDE interface [0101]: ATI Technologies Inc SB600 IDE [1002:438c] (prog-if 8a [Master SecP PriP]) Subsystem: ATI Technologies Inc SB600 IDE [1002:438c] Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV+ VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap- 66MHz+ UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 64 Interrupt: pin A routed to IRQ 16 Region 0: I/O ports at 01f0 [size=8] Region 1: I/O ports at 03f4 [size=1] Region 2: I/O ports at 0170 [size=8] Region 3: I/O ports at 0374 [size=1] Region 4: I/O ports at 8420 [size=16] Kernel driver in use: pata_atiixp 00: 02 10 8c 43 15 00 20 02 00 8a 01 01 00 40 00 00 10: f1 01 00 00 f5 03 00 00 01 00 00 00 01 00 00 00 20: 21 84 00 00 00 00 00 00 00 00 00 00 02 10 8c 43 30: 00 00 00 00 00 00 00 00 00 00 00 00 ff 01 00 00 40: 5d 5d 00 00 ff ff 00 00 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 40 00 10 2c 01 07 01 00 00 00 ff ff 0f 00 70: 05 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:14.2 Audio device [0403]: ATI Technologies Inc SBx00 Azalia (Intel HDA) [1002:4383] Subsystem: Gateway 2000 Device [107b:0184] Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=slow >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 64, Cache Line Size: 32 bytes Interrupt: pin ? routed to IRQ 16 Region 0: Memory at f0500000 (64-bit, non-prefetchable) [size=16K] Capabilities: [50] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=55mA PME(D0+,D1-,D2-,D3hot+,D3cold+) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- Kernel driver in use: HDA Intel 00: 02 10 83 43 06 00 10 04 00 00 03 04 08 40 00 00 10: 04 00 50 f0 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 7b 10 84 01 30: 00 00 00 00 50 00 00 00 00 00 00 00 0b 00 00 00 40: 00 00 02 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 01 00 42 c8 00 00 00 00 00 00 00 00 00 00 00 00 60: 05 00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:14.3 ISA bridge [0601]: ATI Technologies Inc SB600 PCI to LPC Bridge [1002:438d] Subsystem: ATI Technologies Inc SB600 PCI to LPC Bridge [1002:438d] Control: I/O+ Mem+ BusMaster+ SpecCycle+ MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap- 66MHz+ UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 00: 02 10 8d 43 0f 00 20 02 00 00 01 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 02 10 8d 43 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40: 04 00 00 00 ff ff c3 ff 07 ff 62 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 68 00 00 00 0e 00 0f 00 70 ff ff ff 70: 67 45 23 00 01 00 00 00 01 00 00 00 05 00 00 00 80: 08 00 03 a8 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:14.4 PCI bridge [0604]: ATI Technologies Inc SBx00 PCI to PCI Bridge [1002:4384] (prog-if 01 [Subtractive decode]) Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap- 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 64 Bus: primary=00, secondary=08, subordinate=0a, sec-latency=64 I/O behind bridge: 0000f000-00000fff Memory behind bridge: fff00000-000fffff Prefetchable memory behind bridge: fff00000-000fffff Secondary status: 66MHz- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort+ <SERR- <PERR- BridgeCtl: Parity- SERR+ NoISA- VGA- MAbort- >Reset- FastB2B- PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- 00: 02 10 84 43 07 00 a0 02 00 01 04 06 00 40 81 00 10: 00 00 00 00 00 00 00 00 00 08 0a 40 f0 00 80 22 20: f0 ff 00 00 f0 ff 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 02 00 40: 26 00 0c ff 00 00 00 00 0c 01 38 d1 00 00 00 00 50: 01 00 00 00 08 00 03 a8 00 00 00 00 85 00 ff ff 60: ca 0e 17 00 ba 18 10 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 01 00 02 06 e0: 00 00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:18.0 Host bridge [0600]: Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] HyperTransport Technology Configuration [1022:1100] Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Capabilities: [80] HyperTransport: Host or Secondary Interface Command: WarmRst+ DblEnd- DevNum=0 ChainSide- HostHide+ Slave- <EOCErr- DUL- Link Control: CFlE- CST- CFE- <LkFail- Init+ EOC- TXO- <CRCErr=8 IsocEn- LSEn+ ExtCTL- 64b+ Link Config: MLWI=16bit DwFcIn- MLWO=16bit DwFcOut- LWI=16bit DwFcInEn- LWO=16bit DwFcOutEn- Revision ID: 1.02 Link Frequency: 800MHz Link Error: <Prot- <Ovfl- <EOC- CTLTm- Link Frequency Capability: 200MHz+ 300MHz- 400MHz+ 500MHz- 600MHz+ 800MHz+ 1.0GHz- 1.2GHz- 1.4GHz- 1.6GHz- Vend- Feature Capability: IsocFC- LDTSTOP+ CRCTM- ECTLT- 64bA- UIDRD- ExtRS- UCnfE- 00: 22 10 00 11 00 00 10 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 80 00 00 00 00 00 00 00 00 00 00 00 40: 01 01 01 00 01 01 01 00 01 01 01 00 01 01 01 00 50: 01 01 01 00 01 01 01 00 01 01 01 00 01 01 01 00 60: 00 00 00 00 e4 00 00 00 0f cc 2f 0f 3c 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 08 00 01 21 20 a8 11 11 22 05 35 80 02 00 00 00 90: 78 01 70 01 00 00 00 00 07 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:18.1 Host bridge [0600]: Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] Address Map [1022:1101] Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap- 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- 00: 22 10 01 11 00 00 00 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40: 03 00 00 00 00 00 bf 00 00 00 00 00 01 00 00 00 50: 00 00 00 00 02 00 00 00 00 00 00 00 03 00 00 00 60: 00 00 00 00 04 00 00 00 00 00 00 00 05 00 00 00 70: 00 00 00 00 06 00 00 00 00 00 00 00 07 00 00 00 80: 00 00 00 00 00 00 00 00 03 10 f0 00 00 ff ff 00 90: 03 00 e0 00 00 ff df 00 03 00 d0 00 80 ff df 00 a0: 03 0a 00 00 00 0b 00 00 03 00 f0 00 80 0f f0 00 b0: 03 00 e0 00 80 ff ef 00 03 00 c0 00 00 ff cf 00 c0: 00 00 00 00 00 00 00 00 13 10 00 00 00 f0 0f 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 03 00 00 ff 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:18.2 Host bridge [0600]: Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] DRAM Controller [1022:1102] Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap- 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- 00: 22 10 02 11 00 00 00 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40: 01 00 80 00 01 00 a0 00 00 00 00 00 00 00 00 00 50: 01 00 00 00 01 00 40 00 00 00 00 00 00 00 00 00 60: e0 3f 18 00 00 00 00 00 e0 3f 38 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 46 00 00 00 00 00 00 00 80: 04 05 00 00 00 00 00 00 24 ca aa 5d 20 13 22 08 90: 20 04 01 00 6a 80 10 a7 39 00 00 80 00 00 00 00 a0: ff 06 00 5d 00 00 00 00 00 00 00 00 00 00 00 00 b0: 7b 16 1e b9 c3 00 00 00 4f ba 00 08 40 10 02 65 c0: 00 00 01 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 39 04 18 22 03 bc 19 6a 2e a0 78 2a 83 d8 10 2c e0: 30 e0 58 4b 00 f4 88 2c 07 78 08 44 22 68 11 1a f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:18.3 Host bridge [0600]: Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] Miscellaneous Control [1022:1103] Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Capabilities: [f0] Secure device <?> Kernel driver in use: k8temp 00: 22 10 03 11 00 00 10 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 f0 00 00 00 00 00 00 00 00 00 00 00 40: ff 3b 04 00 40 00 10 02 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 c0 fa c2 74 60: e4 00 00 00 00 00 00 00 c0 00 00 00 00 00 00 00 70: 11 01 32 51 21 40 30 50 00 2a 00 08 1c 21 00 00 80: 31 00 07 23 13 21 13 21 00 00 00 00 00 00 00 00 90: 00 00 00 00 01 00 00 00 00 40 08 1e 00 00 00 00 a0: 96 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 01 a7 0d 00 00 00 40 0d 25 26 26 00 e0: 00 00 00 00 36 a2 5f 00 19 07 00 00 00 00 00 00 f0: 0f 00 10 00 00 00 00 00 00 00 00 00 f2 0f 07 00 01:05.0 VGA compatible controller [0300]: ATI Technologies Inc RS690M [Radeon X1200 Series] [1002:791f] (prog-if 00 [VGA controller]) Subsystem: Gateway 2000 Device [107b:0184] Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 64, Cache Line Size: 32 bytes Interrupt: pin A routed to IRQ 18 Region 0: Memory at d0000000 (64-bit, prefetchable) [size=256M] Region 2: Memory at f0100000 (64-bit, non-prefetchable) [size=64K] Region 4: I/O ports at 9400 [size=256] Region 5: Memory at f0000000 (32-bit, non-prefetchable) [size=1M] Expansion ROM at <unassigned> [disabled] Capabilities: [50] Power Management version 2 Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- Capabilities: [80] MSI: Enable- Count=1/1 Maskable- 64bit+ Address: 0000000000000000 Data: 0000 00: 02 10 1f 79 07 00 10 00 00 00 00 03 08 40 00 00 10: 0c 00 00 d0 00 00 00 00 04 00 10 f0 00 00 00 00 20: 01 94 00 00 00 00 00 f0 00 00 00 00 7b 10 84 01 30: 00 00 00 00 50 00 00 00 00 00 00 00 ff 01 00 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 7b 10 84 01 50: 01 80 02 06 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 05 00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 02:00.0 Ethernet controller [0200]: Atheros Communications Inc. AR5001 Wireless Network Adapter [168c:001c] (rev 01) Subsystem: AMBIT Microsystem Corp. AR5BXB63 802.11bg NIC [1468:0428] Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0, Cache Line Size: 32 bytes Interrupt: pin A routed to IRQ 18 Region 0: Memory at f0200000 (64-bit, non-prefetchable) [size=64K] Capabilities: [40] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=375mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- Capabilities: [50] MSI: Enable- Count=1/1 Maskable- 64bit- Address: 00000000 Data: 0000 Capabilities: [60] Express (v1) Legacy Endpoint, MSI 00 DevCap: MaxPayload 128 bytes, PhantFunc 0, Latency L0s <512ns, L1 <64us ExtTag- AttnBtn- AttnInd- PwrInd- RBE- FLReset- DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop- MaxPayload 128 bytes, MaxReadReq 512 bytes DevSta: CorrErr- UncorrErr+ FatalErr- UnsuppReq+ AuxPwr- TransPend- LnkCap: Port #0, Speed 2.5GT/s, Width x1, ASPM L0s L1, Latency L0 <512ns, L1 <64us ClockPM- Surprise- LLActRep- BwNot- LnkCtl: ASPM Disabled; RCB 128 bytes Disabled- Retrain- CommClk+ ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- LnkSta: Speed 2.5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt- Capabilities: [90] MSI-X: Enable- Count=1 Masked- Vector table: BAR=0 offset=00000000 PBA: BAR=0 offset=00000000 Capabilities: [100] Advanced Error Reporting UESta: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq+ ACSViol- UEMsk: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol- UESvrt: DLP+ SDES- TLP- FCP+ CmpltTO- CmpltAbrt- UnxCmplt- RxOF+ MalfTLP+ ECRC- UnsupReq- ACSViol- CESta: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr- CEMsk: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr- AERCap: First Error Pointer: 14, GenCap+ CGenEn- ChkCap+ ChkEn- Capabilities: [140] Virtual Channel <?> Kernel driver in use: ath5k 00: 8c 16 1c 00 07 00 10 00 01 00 00 02 08 00 00 00 10: 04 00 20 f0 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 01 50 00 00 68 14 28 04 30: 00 00 00 00 40 00 00 00 00 00 00 00 0b 01 00 00 40: 01 50 c2 01 00 00 00 00 00 00 00 00 00 00 00 00 50: 05 60 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 10 90 11 00 c0 0c 64 00 10 20 0a 00 11 3c 03 00 70: 48 00 11 10 00 00 00 00 c0 03 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 11 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 05:00.0 Ethernet controller [0200]: Realtek Semiconductor Co., Ltd. RTL8101E/RTL8102E PCI Express Fast Ethernet controller [10ec:8136] (rev 02) Subsystem: Gateway 2000 Device [107b:0184] Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+ Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0, Cache Line Size: 64 bytes Interrupt: pin A routed to IRQ 26 Region 0: I/O ports at a400 [size=256] Region 2: Memory at cfdef000 (64-bit, prefetchable) [size=4K] Region 4: Memory at cfdf0000 (64-bit, prefetchable) [size=64K] [virtual] Expansion ROM at cfd00000 [disabled] [size=128K] Capabilities: [40] Power Management version 3 Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=375mA PME(D0+,D1+,D2+,D3hot+,D3cold+) Status: D0 NoSoftRst+ PME-Enable- DSel=0 DScale=0 PME- Capabilities: [50] MSI: Enable+ Count=1/1 Maskable- 64bit+ Address: 00000000fee0100c Data: 4189 Capabilities: [70] Express (v2) Endpoint, MSI 01 DevCap: MaxPayload 256 bytes, PhantFunc 0, Latency L0s <512ns, L1 <64us ExtTag- AttnBtn- AttnInd- PwrInd- RBE+ FLReset- DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop- MaxPayload 128 bytes, MaxReadReq 4096 bytes DevSta: CorrErr+ UncorrErr- FatalErr- UnsuppReq+ AuxPwr+ TransPend- LnkCap: Port #0, Speed 2.5GT/s, Width x1, ASPM L0s L1, Latency L0 <512ns, L1 <64us ClockPM+ Surprise- LLActRep- BwNot- LnkCtl: ASPM L1 Enabled; RCB 64 bytes Disabled- Retrain- CommClk+ ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- LnkSta: Speed 2.5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt- DevCap2: Completion Timeout: Not Supported, TimeoutDis+ DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis- LnkCtl2: Target Link Speed: 2.5GT/s, EnterCompliance- SpeedDis-, Selectable De-emphasis: -6dB Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS- Compliance De-emphasis: -6dB LnkSta2: Current De-emphasis Level: -6dB Capabilities: [ac] MSI-X: Enable- Count=2 Masked- Vector table: BAR=4 offset=00000000 PBA: BAR=4 offset=00000800 Capabilities: [cc] Vital Product Data Unknown small resource type 00, will not decode more. Capabilities: [100] Advanced Error Reporting UESta: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol- UEMsk: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol- UESvrt: DLP+ SDES+ TLP- FCP+ CmpltTO- CmpltAbrt- UnxCmplt- RxOF+ MalfTLP+ ECRC- UnsupReq- ACSViol- CESta: RxErr+ BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr+ CEMsk: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr+ AERCap: First Error Pointer: 00, GenCap+ CGenEn- ChkCap+ ChkEn- Capabilities: [140] Virtual Channel <?> Capabilities: [160] Device Serial Number 82-05-00-00-ff-ff-00-00 Kernel driver in use: r8169 00: ec 10 36 81 07 04 10 00 02 00 00 02 10 00 00 00 10: 01 a4 00 00 00 00 00 00 0c f0 de cf 00 00 00 00 20: 0c 00 df cf 00 00 00 00 00 00 00 00 7b 10 84 01 30: 00 00 00 00 40 00 00 00 00 00 00 00 0b 01 00 00 40: 01 50 c3 ff 08 00 00 00 00 00 00 00 00 00 00 00 50: 05 70 81 00 0c 10 e0 fe 00 00 00 00 89 41 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 10 ac 02 02 c1 8c 64 00 10 50 19 00 11 3c 07 00 80: 42 00 11 10 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 10 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 11 cc 01 00 b0: 04 00 00 00 04 08 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 03 00 00 80 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

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Re: [flashrom] [SerialICE] an idea
by Carl-Daniel Hailfinger 26 Nov '09

26 Nov '09

[CC flashrom because this is a flashrom topic. Please don't drop it from CC.] On 27.11.2009 01:04, Peter Stuge wrote: > ron minnich wrote: > >> Serialice could have the capability to flash the "normal". >> > > Yes, but I say forget about using flashrom as-is for this. The code > is still pretty much a mess. > Really? The code has changed a lot in the last 6 months. I won't debate that main() is ugly, but the rest of the code is abstracted well enough to support SerialICE as external flasher right now with ~21 LOC (given a fast enough serial line, but timing constraints are not the fault of flashrom). Detailed size estimate for a SerialICE external programmer driver (supporting Parallel/LPC/FWH) in flashrom: Functions for programming are exactly 13 LOC (including function headers, unless SerialICE requires more than 1 write overhead for each read/write). Function for init is ~4 LOC (1 line function header, 1 line opening serial port, 1 line setting buses_supported, 1 line return). Adding required functions to flash.h is 0 LOC (pure cut-n-paste of 3 lines from the new driver). Hooking up the new driver is 4 LOC (copy-n-paste programmer_table it87spi entry, change name/init/writeb/readb). We can even use dummyflasher.c as basis and run s/dummy/serialice/ on 3 functions which saves us 3 LOC and a similar search/replace in programmer_table which saves us writing another 4 LOC, reducing the total to 14 LOC. Writing 14 LOC can't be that hard. Regards, Carl-Daniel P.S. The makefile one-liner and the man page entry are not included in above calculations. -- Developer quote of the month: "We are juggling too many chainsaws and flaming arrows and tigers."

1 0

consts and copies (was: Re: [SerialICE] an idea)
by Stefan Reinauer 26 Nov '09

26 Nov '09

On 11/27/09 12:24 AM, Carl-Daniel Hailfinger wrote: > Well, with some careful changes, I think flashrom can get by with maybe > 2 kB of RAM or CAR. I know what to change, but I can't make 100% correct > RAM requirement estimates. And we'll need boatloads of const keywords. > Patches welcome, especially for the const stuff. The biggest writable > object is the flashchip array. We can make it const, but then we have to > copy each chip to a temporary variable during probe. Not really ideal. Hm. > Why the copy? Can't we instead have a writable struct flashchip_instance and let that contain a pointer to the current readonly struct flashchip member? Stefan

2 3

[PATCH] Add support for Intel 3400 series chipset
by Carl-Daniel Hailfinger 26 Nov '09

26 Nov '09

Add support for Intel 3400 series / 5 series chipset. Found in Intel document 322170 (Intel 5 Series Chipset and Intel 3400 Series Chipset Specification Update). According to http://pciids.sourceforge.net/ we probably should match all IDs from 0x3b00-0x3b1f, but so far I didn't find an Intel doc saying the same. If anybody has contacts at Intel and can check, I'd be happy to add the rest of the IDs. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-intel_3400series_5series/chipset_enable.c =================================================================== --- flashrom-intel_3400series_5series/chipset_enable.c (Revision 782) +++ flashrom-intel_3400series_5series/chipset_enable.c (Arbeitskopie) @@ -1097,6 +1097,9 @@ {0x100b, 0x0510, NT, "AMD", "SC1100", enable_flash_sc1100}, {0x1002, 0x4377, OK, "ATI", "SB400", enable_flash_sb400}, {0x1166, 0x0205, OK, "Broadcom", "HT-1000", enable_flash_ht1000}, + {0x8086, 0x3b00, NT, "Intel", "3400 Desktop", enable_flash_ich10}, + {0x8086, 0x3b01, NT, "Intel", "3400 Mobile", enable_flash_ich10}, + {0x8086, 0x3b0d, NT, "Intel", "3400 Mobile SFF", enable_flash_ich10}, {0x8086, 0x7198, OK, "Intel", "440MX", enable_flash_piix4}, {0x8086, 0x25a1, OK, "Intel", "6300ESB", enable_flash_ich_4e}, {0x8086, 0x2670, OK, "Intel", "631xESB/632xESB/3100", enable_flash_ich_dc}, -- Developer quote of the month: "We are juggling too many chainsaws and flaming arrows and tigers."

2 2

[commit] r784 - trunk
by svn＠flashrom.org 26 Nov '09

26 Nov '09

Author: hailfinger Date: 2009-11-26 17:51:39 +0100 (Thu, 26 Nov 2009) New Revision: 784 Modified: trunk/chipset_enable.c Log: Add support for Intel 3400 series / 5 series chipset. Found in Intel document 322170 (Intel 5 Series Chipset and Intel 3400 Series Chipset Specification Update). According to http://pciids.sourceforge.net/ we probably should match all IDs from 0x3b00-0x3b1f, but so far I didn't find an Intel doc saying the same. If anybody has contacts at Intel and can check, I'd be happy to add the rest of the IDs. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Sean Nelson <audiohacked(a)gmail.com> Modified: trunk/chipset_enable.c =================================================================== --- trunk/chipset_enable.c 2009-11-26 14:50:52 UTC (rev 783) +++ trunk/chipset_enable.c 2009-11-26 16:51:39 UTC (rev 784) @@ -1097,6 +1097,9 @@ {0x100b, 0x0510, NT, "AMD", "SC1100", enable_flash_sc1100}, {0x1002, 0x4377, OK, "ATI", "SB400", enable_flash_sb400}, {0x1166, 0x0205, OK, "Broadcom", "HT-1000", enable_flash_ht1000}, + {0x8086, 0x3b00, NT, "Intel", "3400 Desktop", enable_flash_ich10}, + {0x8086, 0x3b01, NT, "Intel", "3400 Mobile", enable_flash_ich10}, + {0x8086, 0x3b0d, NT, "Intel", "3400 Mobile SFF", enable_flash_ich10}, {0x8086, 0x7198, OK, "Intel", "440MX", enable_flash_piix4}, {0x8086, 0x25a1, OK, "Intel", "6300ESB", enable_flash_ich_4e}, {0x8086, 0x2670, OK, "Intel", "631xESB/632xESB/3100", enable_flash_ich_dc},

1 0

[PATCH] remove JEDEC protect/unprotect
by Michael Karcher 26 Nov '09

26 Nov '09

This patch removes the extremely dangerous unprotect_jedec function which is not used at all within flashrom code, and renames the misleadingly named protect_jedec function to start_program_jedec. Calls to protect_jedec after flashing are removed, because a) on LPC chips, the command sent by protoct_jedec is not even in the datasheet and b) on parallel chips, the block write command issued before already contained the software protection sequence, so software protection is definitely enabled. This patch also removes two clones of protect_jedec Background: JEDEC Software Data Protection started as an optional feature, which was disabled on the first single-voltage-flash chips. The software data protection is the need to prefix a write with a magic "write enable" command, while without write protection every write access into the chip's address space modifies flash content. This magic write enable command also tells the flash chip that the programmer obviously support sending write-enable commands and turns off the "any write modifies flash content" mode. There also exist a two-command (6 writes) sequence that disables Software Data Protection completey, which should only ever be used to prepare updating with a device that can't handle software data protection. Regards, Michael Karcher Index: flash.h =================================================================== --- flash.h (Revision 777) +++ flash.h (Arbeitskopie) @@ -647,8 +647,7 @@ uint8_t oddparity(uint8_t val); void toggle_ready_jedec(chipaddr dst); void data_polling_jedec(chipaddr dst, uint8_t data); -void unprotect_jedec(chipaddr bios); -void protect_jedec(chipaddr bios); +void start_program_jedec(chipaddr bios); int write_byte_program_jedec(chipaddr bios, uint8_t *src, chipaddr dst); int probe_jedec(struct flashchip *flash); Index: jedec.c =================================================================== --- jedec.c (Revision 777) +++ jedec.c (Arbeitskopie) @@ -64,25 +64,11 @@ } } -void unprotect_jedec(chipaddr bios) +void start_program_jedec(chipaddr bios) { chip_writeb(0xAA, bios + 0x5555); chip_writeb(0x55, bios + 0x2AAA); - chip_writeb(0x80, bios + 0x5555); - chip_writeb(0xAA, bios + 0x5555); - chip_writeb(0x55, bios + 0x2AAA); - chip_writeb(0x20, bios + 0x5555); - - programmer_delay(200); -} - -void protect_jedec(chipaddr bios) -{ - chip_writeb(0xAA, bios + 0x5555); - chip_writeb(0x55, bios + 0x2AAA); chip_writeb(0xA0, bios + 0x5555); - - programmer_delay(200); } int probe_jedec(struct flashchip *flash) @@ -270,9 +256,7 @@ retry: /* Issue JEDEC Data Unprotect comand */ - chip_writeb(0xAA, bios + 0x5555); - chip_writeb(0x55, bios + 0x2AAA); - chip_writeb(0xA0, bios + 0x5555); + start_program_jedec(bios); /* transfer data from source to destination */ for (i = 0; i < page_size; i++) { @@ -312,9 +296,7 @@ retry: /* Issue JEDEC Byte Program command */ - chip_writeb(0xAA, bios + 0x5555); - chip_writeb(0x55, bios + 0x2AAA); - chip_writeb(0xA0, bios + 0x5555); + start_program_jedec(bios); /* transfer data from source to destination */ chip_writeb(*src, dst); @@ -348,7 +330,6 @@ int i; int total_size = flash->total_size * 1024; int page_size = flash->page_size; - chipaddr bios = flash->virtual_memory; if (erase_chip_jedec(flash)) { fprintf(stderr,"ERASE FAILED!\n"); @@ -363,7 +344,6 @@ printf("\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b"); } printf("\n"); - protect_jedec(bios); return 0; } Index: sharplhf00l04.c =================================================================== --- sharplhf00l04.c (Revision 777) +++ sharplhf00l04.c (Arbeitskopie) @@ -179,7 +179,6 @@ printf("\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b"); } printf("\n"); - protect_jedec(bios); return 0; } Index: stm50flw0x0x.c =================================================================== --- stm50flw0x0x.c (Revision 777) +++ stm50flw0x0x.c (Arbeitskopie) @@ -31,15 +31,6 @@ #include "flash.h" #include "flashchips.h" -void protect_stm50flw0x0x(chipaddr bios) -{ - chip_writeb(0xAA, bios + 0x5555); - chip_writeb(0x55, bios + 0x2AAA); - chip_writeb(0xA0, bios + 0x5555); - - programmer_delay(200); -} - int probe_stm50flw0x0x(struct flashchip *flash) { int result = probe_jedec(flash); @@ -189,7 +180,6 @@ int i; int total_size = flash->total_size * 1024; int page_size = flash->page_size; - chipaddr bios = flash->virtual_memory; printf("Erasing page:\n"); for (i = 0; i < total_size / page_size; i++) { @@ -206,7 +196,6 @@ } } printf("\n"); - protect_stm50flw0x0x(bios); return 0; } @@ -250,7 +239,6 @@ bios + i * page_size, page_size); } printf("\n"); - protect_stm50flw0x0x(bios); free(tmpbuf); return rc; Index: 82802ab.c =================================================================== --- 82802ab.c (Revision 777) +++ 82802ab.c (Arbeitskopie) @@ -190,7 +190,6 @@ bios + i * page_size, page_size); } printf("\n"); - protect_jedec(bios); free(tmpbuf); return 0; Index: m29f400bt.c =================================================================== --- m29f400bt.c (Revision 777) +++ m29f400bt.c (Arbeitskopie) @@ -20,15 +20,6 @@ #include "flash.h" -void protect_m29f400bt(chipaddr bios) -{ - chip_writeb(0xAA, bios + 0xAAA); - chip_writeb(0x55, bios + 0x555); - chip_writeb(0xA0, bios + 0xAAA); - - programmer_delay(200); -} - void write_page_m29f400bt(chipaddr bios, uint8_t *src, chipaddr dst, int page_size) { @@ -194,7 +185,6 @@ write_page_m29f400bt(bios, buf + 0x7c000, bios + 0x7c000, 16 * 1024); printf("\n"); - //protect_m29f400bt (bios); return 0; } @@ -248,7 +238,6 @@ write_page_m29f400bt(bios, buf + 0x30000, bios + 0x30000, 64 * 1024); printf("\n"); - //protect_m29f400bt (bios); return 0; }

4 4

[commit] r783 - trunk
by svn＠flashrom.org 26 Nov '09

26 Nov '09

Author: hailfinger Date: 2009-11-26 15:50:52 +0100 (Thu, 26 Nov 2009) New Revision: 783 Modified: trunk/82802ab.c trunk/flash.h trunk/jedec.c trunk/m29f400bt.c trunk/sharplhf00l04.c trunk/stm50flw0x0x.c Log: This patch removes the extremely dangerous unprotect_jedec function which is not used at all within flashrom code, and renames the misleadingly named protect_jedec function to start_program_jedec. Calls to protect_jedec after flashing are removed, because a) on LPC chips, the command sent by protoct_jedec is not even in the datasheet and b) on parallel chips, the block write command issued before already contained the software protection sequence, so software protection is definitely enabled. This patch also removes two clones of protect_jedec Background: JEDEC Software Data Protection started as an optional feature, which was disabled on the first single-voltage-flash chips. The software data protection is the need to prefix a write with a magic "write enable" command, while without write protection every write access into the chip's address space modifies flash content. This magic write enable command also tells the flash chip that the programmer obviously support sending write-enable commands and turns off the "any write modifies flash content" mode. There also exist a two-command (6 writes) sequence that disables Software Data Protection completey, which should only ever be used to prepare updating with a device that can't handle software data protection. Signed-off-by: Michael Karcher <flashrom(a)mkarcher.dialup.fu-berlin.de> Acked-by: Sean Nelson <audiohacked(a)gmail.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: trunk/82802ab.c =================================================================== --- trunk/82802ab.c 2009-11-26 11:05:01 UTC (rev 782) +++ trunk/82802ab.c 2009-11-26 14:50:52 UTC (rev 783) @@ -190,7 +190,6 @@ bios + i * page_size, page_size); } printf("\n"); - protect_jedec(bios); free(tmpbuf); return 0; Modified: trunk/flash.h =================================================================== --- trunk/flash.h 2009-11-26 11:05:01 UTC (rev 782) +++ trunk/flash.h 2009-11-26 14:50:52 UTC (rev 783) @@ -647,8 +647,7 @@ uint8_t oddparity(uint8_t val); void toggle_ready_jedec(chipaddr dst); void data_polling_jedec(chipaddr dst, uint8_t data); -void unprotect_jedec(chipaddr bios); -void protect_jedec(chipaddr bios); +void start_program_jedec(chipaddr bios); int write_byte_program_jedec(chipaddr bios, uint8_t *src, chipaddr dst); int probe_jedec(struct flashchip *flash); Modified: trunk/jedec.c =================================================================== --- trunk/jedec.c 2009-11-26 11:05:01 UTC (rev 782) +++ trunk/jedec.c 2009-11-26 14:50:52 UTC (rev 783) @@ -64,25 +64,11 @@ } } -void unprotect_jedec(chipaddr bios) +void start_program_jedec(chipaddr bios) { chip_writeb(0xAA, bios + 0x5555); chip_writeb(0x55, bios + 0x2AAA); - chip_writeb(0x80, bios + 0x5555); - chip_writeb(0xAA, bios + 0x5555); - chip_writeb(0x55, bios + 0x2AAA); - chip_writeb(0x20, bios + 0x5555); - - programmer_delay(200); -} - -void protect_jedec(chipaddr bios) -{ - chip_writeb(0xAA, bios + 0x5555); - chip_writeb(0x55, bios + 0x2AAA); chip_writeb(0xA0, bios + 0x5555); - - programmer_delay(200); } int probe_jedec(struct flashchip *flash) @@ -270,9 +256,7 @@ retry: /* Issue JEDEC Data Unprotect comand */ - chip_writeb(0xAA, bios + 0x5555); - chip_writeb(0x55, bios + 0x2AAA); - chip_writeb(0xA0, bios + 0x5555); + start_program_jedec(bios); /* transfer data from source to destination */ for (i = 0; i < page_size; i++) { @@ -312,9 +296,7 @@ retry: /* Issue JEDEC Byte Program command */ - chip_writeb(0xAA, bios + 0x5555); - chip_writeb(0x55, bios + 0x2AAA); - chip_writeb(0xA0, bios + 0x5555); + start_program_jedec(bios); /* transfer data from source to destination */ chip_writeb(*src, dst); @@ -353,7 +335,6 @@ int i, failed = 0; int total_size = flash->total_size * 1024; int page_size = flash->page_size; - chipaddr bios = flash->virtual_memory; if (erase_chip_jedec(flash)) { fprintf(stderr,"ERASE FAILED!\n"); @@ -369,7 +350,6 @@ printf("\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b"); } printf("\n"); - protect_jedec(bios); return failed; } Modified: trunk/m29f400bt.c =================================================================== --- trunk/m29f400bt.c 2009-11-26 11:05:01 UTC (rev 782) +++ trunk/m29f400bt.c 2009-11-26 14:50:52 UTC (rev 783) @@ -20,15 +20,6 @@ #include "flash.h" -void protect_m29f400bt(chipaddr bios) -{ - chip_writeb(0xAA, bios + 0xAAA); - chip_writeb(0x55, bios + 0x555); - chip_writeb(0xA0, bios + 0xAAA); - - programmer_delay(200); -} - void write_page_m29f400bt(chipaddr bios, uint8_t *src, chipaddr dst, int page_size) { @@ -194,7 +185,6 @@ write_page_m29f400bt(bios, buf + 0x7c000, bios + 0x7c000, 16 * 1024); printf("\n"); - //protect_m29f400bt (bios); return 0; } @@ -248,7 +238,6 @@ write_page_m29f400bt(bios, buf + 0x30000, bios + 0x30000, 64 * 1024); printf("\n"); - //protect_m29f400bt (bios); return 0; } Modified: trunk/sharplhf00l04.c =================================================================== --- trunk/sharplhf00l04.c 2009-11-26 11:05:01 UTC (rev 782) +++ trunk/sharplhf00l04.c 2009-11-26 14:50:52 UTC (rev 783) @@ -179,7 +179,6 @@ printf("\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b"); } printf("\n"); - protect_jedec(bios); return 0; } Modified: trunk/stm50flw0x0x.c =================================================================== --- trunk/stm50flw0x0x.c 2009-11-26 11:05:01 UTC (rev 782) +++ trunk/stm50flw0x0x.c 2009-11-26 14:50:52 UTC (rev 783) @@ -31,15 +31,6 @@ #include "flash.h" #include "flashchips.h" -void protect_stm50flw0x0x(chipaddr bios) -{ - chip_writeb(0xAA, bios + 0x5555); - chip_writeb(0x55, bios + 0x2AAA); - chip_writeb(0xA0, bios + 0x5555); - - programmer_delay(200); -} - int probe_stm50flw0x0x(struct flashchip *flash) { int result = probe_jedec(flash); @@ -189,7 +180,6 @@ int i; int total_size = flash->total_size * 1024; int page_size = flash->page_size; - chipaddr bios = flash->virtual_memory; printf("Erasing page:\n"); for (i = 0; i < total_size / page_size; i++) { @@ -206,7 +196,6 @@ } } printf("\n"); - protect_stm50flw0x0x(bios); return 0; } @@ -250,7 +239,6 @@ bios + i * page_size, page_size); } printf("\n"); - protect_stm50flw0x0x(bios); free(tmpbuf); return rc;

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Verbose output of lspci, superiotool and flashrom - Intel DP55WB (unsupported)
by Adrian Glaubitz 26 Nov '09

26 Nov '09

Hi, tested an Intel DP55WB, however the chipset was not detected and therefore flashing was not possible. Please see the attached logs of lspci -nnvvvxxx, superiotool -dV and flashrom -V. Website: <http://www.intel.com/products/desktop/motherboards/DP55WB/DP55WB-overview.h…> Adrian

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[RFC] Abort early or abort late on failure?
by Carl-Daniel Hailfinger 26 Nov '09

26 Nov '09

Hi, flashrom currently doesn't have a coherent policy about failed writes. Some chip drivers abort on the first failed write, others keep going until the end. Either variant makes sense, but mixing them is suboptimal. The following policies are available: - hardcode abort early (on first error) - hardcode abort never (ignore all errors until the end) - switch behaviour based on commandline parameter. Opinions? Regards, Carl-Daniel -- Developer quote of the month: "We are juggling too many chainsaws and flaming arrows and tigers."

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Success with DFI Blood-Iron P35 T2RL
by Erno Vaurio 26 Nov '09

26 Nov '09

Hello, I was able to successfully flash my board with a new bios. There was one warning about spi_chip_erase_60 failing, this didn't affect the outcome and flash was verified. Board model: DFI Infinity Blood-Iron P35-T2RL Manual: http://img.lanparty.tw/Upload/Manual/CM/021107321.pdf Bios download link: http://img.lanparty.tw/Upload/BIOS/CM/I35RD924.zip $ sudo flashrom -w I35RD924.BIN flashrom v0.9.1-r706 No coreboot table found. Found chipset "Intel ICH9R", enabling flash write... OK. This chipset supports the following protocols: LPC,FWH,SPI. Calibrating delay loop... OK. Found chip "SST SST25VF080B" (1024 KB, SPI) at physical address 0xfff00000. Flash image seems to be a legacy BIOS. Disabling checks. Writing flash chip... Erasing flash before programming... spi_chip_erase_60 failed during command execution done. COMPLETE. Verifying flash... VERIFIED. Requested output attached as files.

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