flashrom June 2014

flashrom@flashrom.org

29 participants
115 discussions

[commit] r1817 - trunk
by repository service 01 Jun '14

01 Jun '14

Author: stefanct Date: Mon Jun 2 02:46:02 2014 New Revision: 1817 URL: http://flashrom.org/trac/flashrom/changeset/1817 Log: print_wiki.c: there is only one way to represent time. ISO 8601. Signed-off-by: Stefan Tauner <stefan.tauner(a)alumni.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner(a)alumni.tuwien.ac.at> Modified: trunk/print_wiki.c Modified: trunk/print_wiki.c ============================================================================== --- trunk/print_wiki.c Mon Jun 2 02:45:57 2014 (r1816) +++ trunk/print_wiki.c Mon Jun 2 02:46:02 2014 (r1817) @@ -31,7 +31,7 @@ <div style=\"margin-top:0.5em; padding:0.5em 0.5em 0.5em 0.5em; \ background-color:#eeeeee; text-align:left; border:1px solid #aabbcc;\">\ <small>\n\ -'''Last update:''' %s(generated by flashrom %s)<br />\n\ +'''Last update:''' %s (generated by flashrom %s)<br />\n\ The tables below are generated from flashrom's source by copying the output of '''flashrom -z'''.<br /><br />\n\ A short explanation of the cells representing the support state follows:<br />\n\ {| border=\"0\" valign=\"top\"\n\ @@ -443,8 +443,10 @@ void print_supported_wiki(void) { time_t t = time(NULL); + char buf[sizeof("1986-02-28T12:37:42Z")]; + strftime(buf, sizeof(buf), "%Y-%m-%dT%H:%M:%SZ", gmtime(&t)); - printf(wiki_header, ctime(&t), flashrom_version); + printf(wiki_header, buf, flashrom_version); print_supported_chips_wiki(2); #if CONFIG_INTERNAL == 1 print_supported_chipsets_wiki(3);

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[commit] r1816 - trunk
by repository service 01 Jun '14

01 Jun '14

Author: stefanct Date: Mon Jun 2 02:45:57 2014 New Revision: 1816 URL: http://flashrom.org/trac/flashrom/changeset/1816 Log: print_wiki.c: refine header and include a legend explaining the test state representation. Signed-off-by: Stefan Tauner <stefan.tauner(a)alumni.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner(a)alumni.tuwien.ac.at> Modified: trunk/print_wiki.c Modified: trunk/print_wiki.c ============================================================================== --- trunk/print_wiki.c Mon Jun 2 02:34:58 2014 (r1815) +++ trunk/print_wiki.c Mon Jun 2 02:45:57 2014 (r1816) @@ -29,11 +29,33 @@ static const char wiki_header[] = "= Supported devices =\n\n\ <div style=\"margin-top:0.5em; padding:0.5em 0.5em 0.5em 0.5em; \ -background-color:#eeeeee; text-align:right; border:1px solid #aabbcc;\">\ +background-color:#eeeeee; text-align:left; border:1px solid #aabbcc;\">\ <small>\n\ -Please do '''not''' edit these tables in the wiki directly, they are \ -generated by pasting '''flashrom -z''' output.<br />\ -'''Last update:''' %s(generated by flashrom %s)\n</small></div>\n"; +'''Last update:''' %s(generated by flashrom %s)<br />\n\ +The tables below are generated from flashrom's source by copying the output of '''flashrom -z'''.<br /><br />\n\ +A short explanation of the cells representing the support state follows:<br />\n\ +{| border=\"0\" valign=\"top\"\n\ +! style=\"text-align:left;\" |\n\ +! style=\"text-align:left;\" |\n\ +|-\n\ +|{{OK}}\n\ +| The feature was '''tested and should work''' in general unless there is a bug in flashrom or another component in \ +the system prohibits some functionality.\n\ +|-\n\ +|{{Dep}}\n\ +| '''Configuration-dependent'''. The feature was tested and should work in general but there are common \ +configurations that drastically limit flashrom's capabilities or make it completely stop working.\n\ +|-\n\ +|{{?3}}\n\ +| The feature is '''untested''' but believed to be working.\n\ +|-\n\ +|{{NA}}\n\ +| The feature is '''not applicable''' in this configuration (e.g. write operations on ROM chips).\n\ +|-\n\ +|{{No}}\n\ +| The feature is '''known to not work'''. Don't bother testing (nor reporting. Patches welcome! ;).\n\ +|}\n\ +</small></div>\n"; static const char th_start[] = "| valign=\"top\"|\n\n\ {| border=\"0\" style=\"font-size: smaller\" valign=\"top\"\n\

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Re: [flashrom] [PATCH 2/2] Utilize new tested states for chipsets as well.
by Carl-Daniel Hailfinger 01 Jun '14

01 Jun '14

Am 30.05.2014 05:15 schrieb Stefan Tauner: > Mark all ME-enabled Intel chipsets as DEP, alter print.c accordingly > (print_wiki.c was already prepared). > > Signed-off-by: Stefan Tauner <stefan.tauner(a)alumni.tuwien.ac.at> Thanks for your patch! Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Regards, Carl-Daniel -- http://www.hailfinger.org/

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[commit] r1815 - trunk
by repository service 01 Jun '14

01 Jun '14

Author: stefanct Date: Mon Jun 2 02:34:58 2014 New Revision: 1815 URL: http://flashrom.org/trac/flashrom/changeset/1815 Log: Utilize new tested states for chipsets as well. Mark all ME-enabled Intel chipsets as DEP, alter print.c accordingly (print_wiki.c was already prepared). And realign the chipset enable table when we are at it already. Signed-off-by: Stefan Tauner <stefan.tauner(a)alumni.tuwien.ac.at> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: trunk/chipset_enable.c trunk/print.c Modified: trunk/chipset_enable.c ============================================================================== --- trunk/chipset_enable.c Mon Jun 2 02:12:23 2014 (r1814) +++ trunk/chipset_enable.c Mon Jun 2 02:34:58 2014 (r1815) @@ -1366,60 +1366,60 @@ /* Please keep this list numerically sorted by vendor/device ID. */ const struct penable chipset_enables[] = { #if defined(__i386__) || defined(__x86_64__) - {0x1002, 0x4377, OK, "ATI", "SB400", enable_flash_sb400}, - {0x1002, 0x438d, OK, "AMD", "SB600", enable_flash_sb600}, - {0x1002, 0x439d, OK, "AMD", "SB7x0/SB8x0/SB9x0", enable_flash_sb600}, - {0x100b, 0x0510, NT, "AMD", "SC1100", enable_flash_sc1100}, - {0x1022, 0x2080, OK, "AMD", "CS5536", enable_flash_cs5536}, - {0x1022, 0x2090, OK, "AMD", "CS5536", enable_flash_cs5536}, - {0x1022, 0x3000, OK, "AMD", "Elan SC520", get_flashbase_sc520}, - {0x1022, 0x7440, OK, "AMD", "AMD-768", enable_flash_amd_768_8111}, - {0x1022, 0x7468, OK, "AMD", "AMD-8111", enable_flash_amd_768_8111}, - {0x1022, 0x780e, OK, "AMD", "FCH", enable_flash_sb600}, - {0x1039, 0x0406, NT, "SiS", "501/5101/5501", enable_flash_sis501}, - {0x1039, 0x0496, NT, "SiS", "85C496+497", enable_flash_sis85c496}, - {0x1039, 0x0530, OK, "SiS", "530", enable_flash_sis530}, - {0x1039, 0x0540, NT, "SiS", "540", enable_flash_sis540}, - {0x1039, 0x0620, NT, "SiS", "620", enable_flash_sis530}, - {0x1039, 0x0630, NT, "SiS", "630", enable_flash_sis540}, - {0x1039, 0x0635, NT, "SiS", "635", enable_flash_sis540}, - {0x1039, 0x0640, NT, "SiS", "640", enable_flash_sis540}, - {0x1039, 0x0645, NT, "SiS", "645", enable_flash_sis540}, - {0x1039, 0x0646, OK, "SiS", "645DX", enable_flash_sis540}, - {0x1039, 0x0648, OK, "SiS", "648", enable_flash_sis540}, - {0x1039, 0x0650, OK, "SiS", "650", enable_flash_sis540}, - {0x1039, 0x0651, OK, "SiS", "651", enable_flash_sis540}, - {0x1039, 0x0655, NT, "SiS", "655", enable_flash_sis540}, - {0x1039, 0x0661, OK, "SiS", "661", enable_flash_sis540}, - {0x1039, 0x0730, OK, "SiS", "730", enable_flash_sis540}, - {0x1039, 0x0733, NT, "SiS", "733", enable_flash_sis540}, - {0x1039, 0x0735, OK, "SiS", "735", enable_flash_sis540}, - {0x1039, 0x0740, NT, "SiS", "740", enable_flash_sis540}, - {0x1039, 0x0741, OK, "SiS", "741", enable_flash_sis540}, - {0x1039, 0x0745, OK, "SiS", "745", enable_flash_sis540}, - {0x1039, 0x0746, NT, "SiS", "746", enable_flash_sis540}, - {0x1039, 0x0748, NT, "SiS", "748", enable_flash_sis540}, - {0x1039, 0x0755, OK, "SiS", "755", enable_flash_sis540}, - {0x1039, 0x5511, NT, "SiS", "5511", enable_flash_sis5511}, - {0x1039, 0x5571, NT, "SiS", "5571", enable_flash_sis530}, - {0x1039, 0x5591, NT, "SiS", "5591/5592", enable_flash_sis530}, - {0x1039, 0x5596, NT, "SiS", "5596", enable_flash_sis5511}, - {0x1039, 0x5597, NT, "SiS", "5597/5598/5581/5120", enable_flash_sis530}, - {0x1039, 0x5600, NT, "SiS", "600", enable_flash_sis530}, - {0x1078, 0x0100, OK, "AMD", "CS5530(A)", enable_flash_cs5530}, - {0x10b9, 0x1533, OK, "ALi", "M1533", enable_flash_ali_m1533}, - {0x10de, 0x0030, OK, "NVIDIA", "nForce4/MCP4", enable_flash_nvidia_nforce2}, - {0x10de, 0x0050, OK, "NVIDIA", "CK804", enable_flash_ck804}, /* LPC */ - {0x10de, 0x0051, OK, "NVIDIA", "CK804", enable_flash_ck804}, /* Pro */ - {0x10de, 0x0060, OK, "NVIDIA", "NForce2", enable_flash_nvidia_nforce2}, - {0x10de, 0x00e0, OK, "NVIDIA", "NForce3", enable_flash_nvidia_nforce2}, + {0x1002, 0x4377, OK, "ATI", "SB400", enable_flash_sb400}, + {0x1002, 0x438d, OK, "AMD", "SB600", enable_flash_sb600}, + {0x1002, 0x439d, OK, "AMD", "SB7x0/SB8x0/SB9x0", enable_flash_sb600}, + {0x100b, 0x0510, NT, "AMD", "SC1100", enable_flash_sc1100}, + {0x1022, 0x2080, OK, "AMD", "CS5536", enable_flash_cs5536}, + {0x1022, 0x2090, OK, "AMD", "CS5536", enable_flash_cs5536}, + {0x1022, 0x3000, OK, "AMD", "Elan SC520", get_flashbase_sc520}, + {0x1022, 0x7440, OK, "AMD", "AMD-768", enable_flash_amd_768_8111}, + {0x1022, 0x7468, OK, "AMD", "AMD-8111", enable_flash_amd_768_8111}, + {0x1022, 0x780e, OK, "AMD", "FCH", enable_flash_sb600}, + {0x1039, 0x0406, NT, "SiS", "501/5101/5501", enable_flash_sis501}, + {0x1039, 0x0496, NT, "SiS", "85C496+497", enable_flash_sis85c496}, + {0x1039, 0x0530, OK, "SiS", "530", enable_flash_sis530}, + {0x1039, 0x0540, NT, "SiS", "540", enable_flash_sis540}, + {0x1039, 0x0620, NT, "SiS", "620", enable_flash_sis530}, + {0x1039, 0x0630, NT, "SiS", "630", enable_flash_sis540}, + {0x1039, 0x0635, NT, "SiS", "635", enable_flash_sis540}, + {0x1039, 0x0640, NT, "SiS", "640", enable_flash_sis540}, + {0x1039, 0x0645, NT, "SiS", "645", enable_flash_sis540}, + {0x1039, 0x0646, OK, "SiS", "645DX", enable_flash_sis540}, + {0x1039, 0x0648, OK, "SiS", "648", enable_flash_sis540}, + {0x1039, 0x0650, OK, "SiS", "650", enable_flash_sis540}, + {0x1039, 0x0651, OK, "SiS", "651", enable_flash_sis540}, + {0x1039, 0x0655, NT, "SiS", "655", enable_flash_sis540}, + {0x1039, 0x0661, OK, "SiS", "661", enable_flash_sis540}, + {0x1039, 0x0730, OK, "SiS", "730", enable_flash_sis540}, + {0x1039, 0x0733, NT, "SiS", "733", enable_flash_sis540}, + {0x1039, 0x0735, OK, "SiS", "735", enable_flash_sis540}, + {0x1039, 0x0740, NT, "SiS", "740", enable_flash_sis540}, + {0x1039, 0x0741, OK, "SiS", "741", enable_flash_sis540}, + {0x1039, 0x0745, OK, "SiS", "745", enable_flash_sis540}, + {0x1039, 0x0746, NT, "SiS", "746", enable_flash_sis540}, + {0x1039, 0x0748, NT, "SiS", "748", enable_flash_sis540}, + {0x1039, 0x0755, OK, "SiS", "755", enable_flash_sis540}, + {0x1039, 0x5511, NT, "SiS", "5511", enable_flash_sis5511}, + {0x1039, 0x5571, NT, "SiS", "5571", enable_flash_sis530}, + {0x1039, 0x5591, NT, "SiS", "5591/5592", enable_flash_sis530}, + {0x1039, 0x5596, NT, "SiS", "5596", enable_flash_sis5511}, + {0x1039, 0x5597, NT, "SiS", "5597/5598/5581/5120", enable_flash_sis530}, + {0x1039, 0x5600, NT, "SiS", "600", enable_flash_sis530}, + {0x1078, 0x0100, OK, "AMD", "CS5530(A)", enable_flash_cs5530}, + {0x10b9, 0x1533, OK, "ALi", "M1533", enable_flash_ali_m1533}, + {0x10de, 0x0030, OK, "NVIDIA", "nForce4/MCP4", enable_flash_nvidia_nforce2}, + {0x10de, 0x0050, OK, "NVIDIA", "CK804", enable_flash_ck804}, /* LPC */ + {0x10de, 0x0051, OK, "NVIDIA", "CK804", enable_flash_ck804}, /* Pro */ + {0x10de, 0x0060, OK, "NVIDIA", "NForce2", enable_flash_nvidia_nforce2}, + {0x10de, 0x00e0, OK, "NVIDIA", "NForce3", enable_flash_nvidia_nforce2}, /* Slave, should not be here, to fix known bug for A01. */ - {0x10de, 0x00d3, OK, "NVIDIA", "CK804", enable_flash_ck804}, - {0x10de, 0x0260, OK, "NVIDIA", "MCP51", enable_flash_ck804}, - {0x10de, 0x0261, OK, "NVIDIA", "MCP51", enable_flash_ck804}, - {0x10de, 0x0262, NT, "NVIDIA", "MCP51", enable_flash_ck804}, - {0x10de, 0x0263, NT, "NVIDIA", "MCP51", enable_flash_ck804}, - {0x10de, 0x0360, OK, "NVIDIA", "MCP55", enable_flash_mcp55}, /* M57SLI*/ + {0x10de, 0x00d3, OK, "NVIDIA", "CK804", enable_flash_ck804}, + {0x10de, 0x0260, OK, "NVIDIA", "MCP51", enable_flash_ck804}, + {0x10de, 0x0261, OK, "NVIDIA", "MCP51", enable_flash_ck804}, + {0x10de, 0x0262, NT, "NVIDIA", "MCP51", enable_flash_ck804}, + {0x10de, 0x0263, NT, "NVIDIA", "MCP51", enable_flash_ck804}, + {0x10de, 0x0360, OK, "NVIDIA", "MCP55", enable_flash_mcp55}, /* M57SLI*/ /* 10de:0361 is present in Tyan S2915 OEM systems, but not connected to * the flash chip. Instead, 10de:0364 is connected to the flash chip. * Until we have PCI device class matching or some fallback mechanism, @@ -1427,221 +1427,221 @@ * dual-MCP55 boards. */ #if 0 - {0x10de, 0x0361, NT, "NVIDIA", "MCP55", enable_flash_mcp55}, /* LPC */ + {0x10de, 0x0361, NT, "NVIDIA", "MCP55", enable_flash_mcp55}, /* LPC */ #endif - {0x10de, 0x0362, OK, "NVIDIA", "MCP55", enable_flash_mcp55}, /* LPC */ - {0x10de, 0x0363, OK, "NVIDIA", "MCP55", enable_flash_mcp55}, /* LPC */ - {0x10de, 0x0364, OK, "NVIDIA", "MCP55", enable_flash_mcp55}, /* LPC */ - {0x10de, 0x0365, OK, "NVIDIA", "MCP55", enable_flash_mcp55}, /* LPC */ - {0x10de, 0x0366, OK, "NVIDIA", "MCP55", enable_flash_mcp55}, /* LPC */ - {0x10de, 0x0367, OK, "NVIDIA", "MCP55", enable_flash_mcp55}, /* Pro */ - {0x10de, 0x03e0, OK, "NVIDIA", "MCP61", enable_flash_mcp6x_7x}, - {0x10de, 0x03e1, OK, "NVIDIA", "MCP61", enable_flash_mcp6x_7x}, - {0x10de, 0x03e3, NT, "NVIDIA", "MCP61", enable_flash_mcp6x_7x}, - {0x10de, 0x0440, NT, "NVIDIA", "MCP65", enable_flash_mcp6x_7x}, - {0x10de, 0x0441, NT, "NVIDIA", "MCP65", enable_flash_mcp6x_7x}, - {0x10de, 0x0442, NT, "NVIDIA", "MCP65", enable_flash_mcp6x_7x}, - {0x10de, 0x0443, NT, "NVIDIA", "MCP65", enable_flash_mcp6x_7x}, - {0x10de, 0x0548, OK, "NVIDIA", "MCP67", enable_flash_mcp6x_7x}, - {0x10de, 0x075c, OK, "NVIDIA", "MCP78S", enable_flash_mcp6x_7x}, - {0x10de, 0x075d, OK, "NVIDIA", "MCP78S", enable_flash_mcp6x_7x}, - {0x10de, 0x07d7, OK, "NVIDIA", "MCP73", enable_flash_mcp6x_7x}, - {0x10de, 0x0aac, OK, "NVIDIA", "MCP79", enable_flash_mcp6x_7x}, - {0x10de, 0x0aad, NT, "NVIDIA", "MCP79", enable_flash_mcp6x_7x}, - {0x10de, 0x0aae, NT, "NVIDIA", "MCP79", enable_flash_mcp6x_7x}, - {0x10de, 0x0aaf, NT, "NVIDIA", "MCP79", enable_flash_mcp6x_7x}, - {0x10de, 0x0d80, NT, "NVIDIA", "MCP89", enable_flash_mcp6x_7x}, + {0x10de, 0x0362, OK, "NVIDIA", "MCP55", enable_flash_mcp55}, /* LPC */ + {0x10de, 0x0363, OK, "NVIDIA", "MCP55", enable_flash_mcp55}, /* LPC */ + {0x10de, 0x0364, OK, "NVIDIA", "MCP55", enable_flash_mcp55}, /* LPC */ + {0x10de, 0x0365, OK, "NVIDIA", "MCP55", enable_flash_mcp55}, /* LPC */ + {0x10de, 0x0366, OK, "NVIDIA", "MCP55", enable_flash_mcp55}, /* LPC */ + {0x10de, 0x0367, OK, "NVIDIA", "MCP55", enable_flash_mcp55}, /* Pro */ + {0x10de, 0x03e0, OK, "NVIDIA", "MCP61", enable_flash_mcp6x_7x}, + {0x10de, 0x03e1, OK, "NVIDIA", "MCP61", enable_flash_mcp6x_7x}, + {0x10de, 0x03e3, NT, "NVIDIA", "MCP61", enable_flash_mcp6x_7x}, + {0x10de, 0x0440, NT, "NVIDIA", "MCP65", enable_flash_mcp6x_7x}, + {0x10de, 0x0441, NT, "NVIDIA", "MCP65", enable_flash_mcp6x_7x}, + {0x10de, 0x0442, NT, "NVIDIA", "MCP65", enable_flash_mcp6x_7x}, + {0x10de, 0x0443, NT, "NVIDIA", "MCP65", enable_flash_mcp6x_7x}, + {0x10de, 0x0548, OK, "NVIDIA", "MCP67", enable_flash_mcp6x_7x}, + {0x10de, 0x075c, OK, "NVIDIA", "MCP78S", enable_flash_mcp6x_7x}, + {0x10de, 0x075d, OK, "NVIDIA", "MCP78S", enable_flash_mcp6x_7x}, + {0x10de, 0x07d7, OK, "NVIDIA", "MCP73", enable_flash_mcp6x_7x}, + {0x10de, 0x0aac, OK, "NVIDIA", "MCP79", enable_flash_mcp6x_7x}, + {0x10de, 0x0aad, NT, "NVIDIA", "MCP79", enable_flash_mcp6x_7x}, + {0x10de, 0x0aae, NT, "NVIDIA", "MCP79", enable_flash_mcp6x_7x}, + {0x10de, 0x0aaf, NT, "NVIDIA", "MCP79", enable_flash_mcp6x_7x}, + {0x10de, 0x0d80, NT, "NVIDIA", "MCP89", enable_flash_mcp6x_7x}, /* VIA northbridges */ - {0x1106, 0x0585, NT, "VIA", "VT82C585VPX", via_no_byte_merge}, - {0x1106, 0x0595, NT, "VIA", "VT82C595", via_no_byte_merge}, - {0x1106, 0x0597, NT, "VIA", "VT82C597", via_no_byte_merge}, - {0x1106, 0x0601, NT, "VIA", "VT8601/VT8601A", via_no_byte_merge}, - {0x1106, 0x0691, OK, "VIA", "VT82C69x", via_no_byte_merge}, - {0x1106, 0x8601, NT, "VIA", "VT8601T", via_no_byte_merge}, + {0x1106, 0x0585, NT, "VIA", "VT82C585VPX", via_no_byte_merge}, + {0x1106, 0x0595, NT, "VIA", "VT82C595", via_no_byte_merge}, + {0x1106, 0x0597, NT, "VIA", "VT82C597", via_no_byte_merge}, + {0x1106, 0x0601, NT, "VIA", "VT8601/VT8601A", via_no_byte_merge}, + {0x1106, 0x0691, OK, "VIA", "VT82C69x", via_no_byte_merge}, + {0x1106, 0x8601, NT, "VIA", "VT8601T", via_no_byte_merge}, /* VIA southbridges */ - {0x1106, 0x0586, OK, "VIA", "VT82C586A/B", enable_flash_vt82c586}, - {0x1106, 0x0596, OK, "VIA", "VT82C596", enable_flash_vt82c596}, - {0x1106, 0x0686, OK, "VIA", "VT82C686A/B", enable_flash_vt82c596}, - {0x1106, 0x3074, OK, "VIA", "VT8233", enable_flash_vt823x}, - {0x1106, 0x3147, OK, "VIA", "VT8233A", enable_flash_vt823x}, - {0x1106, 0x3177, OK, "VIA", "VT8235", enable_flash_vt823x}, - {0x1106, 0x3227, OK, "VIA", "VT8237(R)", enable_flash_vt823x}, - {0x1106, 0x3337, OK, "VIA", "VT8237A", enable_flash_vt823x}, - {0x1106, 0x3372, OK, "VIA", "VT8237S", enable_flash_vt8237s_spi}, - {0x1106, 0x8231, NT, "VIA", "VT8231", enable_flash_vt823x}, - {0x1106, 0x8324, OK, "VIA", "CX700", enable_flash_vt823x}, - {0x1106, 0x8353, NT, "VIA", "VX800/VX820", enable_flash_vt_vx}, - {0x1106, 0x8409, NT, "VIA", "VX855/VX875", enable_flash_vt_vx}, - {0x1106, 0x8410, NT, "VIA", "VX900", enable_flash_vt_vx}, - {0x1166, 0x0200, OK, "Broadcom", "OSB4", enable_flash_osb4}, - {0x1166, 0x0205, OK, "Broadcom", "HT-1000", enable_flash_ht1000}, - {0x17f3, 0x6030, OK, "RDC", "R8610/R3210", enable_flash_rdc_r8610}, - {0x8086, 0x0c60, NT, "Intel", "S12x0", enable_flash_s12x0}, - {0x8086, 0x122e, OK, "Intel", "PIIX", enable_flash_piix4}, - {0x8086, 0x1234, NT, "Intel", "MPIIX", enable_flash_piix4}, - {0x8086, 0x1c44, OK, "Intel", "Z68", enable_flash_pch6}, - {0x8086, 0x1c46, OK, "Intel", "P67", enable_flash_pch6}, - {0x8086, 0x1c47, NT, "Intel", "UM67", enable_flash_pch6}, - {0x8086, 0x1c49, NT, "Intel", "HM65", enable_flash_pch6}, - {0x8086, 0x1c4a, OK, "Intel", "H67", enable_flash_pch6}, - {0x8086, 0x1c4b, NT, "Intel", "HM67", enable_flash_pch6}, - {0x8086, 0x1c4c, NT, "Intel", "Q65", enable_flash_pch6}, - {0x8086, 0x1c4d, NT, "Intel", "QS67", enable_flash_pch6}, - {0x8086, 0x1c4e, NT, "Intel", "Q67", enable_flash_pch6}, - {0x8086, 0x1c4f, OK, "Intel", "QM67", enable_flash_pch6}, - {0x8086, 0x1c50, NT, "Intel", "B65", enable_flash_pch6}, - {0x8086, 0x1c52, NT, "Intel", "C202", enable_flash_pch6}, - {0x8086, 0x1c54, OK, "Intel", "C204", enable_flash_pch6}, - {0x8086, 0x1c56, NT, "Intel", "C206", enable_flash_pch6}, - {0x8086, 0x1c5c, OK, "Intel", "H61", enable_flash_pch6}, - {0x8086, 0x1d40, OK, "Intel", "C60x/X79", enable_flash_pch6}, - {0x8086, 0x1d41, OK, "Intel", "C60x/X79", enable_flash_pch6}, - {0x8086, 0x1e44, OK, "Intel", "Z77", enable_flash_pch7}, - {0x8086, 0x1e46, NT, "Intel", "Z75", enable_flash_pch7}, - {0x8086, 0x1e47, NT, "Intel", "Q77", enable_flash_pch7}, - {0x8086, 0x1e48, NT, "Intel", "Q75", enable_flash_pch7}, - {0x8086, 0x1e49, OK, "Intel", "B75", enable_flash_pch7}, - {0x8086, 0x1e4a, OK, "Intel", "H77", enable_flash_pch7}, - {0x8086, 0x1e53, NT, "Intel", "C216", enable_flash_pch7}, - {0x8086, 0x1e55, OK, "Intel", "QM77", enable_flash_pch7}, - {0x8086, 0x1e56, NT, "Intel", "QS77", enable_flash_pch7}, - {0x8086, 0x1e57, OK, "Intel", "HM77", enable_flash_pch7}, - {0x8086, 0x1e58, NT, "Intel", "UM77", enable_flash_pch7}, - {0x8086, 0x1e59, NT, "Intel", "HM76", enable_flash_pch7}, - {0x8086, 0x1e5d, NT, "Intel", "HM75", enable_flash_pch7}, - {0x8086, 0x1e5e, NT, "Intel", "HM70", enable_flash_pch7}, - {0x8086, 0x1e5f, OK, "Intel", "NM70", enable_flash_pch7}, - {0x8086, 0x2310, NT, "Intel", "DH89xxCC", enable_flash_pch7}, - {0x8086, 0x2390, NT, "Intel", "Coleto Creek", enable_flash_pch7}, - {0x8086, 0x2410, OK, "Intel", "ICH", enable_flash_ich0}, - {0x8086, 0x2420, OK, "Intel", "ICH0", enable_flash_ich0}, - {0x8086, 0x2440, OK, "Intel", "ICH2", enable_flash_ich2345}, - {0x8086, 0x244c, OK, "Intel", "ICH2-M", enable_flash_ich2345}, - {0x8086, 0x2450, NT, "Intel", "C-ICH", enable_flash_ich2345}, - {0x8086, 0x2480, OK, "Intel", "ICH3-S", enable_flash_ich2345}, - {0x8086, 0x248c, OK, "Intel", "ICH3-M", enable_flash_ich2345}, - {0x8086, 0x24c0, OK, "Intel", "ICH4/ICH4-L", enable_flash_ich2345}, - {0x8086, 0x24cc, OK, "Intel", "ICH4-M", enable_flash_ich2345}, - {0x8086, 0x24d0, OK, "Intel", "ICH5/ICH5R", enable_flash_ich2345}, - {0x8086, 0x25a1, OK, "Intel", "6300ESB", enable_flash_ich2345}, - {0x8086, 0x2640, OK, "Intel", "ICH6/ICH6R", enable_flash_ich6}, - {0x8086, 0x2641, OK, "Intel", "ICH6-M", enable_flash_ich6}, - {0x8086, 0x2642, NT, "Intel", "ICH6W/ICH6RW", enable_flash_ich6}, - {0x8086, 0x2670, OK, "Intel", "631xESB/632xESB/3100", enable_flash_ich6}, - {0x8086, 0x27b0, OK, "Intel", "ICH7DH", enable_flash_ich7}, - {0x8086, 0x27b8, OK, "Intel", "ICH7/ICH7R", enable_flash_ich7}, - {0x8086, 0x27b9, OK, "Intel", "ICH7M", enable_flash_ich7}, - {0x8086, 0x27bc, OK, "Intel", "NM10", enable_flash_ich7}, - {0x8086, 0x27bd, OK, "Intel", "ICH7MDH", enable_flash_ich7}, - {0x8086, 0x2810, OK, "Intel", "ICH8/ICH8R", enable_flash_ich8}, - {0x8086, 0x2811, OK, "Intel", "ICH8M-E", enable_flash_ich8}, - {0x8086, 0x2812, OK, "Intel", "ICH8DH", enable_flash_ich8}, - {0x8086, 0x2814, OK, "Intel", "ICH8DO", enable_flash_ich8}, - {0x8086, 0x2815, OK, "Intel", "ICH8M", enable_flash_ich8}, - {0x8086, 0x2910, OK, "Intel", "ICH9 Engineering Sample", enable_flash_ich9}, - {0x8086, 0x2912, OK, "Intel", "ICH9DH", enable_flash_ich9}, - {0x8086, 0x2914, OK, "Intel", "ICH9DO", enable_flash_ich9}, - {0x8086, 0x2916, OK, "Intel", "ICH9R", enable_flash_ich9}, - {0x8086, 0x2917, OK, "Intel", "ICH9M-E", enable_flash_ich9}, - {0x8086, 0x2918, OK, "Intel", "ICH9", enable_flash_ich9}, - {0x8086, 0x2919, OK, "Intel", "ICH9M", enable_flash_ich9}, - {0x8086, 0x3a10, NT, "Intel", "ICH10R Engineering Sample", enable_flash_ich10}, - {0x8086, 0x3a14, OK, "Intel", "ICH10DO", enable_flash_ich10}, - {0x8086, 0x3a16, OK, "Intel", "ICH10R", enable_flash_ich10}, - {0x8086, 0x3a18, OK, "Intel", "ICH10", enable_flash_ich10}, - {0x8086, 0x3a1a, OK, "Intel", "ICH10D", enable_flash_ich10}, - {0x8086, 0x3a1e, NT, "Intel", "ICH10 Engineering Sample", enable_flash_ich10}, - {0x8086, 0x3b00, NT, "Intel", "3400 Desktop", enable_flash_pch5}, - {0x8086, 0x3b01, NT, "Intel", "3400 Mobile", enable_flash_pch5}, - {0x8086, 0x3b02, NT, "Intel", "P55", enable_flash_pch5}, - {0x8086, 0x3b03, NT, "Intel", "PM55", enable_flash_pch5}, - {0x8086, 0x3b06, OK, "Intel", "H55", enable_flash_pch5}, - {0x8086, 0x3b07, OK, "Intel", "QM57", enable_flash_pch5}, - {0x8086, 0x3b08, NT, "Intel", "H57", enable_flash_pch5}, - {0x8086, 0x3b09, NT, "Intel", "HM55", enable_flash_pch5}, - {0x8086, 0x3b0a, NT, "Intel", "Q57", enable_flash_pch5}, - {0x8086, 0x3b0b, NT, "Intel", "HM57", enable_flash_pch5}, - {0x8086, 0x3b0d, NT, "Intel", "3400 Mobile SFF", enable_flash_pch5}, - {0x8086, 0x3b0e, NT, "Intel", "B55", enable_flash_pch5}, - {0x8086, 0x3b0f, OK, "Intel", "QS57", enable_flash_pch5}, - {0x8086, 0x3b12, NT, "Intel", "3400", enable_flash_pch5}, - {0x8086, 0x3b14, OK, "Intel", "3420", enable_flash_pch5}, - {0x8086, 0x3b16, NT, "Intel", "3450", enable_flash_pch5}, - {0x8086, 0x3b1e, NT, "Intel", "B55", enable_flash_pch5}, - {0x8086, 0x5031, OK, "Intel", "EP80579", enable_flash_ich7}, - {0x8086, 0x7000, OK, "Intel", "PIIX3", enable_flash_piix4}, - {0x8086, 0x7110, OK, "Intel", "PIIX4/4E/4M", enable_flash_piix4}, - {0x8086, 0x7198, OK, "Intel", "440MX", enable_flash_piix4}, - {0x8086, 0x8119, OK, "Intel", "SCH Poulsbo", enable_flash_poulsbo}, - {0x8086, 0x8186, OK, "Intel", "Atom E6xx(T)/Tunnel Creek", enable_flash_tunnelcreek}, - {0x8086, 0x8c40, NT, "Intel", "Lynx Point", enable_flash_pch8}, - {0x8086, 0x8c41, NT, "Intel", "Lynx Point Mobile Engineering Sample", enable_flash_pch8}, - {0x8086, 0x8c42, NT, "Intel", "Lynx Point Desktop Engineering Sample", enable_flash_pch8}, - {0x8086, 0x8c43, NT, "Intel", "Lynx Point", enable_flash_pch8}, - {0x8086, 0x8c44, OK, "Intel", "Z87", enable_flash_pch8}, - {0x8086, 0x8c45, NT, "Intel", "Lynx Point", enable_flash_pch8}, - {0x8086, 0x8c46, NT, "Intel", "Z85", enable_flash_pch8}, - {0x8086, 0x8c47, NT, "Intel", "Lynx Point", enable_flash_pch8}, - {0x8086, 0x8c48, NT, "Intel", "Lynx Point", enable_flash_pch8}, - {0x8086, 0x8c49, NT, "Intel", "HM86", enable_flash_pch8}, - {0x8086, 0x8c4a, OK, "Intel", "H87", enable_flash_pch8}, - {0x8086, 0x8c4b, OK, "Intel", "HM87", enable_flash_pch8}, - {0x8086, 0x8c4c, NT, "Intel", "Q85", enable_flash_pch8}, - {0x8086, 0x8c4d, NT, "Intel", "Lynx Point", enable_flash_pch8}, - {0x8086, 0x8c4e, NT, "Intel", "Q87", enable_flash_pch8}, - {0x8086, 0x8c4f, NT, "Intel", "QM87", enable_flash_pch8}, - {0x8086, 0x8c50, OK, "Intel", "B85", enable_flash_pch8}, - {0x8086, 0x8c51, NT, "Intel", "Lynx Point", enable_flash_pch8}, - {0x8086, 0x8c52, NT, "Intel", "C222", enable_flash_pch8}, - {0x8086, 0x8c53, NT, "Intel", "Lynx Point", enable_flash_pch8}, - {0x8086, 0x8c54, NT, "Intel", "C224", enable_flash_pch8}, - {0x8086, 0x8c55, NT, "Intel", "Lynx Point", enable_flash_pch8}, - {0x8086, 0x8c56, NT, "Intel", "C226", enable_flash_pch8}, - {0x8086, 0x8c57, NT, "Intel", "Lynx Point", enable_flash_pch8}, - {0x8086, 0x8c58, NT, "Intel", "Lynx Point", enable_flash_pch8}, - {0x8086, 0x8c59, NT, "Intel", "Lynx Point", enable_flash_pch8}, - {0x8086, 0x8c5a, NT, "Intel", "Lynx Point", enable_flash_pch8}, - {0x8086, 0x8c5b, NT, "Intel", "Lynx Point", enable_flash_pch8}, - {0x8086, 0x8c5c, NT, "Intel", "H81", enable_flash_pch8}, - {0x8086, 0x8c5d, NT, "Intel", "Lynx Point", enable_flash_pch8}, - {0x8086, 0x8c5e, NT, "Intel", "Lynx Point", enable_flash_pch8}, - {0x8086, 0x8c5f, NT, "Intel", "Lynx Point", enable_flash_pch8}, - {0x8086, 0x9c41, NT, "Intel", "Lynx Point LP Engineering Sample", enable_flash_pch8_lp}, - {0x8086, 0x9c43, NT, "Intel", "Lynx Point LP Premium", enable_flash_pch8_lp}, - {0x8086, 0x9c45, NT, "Intel", "Lynx Point LP Mainstream", enable_flash_pch8_lp}, - {0x8086, 0x9c47, NT, "Intel", "Lynx Point LP Value", enable_flash_pch8_lp}, - {0x8086, 0x8d40, NT, "Intel", "Wellsburg", enable_flash_pch8_wb}, - {0x8086, 0x8d41, NT, "Intel", "Wellsburg", enable_flash_pch8_wb}, - {0x8086, 0x8d42, NT, "Intel", "Wellsburg", enable_flash_pch8_wb}, - {0x8086, 0x8d43, NT, "Intel", "Wellsburg", enable_flash_pch8_wb}, - {0x8086, 0x8d44, NT, "Intel", "Wellsburg", enable_flash_pch8_wb}, - {0x8086, 0x8d45, NT, "Intel", "Wellsburg", enable_flash_pch8_wb}, - {0x8086, 0x8d46, NT, "Intel", "Wellsburg", enable_flash_pch8_wb}, - {0x8086, 0x8d47, NT, "Intel", "Wellsburg", enable_flash_pch8_wb}, - {0x8086, 0x8d48, NT, "Intel", "Wellsburg", enable_flash_pch8_wb}, - {0x8086, 0x8d49, NT, "Intel", "Wellsburg", enable_flash_pch8_wb}, - {0x8086, 0x8d4a, NT, "Intel", "Wellsburg", enable_flash_pch8_wb}, - {0x8086, 0x8d4b, NT, "Intel", "Wellsburg", enable_flash_pch8_wb}, - {0x8086, 0x8d4c, NT, "Intel", "Wellsburg", enable_flash_pch8_wb}, - {0x8086, 0x8d4d, NT, "Intel", "Wellsburg", enable_flash_pch8_wb}, - {0x8086, 0x8d4e, NT, "Intel", "Wellsburg", enable_flash_pch8_wb}, - {0x8086, 0x8d4f, NT, "Intel", "Wellsburg", enable_flash_pch8_wb}, - {0x8086, 0x8d50, NT, "Intel", "Wellsburg", enable_flash_pch8_wb}, - {0x8086, 0x8d51, NT, "Intel", "Wellsburg", enable_flash_pch8_wb}, - {0x8086, 0x8d52, NT, "Intel", "Wellsburg", enable_flash_pch8_wb}, - {0x8086, 0x8d53, NT, "Intel", "Wellsburg", enable_flash_pch8_wb}, - {0x8086, 0x8d54, NT, "Intel", "Wellsburg", enable_flash_pch8_wb}, - {0x8086, 0x8d55, NT, "Intel", "Wellsburg", enable_flash_pch8_wb}, - {0x8086, 0x8d56, NT, "Intel", "Wellsburg", enable_flash_pch8_wb}, - {0x8086, 0x8d57, NT, "Intel", "Wellsburg", enable_flash_pch8_wb}, - {0x8086, 0x8d58, NT, "Intel", "Wellsburg", enable_flash_pch8_wb}, - {0x8086, 0x8d59, NT, "Intel", "Wellsburg", enable_flash_pch8_wb}, - {0x8086, 0x8d5a, NT, "Intel", "Wellsburg", enable_flash_pch8_wb}, - {0x8086, 0x8d5b, NT, "Intel", "Wellsburg", enable_flash_pch8_wb}, - {0x8086, 0x8d5c, NT, "Intel", "Wellsburg", enable_flash_pch8_wb}, - {0x8086, 0x8d5d, NT, "Intel", "Wellsburg", enable_flash_pch8_wb}, - {0x8086, 0x8d5e, NT, "Intel", "Wellsburg", enable_flash_pch8_wb}, - {0x8086, 0x8d5f, NT, "Intel", "Wellsburg", enable_flash_pch8_wb}, + {0x1106, 0x0586, OK, "VIA", "VT82C586A/B", enable_flash_vt82c586}, + {0x1106, 0x0596, OK, "VIA", "VT82C596", enable_flash_vt82c596}, + {0x1106, 0x0686, OK, "VIA", "VT82C686A/B", enable_flash_vt82c596}, + {0x1106, 0x3074, OK, "VIA", "VT8233", enable_flash_vt823x}, + {0x1106, 0x3147, OK, "VIA", "VT8233A", enable_flash_vt823x}, + {0x1106, 0x3177, OK, "VIA", "VT8235", enable_flash_vt823x}, + {0x1106, 0x3227, OK, "VIA", "VT8237(R)", enable_flash_vt823x}, + {0x1106, 0x3337, OK, "VIA", "VT8237A", enable_flash_vt823x}, + {0x1106, 0x3372, OK, "VIA", "VT8237S", enable_flash_vt8237s_spi}, + {0x1106, 0x8231, NT, "VIA", "VT8231", enable_flash_vt823x}, + {0x1106, 0x8324, OK, "VIA", "CX700", enable_flash_vt823x}, + {0x1106, 0x8353, NT, "VIA", "VX800/VX820", enable_flash_vt_vx}, + {0x1106, 0x8409, NT, "VIA", "VX855/VX875", enable_flash_vt_vx}, + {0x1106, 0x8410, NT, "VIA", "VX900", enable_flash_vt_vx}, + {0x1166, 0x0200, OK, "Broadcom", "OSB4", enable_flash_osb4}, + {0x1166, 0x0205, OK, "Broadcom", "HT-1000", enable_flash_ht1000}, + {0x17f3, 0x6030, OK, "RDC", "R8610/R3210", enable_flash_rdc_r8610}, + {0x8086, 0x0c60, NT, "Intel", "S12x0", enable_flash_s12x0}, + {0x8086, 0x122e, OK, "Intel", "PIIX", enable_flash_piix4}, + {0x8086, 0x1234, NT, "Intel", "MPIIX", enable_flash_piix4}, + {0x8086, 0x1c44, DEP, "Intel", "Z68", enable_flash_pch6}, + {0x8086, 0x1c46, DEP, "Intel", "P67", enable_flash_pch6}, + {0x8086, 0x1c47, NT, "Intel", "UM67", enable_flash_pch6}, + {0x8086, 0x1c49, NT, "Intel", "HM65", enable_flash_pch6}, + {0x8086, 0x1c4a, DEP, "Intel", "H67", enable_flash_pch6}, + {0x8086, 0x1c4b, NT, "Intel", "HM67", enable_flash_pch6}, + {0x8086, 0x1c4c, NT, "Intel", "Q65", enable_flash_pch6}, + {0x8086, 0x1c4d, NT, "Intel", "QS67", enable_flash_pch6}, + {0x8086, 0x1c4e, NT, "Intel", "Q67", enable_flash_pch6}, + {0x8086, 0x1c4f, DEP, "Intel", "QM67", enable_flash_pch6}, + {0x8086, 0x1c50, NT, "Intel", "B65", enable_flash_pch6}, + {0x8086, 0x1c52, NT, "Intel", "C202", enable_flash_pch6}, + {0x8086, 0x1c54, DEP, "Intel", "C204", enable_flash_pch6}, + {0x8086, 0x1c56, NT, "Intel", "C206", enable_flash_pch6}, + {0x8086, 0x1c5c, DEP, "Intel", "H61", enable_flash_pch6}, + {0x8086, 0x1d40, DEP, "Intel", "C60x/X79", enable_flash_pch6}, + {0x8086, 0x1d41, DEP, "Intel", "C60x/X79", enable_flash_pch6}, + {0x8086, 0x1e44, DEP, "Intel", "Z77", enable_flash_pch7}, + {0x8086, 0x1e46, NT, "Intel", "Z75", enable_flash_pch7}, + {0x8086, 0x1e47, NT, "Intel", "Q77", enable_flash_pch7}, + {0x8086, 0x1e48, NT, "Intel", "Q75", enable_flash_pch7}, + {0x8086, 0x1e49, DEP, "Intel", "B75", enable_flash_pch7}, + {0x8086, 0x1e4a, DEP, "Intel", "H77", enable_flash_pch7}, + {0x8086, 0x1e53, NT, "Intel", "C216", enable_flash_pch7}, + {0x8086, 0x1e55, DEP, "Intel", "QM77", enable_flash_pch7}, + {0x8086, 0x1e56, NT, "Intel", "QS77", enable_flash_pch7}, + {0x8086, 0x1e57, DEP, "Intel", "HM77", enable_flash_pch7}, + {0x8086, 0x1e58, NT, "Intel", "UM77", enable_flash_pch7}, + {0x8086, 0x1e59, NT, "Intel", "HM76", enable_flash_pch7}, + {0x8086, 0x1e5d, NT, "Intel", "HM75", enable_flash_pch7}, + {0x8086, 0x1e5e, NT, "Intel", "HM70", enable_flash_pch7}, + {0x8086, 0x1e5f, DEP, "Intel", "NM70", enable_flash_pch7}, + {0x8086, 0x2310, NT, "Intel", "DH89xxCC", enable_flash_pch7}, + {0x8086, 0x2390, NT, "Intel", "Coleto Creek", enable_flash_pch7}, + {0x8086, 0x2410, OK, "Intel", "ICH", enable_flash_ich0}, + {0x8086, 0x2420, OK, "Intel", "ICH0", enable_flash_ich0}, + {0x8086, 0x2440, OK, "Intel", "ICH2", enable_flash_ich2345}, + {0x8086, 0x244c, OK, "Intel", "ICH2-M", enable_flash_ich2345}, + {0x8086, 0x2450, NT, "Intel", "C-ICH", enable_flash_ich2345}, + {0x8086, 0x2480, OK, "Intel", "ICH3-S", enable_flash_ich2345}, + {0x8086, 0x248c, OK, "Intel", "ICH3-M", enable_flash_ich2345}, + {0x8086, 0x24c0, OK, "Intel", "ICH4/ICH4-L", enable_flash_ich2345}, + {0x8086, 0x24cc, OK, "Intel", "ICH4-M", enable_flash_ich2345}, + {0x8086, 0x24d0, OK, "Intel", "ICH5/ICH5R", enable_flash_ich2345}, + {0x8086, 0x25a1, OK, "Intel", "6300ESB", enable_flash_ich2345}, + {0x8086, 0x2640, OK, "Intel", "ICH6/ICH6R", enable_flash_ich6}, + {0x8086, 0x2641, OK, "Intel", "ICH6-M", enable_flash_ich6}, + {0x8086, 0x2642, NT, "Intel", "ICH6W/ICH6RW", enable_flash_ich6}, + {0x8086, 0x2670, OK, "Intel", "631xESB/632xESB/3100", enable_flash_ich6}, + {0x8086, 0x27b0, OK, "Intel", "ICH7DH", enable_flash_ich7}, + {0x8086, 0x27b8, OK, "Intel", "ICH7/ICH7R", enable_flash_ich7}, + {0x8086, 0x27b9, OK, "Intel", "ICH7M", enable_flash_ich7}, + {0x8086, 0x27bc, OK, "Intel", "NM10", enable_flash_ich7}, + {0x8086, 0x27bd, OK, "Intel", "ICH7MDH", enable_flash_ich7}, + {0x8086, 0x2810, DEP, "Intel", "ICH8/ICH8R", enable_flash_ich8}, + {0x8086, 0x2811, DEP, "Intel", "ICH8M-E", enable_flash_ich8}, + {0x8086, 0x2812, DEP, "Intel", "ICH8DH", enable_flash_ich8}, + {0x8086, 0x2814, DEP, "Intel", "ICH8DO", enable_flash_ich8}, + {0x8086, 0x2815, DEP, "Intel", "ICH8M", enable_flash_ich8}, + {0x8086, 0x2910, DEP, "Intel", "ICH9 Eng. Sample", enable_flash_ich9}, + {0x8086, 0x2912, DEP, "Intel", "ICH9DH", enable_flash_ich9}, + {0x8086, 0x2914, DEP, "Intel", "ICH9DO", enable_flash_ich9}, + {0x8086, 0x2916, DEP, "Intel", "ICH9R", enable_flash_ich9}, + {0x8086, 0x2917, DEP, "Intel", "ICH9M-E", enable_flash_ich9}, + {0x8086, 0x2918, DEP, "Intel", "ICH9", enable_flash_ich9}, + {0x8086, 0x2919, DEP, "Intel", "ICH9M", enable_flash_ich9}, + {0x8086, 0x3a10, NT, "Intel", "ICH10R Eng. Sample", enable_flash_ich10}, + {0x8086, 0x3a14, DEP, "Intel", "ICH10DO", enable_flash_ich10}, + {0x8086, 0x3a16, DEP, "Intel", "ICH10R", enable_flash_ich10}, + {0x8086, 0x3a18, DEP, "Intel", "ICH10", enable_flash_ich10}, + {0x8086, 0x3a1a, DEP, "Intel", "ICH10D", enable_flash_ich10}, + {0x8086, 0x3a1e, NT, "Intel", "ICH10 Eng. Sample", enable_flash_ich10}, + {0x8086, 0x3b00, NT, "Intel", "3400 Desktop", enable_flash_pch5}, + {0x8086, 0x3b01, NT, "Intel", "3400 Mobile", enable_flash_pch5}, + {0x8086, 0x3b02, NT, "Intel", "P55", enable_flash_pch5}, + {0x8086, 0x3b03, NT, "Intel", "PM55", enable_flash_pch5}, + {0x8086, 0x3b06, DEP, "Intel", "H55", enable_flash_pch5}, + {0x8086, 0x3b07, DEP, "Intel", "QM57", enable_flash_pch5}, + {0x8086, 0x3b08, NT, "Intel", "H57", enable_flash_pch5}, + {0x8086, 0x3b09, NT, "Intel", "HM55", enable_flash_pch5}, + {0x8086, 0x3b0a, NT, "Intel", "Q57", enable_flash_pch5}, + {0x8086, 0x3b0b, NT, "Intel", "HM57", enable_flash_pch5}, + {0x8086, 0x3b0d, NT, "Intel", "3400 Mobile SFF", enable_flash_pch5}, + {0x8086, 0x3b0e, NT, "Intel", "B55", enable_flash_pch5}, + {0x8086, 0x3b0f, DEP, "Intel", "QS57", enable_flash_pch5}, + {0x8086, 0x3b12, NT, "Intel", "3400", enable_flash_pch5}, + {0x8086, 0x3b14, DEP, "Intel", "3420", enable_flash_pch5}, + {0x8086, 0x3b16, NT, "Intel", "3450", enable_flash_pch5}, + {0x8086, 0x3b1e, NT, "Intel", "B55", enable_flash_pch5}, + {0x8086, 0x5031, OK, "Intel", "EP80579", enable_flash_ich7}, + {0x8086, 0x7000, OK, "Intel", "PIIX3", enable_flash_piix4}, + {0x8086, 0x7110, OK, "Intel", "PIIX4/4E/4M", enable_flash_piix4}, + {0x8086, 0x7198, OK, "Intel", "440MX", enable_flash_piix4}, + {0x8086, 0x8119, OK, "Intel", "SCH Poulsbo", enable_flash_poulsbo}, + {0x8086, 0x8186, OK, "Intel", "Atom E6xx(T)/Tunnel Creek", enable_flash_tunnelcreek}, + {0x8086, 0x8c40, NT, "Intel", "Lynx Point", enable_flash_pch8}, + {0x8086, 0x8c41, NT, "Intel", "Lynx Point Mobile Eng. Sample", enable_flash_pch8}, + {0x8086, 0x8c42, NT, "Intel", "Lynx Point Desktop Eng. Sample",enable_flash_pch8}, + {0x8086, 0x8c43, NT, "Intel", "Lynx Point", enable_flash_pch8}, + {0x8086, 0x8c44, DEP, "Intel", "Z87", enable_flash_pch8}, + {0x8086, 0x8c45, NT, "Intel", "Lynx Point", enable_flash_pch8}, + {0x8086, 0x8c46, NT, "Intel", "Z85", enable_flash_pch8}, + {0x8086, 0x8c47, NT, "Intel", "Lynx Point", enable_flash_pch8}, + {0x8086, 0x8c48, NT, "Intel", "Lynx Point", enable_flash_pch8}, + {0x8086, 0x8c49, NT, "Intel", "HM86", enable_flash_pch8}, + {0x8086, 0x8c4a, DEP, "Intel", "H87", enable_flash_pch8}, + {0x8086, 0x8c4b, DEP, "Intel", "HM87", enable_flash_pch8}, + {0x8086, 0x8c4c, NT, "Intel", "Q85", enable_flash_pch8}, + {0x8086, 0x8c4d, NT, "Intel", "Lynx Point", enable_flash_pch8}, + {0x8086, 0x8c4e, NT, "Intel", "Q87", enable_flash_pch8}, + {0x8086, 0x8c4f, NT, "Intel", "QM87", enable_flash_pch8}, + {0x8086, 0x8c50, DEP, "Intel", "B85", enable_flash_pch8}, + {0x8086, 0x8c51, NT, "Intel", "Lynx Point", enable_flash_pch8}, + {0x8086, 0x8c52, NT, "Intel", "C222", enable_flash_pch8}, + {0x8086, 0x8c53, NT, "Intel", "Lynx Point", enable_flash_pch8}, + {0x8086, 0x8c54, NT, "Intel", "C224", enable_flash_pch8}, + {0x8086, 0x8c55, NT, "Intel", "Lynx Point", enable_flash_pch8}, + {0x8086, 0x8c56, NT, "Intel", "C226", enable_flash_pch8}, + {0x8086, 0x8c57, NT, "Intel", "Lynx Point", enable_flash_pch8}, + {0x8086, 0x8c58, NT, "Intel", "Lynx Point", enable_flash_pch8}, + {0x8086, 0x8c59, NT, "Intel", "Lynx Point", enable_flash_pch8}, + {0x8086, 0x8c5a, NT, "Intel", "Lynx Point", enable_flash_pch8}, + {0x8086, 0x8c5b, NT, "Intel", "Lynx Point", enable_flash_pch8}, + {0x8086, 0x8c5c, NT, "Intel", "H81", enable_flash_pch8}, + {0x8086, 0x8c5d, NT, "Intel", "Lynx Point", enable_flash_pch8}, + {0x8086, 0x8c5e, NT, "Intel", "Lynx Point", enable_flash_pch8}, + {0x8086, 0x8c5f, NT, "Intel", "Lynx Point", enable_flash_pch8}, + {0x8086, 0x9c41, NT, "Intel", "Lynx Point LP Eng. Sample", enable_flash_pch8_lp}, + {0x8086, 0x9c43, NT, "Intel", "Lynx Point LP Premium", enable_flash_pch8_lp}, + {0x8086, 0x9c45, NT, "Intel", "Lynx Point LP Mainstream", enable_flash_pch8_lp}, + {0x8086, 0x9c47, NT, "Intel", "Lynx Point LP Value", enable_flash_pch8_lp}, + {0x8086, 0x8d40, NT, "Intel", "Wellsburg", enable_flash_pch8_wb}, + {0x8086, 0x8d41, NT, "Intel", "Wellsburg", enable_flash_pch8_wb}, + {0x8086, 0x8d42, NT, "Intel", "Wellsburg", enable_flash_pch8_wb}, + {0x8086, 0x8d43, NT, "Intel", "Wellsburg", enable_flash_pch8_wb}, + {0x8086, 0x8d44, NT, "Intel", "Wellsburg", enable_flash_pch8_wb}, + {0x8086, 0x8d45, NT, "Intel", "Wellsburg", enable_flash_pch8_wb}, + {0x8086, 0x8d46, NT, "Intel", "Wellsburg", enable_flash_pch8_wb}, + {0x8086, 0x8d47, NT, "Intel", "Wellsburg", enable_flash_pch8_wb}, + {0x8086, 0x8d48, NT, "Intel", "Wellsburg", enable_flash_pch8_wb}, + {0x8086, 0x8d49, NT, "Intel", "Wellsburg", enable_flash_pch8_wb}, + {0x8086, 0x8d4a, NT, "Intel", "Wellsburg", enable_flash_pch8_wb}, + {0x8086, 0x8d4b, NT, "Intel", "Wellsburg", enable_flash_pch8_wb}, + {0x8086, 0x8d4c, NT, "Intel", "Wellsburg", enable_flash_pch8_wb}, + {0x8086, 0x8d4d, NT, "Intel", "Wellsburg", enable_flash_pch8_wb}, + {0x8086, 0x8d4e, NT, "Intel", "Wellsburg", enable_flash_pch8_wb}, + {0x8086, 0x8d4f, NT, "Intel", "Wellsburg", enable_flash_pch8_wb}, + {0x8086, 0x8d50, NT, "Intel", "Wellsburg", enable_flash_pch8_wb}, + {0x8086, 0x8d51, NT, "Intel", "Wellsburg", enable_flash_pch8_wb}, + {0x8086, 0x8d52, NT, "Intel", "Wellsburg", enable_flash_pch8_wb}, + {0x8086, 0x8d53, NT, "Intel", "Wellsburg", enable_flash_pch8_wb}, + {0x8086, 0x8d54, NT, "Intel", "Wellsburg", enable_flash_pch8_wb}, + {0x8086, 0x8d55, NT, "Intel", "Wellsburg", enable_flash_pch8_wb}, + {0x8086, 0x8d56, NT, "Intel", "Wellsburg", enable_flash_pch8_wb}, + {0x8086, 0x8d57, NT, "Intel", "Wellsburg", enable_flash_pch8_wb}, + {0x8086, 0x8d58, NT, "Intel", "Wellsburg", enable_flash_pch8_wb}, + {0x8086, 0x8d59, NT, "Intel", "Wellsburg", enable_flash_pch8_wb}, + {0x8086, 0x8d5a, NT, "Intel", "Wellsburg", enable_flash_pch8_wb}, + {0x8086, 0x8d5b, NT, "Intel", "Wellsburg", enable_flash_pch8_wb}, + {0x8086, 0x8d5c, NT, "Intel", "Wellsburg", enable_flash_pch8_wb}, + {0x8086, 0x8d5d, NT, "Intel", "Wellsburg", enable_flash_pch8_wb}, + {0x8086, 0x8d5e, NT, "Intel", "Wellsburg", enable_flash_pch8_wb}, + {0x8086, 0x8d5f, NT, "Intel", "Wellsburg", enable_flash_pch8_wb}, #endif {0}, }; Modified: trunk/print.c ============================================================================== --- trunk/print.c Mon Jun 2 02:12:23 2014 (r1814) +++ trunk/print.c Mon Jun 2 02:34:58 2014 (r1815) @@ -395,7 +395,7 @@ for (i = strlen("Chipset"); i < maxchipsetlen; i++) msg_ginfo(" "); - msg_ginfo("PCI IDs State\n\n"); + msg_ginfo("PCI IDs Status\n\n"); for (c = chipset_enables; c->vendor_name != NULL; c++) { msg_ginfo("%s", c->vendor_name); @@ -404,8 +404,8 @@ msg_ginfo("%s", c->device_name); for (i = 0; i < maxchipsetlen - strlen(c->device_name); i++) msg_ginfo(" "); - msg_ginfo("%04x:%04x%s\n", c->vendor_id, c->device_id, - (c->status == NT) ? " (untested)" : ""); + msg_ginfo("%04x:%04x %s\n", c->vendor_id, c->device_id, + test_state_to_text(c->status)); } }

1 0

Re: [flashrom] [PATCH] Add default arguments for the default programmer (only).
by Carl-Daniel Hailfinger 01 Jun '14

01 Jun '14

Am 30.05.2014 00:52 schrieb Stefan Tauner: > This code exists thanks to food for thought from Urja Rannikko. > > Signed-off-by: Stefan Tauner <stefan.tauner(a)alumni.tuwien.ac.at> Interesting, to say the least. The default parameter only applies if -p is not specified at all, so there are no unexpected side effects. The only complaint I have (except the question "who would want to use that") is that you can run make CONFIG_DEFAULT_PROGRAMMER_ARGS="foobar" without having to specify CONFIG_DEFAULT_PROGRAMMER as well. CONFIG_DEFAULT_PROGRAMMER_ARGS won't have any effect in that case during runtime, but that might surprise someone who specified it. Hm. Maybe I should really ask who would want to use that... it's obviously not a feature distributions would use, although it seems some of them use CONFIG_DEFAULT_PROGRAMMER to keep the behavoir unchanged compared to previous releases. Not opposed to it, but not really convinced either. Regards, Carl-Daniel > diff --git a/Makefile b/Makefile > index 346d46a..998979d 100644 > --- a/Makefile > +++ b/Makefile > @@ -52,6 +52,11 @@ DOSLIBS_BASE ?= .. > # evaluated below, namely those that enable/disable the various programmers). > # Compilation will fail for unspecified values. > CONFIG_DEFAULT_PROGRAMMER ?= PROGRAMMER_INVALID > +# The following adds a default parameter for the default programmer set above (only). > +CONFIG_DEFAULT_PROGRAMMER_ARGS ?= '' > +# Example: compiling with > +# make CONFIG_DEFAULT_PROGRAMMER=PROGRAMMER_SERPROG CONFIG_DEFAULT_PROGRAMMER_ARGS="dev=/dev/ttyUSB0:1500000" > +# would make executing './flashrom' (almost) equivialent to './flashrom -p serprog:dev=/dev/ttyUSB0:1500000'. > > # If your compiler spits out excessive warnings, run make WARNERROR=no > # You shouldn't have to change this flag. > @@ -471,6 +476,7 @@ CONFIG_INTERNAL_DMI ?= yes > # Depending on the CONFIG_* variables set and verified above we set compiler flags and parameters below. > > FEATURE_CFLAGS += -D'CONFIG_DEFAULT_PROGRAMMER=$(CONFIG_DEFAULT_PROGRAMMER)' > +FEATURE_CFLAGS += -D'CONFIG_DEFAULT_PROGRAMMER_ARGS="$(CONFIG_DEFAULT_PROGRAMMER_ARGS)"' > > ifeq ($(CONFIG_INTERNAL), yes) > FEATURE_CFLAGS += -D'CONFIG_INTERNAL=1' > diff --git a/cli_classic.c b/cli_classic.c > index a32d55b..fc1b9ba 100644 > --- a/cli_classic.c > +++ b/cli_classic.c > @@ -396,8 +396,10 @@ int main(int argc, char *argv[]) > if (prog == PROGRAMMER_INVALID) { > if (CONFIG_DEFAULT_PROGRAMMER != PROGRAMMER_INVALID) { > prog = CONFIG_DEFAULT_PROGRAMMER; > - msg_pinfo("Using default programmer \"%s\".\n", > - programmer_table[CONFIG_DEFAULT_PROGRAMMER].name); > + /* We need to strdup here because we free(pparam) unconditionally later. */ > + pparam = strdup(CONFIG_DEFAULT_PROGRAMMER_ARGS); > + msg_pinfo("Using default programmer \"%s\" with arguments \"%s\".\n", > + programmer_table[CONFIG_DEFAULT_PROGRAMMER].name, pparam); > } else { > msg_perr("Please select a programmer with the --programmer parameter.\n" > "Previously this was not necessary because there was a default set.\n" -- http://www.hailfinger.org/

2 3

[commit] r1814 - trunk
by repository service 01 Jun '14

01 Jun '14

Author: stefanct Date: Mon Jun 2 02:12:23 2014 New Revision: 1814 URL: http://flashrom.org/trac/flashrom/changeset/1814 Log: Add default arguments for the default programmer (only). This code exists thanks to food for thought from Urja Rannikko. Signed-off-by: Stefan Tauner <stefan.tauner(a)alumni.tuwien.ac.at> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: trunk/Makefile trunk/cli_classic.c Modified: trunk/Makefile ============================================================================== --- trunk/Makefile Mon Jun 2 01:49:03 2014 (r1813) +++ trunk/Makefile Mon Jun 2 02:12:23 2014 (r1814) @@ -52,6 +52,11 @@ # evaluated below, namely those that enable/disable the various programmers). # Compilation will fail for unspecified values. CONFIG_DEFAULT_PROGRAMMER ?= PROGRAMMER_INVALID +# The following adds a default parameter for the default programmer set above (only). +CONFIG_DEFAULT_PROGRAMMER_ARGS ?= '' +# Example: compiling with +# make CONFIG_DEFAULT_PROGRAMMER=PROGRAMMER_SERPROG CONFIG_DEFAULT_PROGRAMMER_ARGS="dev=/dev/ttyUSB0:1500000" +# would make executing './flashrom' (almost) equivialent to './flashrom -p serprog:dev=/dev/ttyUSB0:1500000'. # If your compiler spits out excessive warnings, run make WARNERROR=no # You shouldn't have to change this flag. @@ -487,6 +492,7 @@ # Depending on the CONFIG_* variables set and verified above we set compiler flags and parameters below. FEATURE_CFLAGS += -D'CONFIG_DEFAULT_PROGRAMMER=$(CONFIG_DEFAULT_PROGRAMMER)' +FEATURE_CFLAGS += -D'CONFIG_DEFAULT_PROGRAMMER_ARGS="$(CONFIG_DEFAULT_PROGRAMMER_ARGS)"' ifeq ($(CONFIG_INTERNAL), yes) FEATURE_CFLAGS += -D'CONFIG_INTERNAL=1' Modified: trunk/cli_classic.c ============================================================================== --- trunk/cli_classic.c Mon Jun 2 01:49:03 2014 (r1813) +++ trunk/cli_classic.c Mon Jun 2 02:12:23 2014 (r1814) @@ -396,8 +396,10 @@ if (prog == PROGRAMMER_INVALID) { if (CONFIG_DEFAULT_PROGRAMMER != PROGRAMMER_INVALID) { prog = CONFIG_DEFAULT_PROGRAMMER; - msg_pinfo("Using default programmer \"%s\".\n", - programmer_table[CONFIG_DEFAULT_PROGRAMMER].name); + /* We need to strdup here because we free(pparam) unconditionally later. */ + pparam = strdup(CONFIG_DEFAULT_PROGRAMMER_ARGS); + msg_pinfo("Using default programmer \"%s\" with arguments \"%s\".\n", + programmer_table[CONFIG_DEFAULT_PROGRAMMER].name, pparam); } else { msg_perr("Please select a programmer with the --programmer parameter.\n" "Previously this was not necessary because there was a default set.\n"

1 0

Re: [flashrom] [PATCH 2/2] Move global io_base_addr into compilation units.
by Carl-Daniel Hailfinger 01 Jun '14

01 Jun '14

Am 02.06.2014 00:43 schrieb Stefan Tauner: > Signed-off-by: Stefan Tauner <stefan.tauner(a)alumni.tuwien.ac.at> Thanks for your patch. Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Regards, Carl-Daniel -- http://www.hailfinger.org/

2 1

Re: [flashrom] [PATCH 1/2] Add IT8212F as programmer.
by Carl-Daniel Hailfinger 01 Jun '14

01 Jun '14

Am 02.06.2014 00:43 schrieb Stefan Tauner: > This PCI PATA controller can use 3V parallel flash up to 128 kB. > > My card was identified as: > PCI 1283:8212, subsystem 1283:0001. > > and labelled as: > Innovision Multimedia LTD. > EIO ATA133 RAID > (DM-8401 Ver A) > > This particular card did not require setting of any GPIO signals to > enable flash writing. My card has Pm39LV512 in PLCC32 package without > socket. > > Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> > Signed-off-by: Stefan Tauner <stefan.tauner(a)alumni.tuwien.ac.at> Looks good, thanks for your patch! Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Regards, Carl-Daniel -- http://www.hailfinger.org/

2 1

[commit] r1813 - trunk
by repository service 01 Jun '14

01 Jun '14

Author: stefanct Date: Mon Jun 2 01:49:03 2014 New Revision: 1813 URL: http://flashrom.org/trac/flashrom/changeset/1813 Log: Move global io_base_addr into compilation units. Signed-off-by: Stefan Tauner <stefan.tauner(a)alumni.tuwien.ac.at> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: trunk/atahpt.c trunk/gfxnvidia.c trunk/it8212.c trunk/nic3com.c trunk/nicintel_spi.c trunk/nicnatsemi.c trunk/nicrealtek.c trunk/ogp_spi.c trunk/pcidev.c trunk/programmer.h Modified: trunk/atahpt.c ============================================================================== --- trunk/atahpt.c Mon Jun 2 01:48:31 2014 (r1812) +++ trunk/atahpt.c Mon Jun 2 01:49:03 2014 (r1813) @@ -33,6 +33,8 @@ #define PCI_VENDOR_ID_HPT 0x1103 +static uint32_t io_base_addr = 0; + const struct dev_entry ata_hpt[] = { {0x1103, 0x0004, NT, "Highpoint", "HPT366/368/370/370A/372/372N"}, {0x1103, 0x0005, NT, "Highpoint", "HPT372A/372N"}, Modified: trunk/gfxnvidia.c ============================================================================== --- trunk/gfxnvidia.c Mon Jun 2 01:48:31 2014 (r1812) +++ trunk/gfxnvidia.c Mon Jun 2 01:49:03 2014 (r1813) @@ -89,7 +89,7 @@ if (!dev) return 1; - io_base_addr = pcidev_readbar(dev, PCI_BASE_ADDRESS_0); + uint32_t io_base_addr = pcidev_readbar(dev, PCI_BASE_ADDRESS_0); if (!io_base_addr) return 1; Modified: trunk/it8212.c ============================================================================== --- trunk/it8212.c Mon Jun 2 01:48:31 2014 (r1812) +++ trunk/it8212.c Mon Jun 2 01:49:03 2014 (r1813) @@ -59,7 +59,7 @@ return 1; /* Bit 0 is address decode enable, 17-31 the base address, everything else reserved/zero. */ - io_base_addr = pcidev_readbar(dev, PCI_ROM_ADDRESS) & 0xFFFFFFFE; + uint32_t io_base_addr = pcidev_readbar(dev, PCI_ROM_ADDRESS) & 0xFFFFFFFE; if (!io_base_addr) return 1; Modified: trunk/nic3com.c ============================================================================== --- trunk/nic3com.c Mon Jun 2 01:48:31 2014 (r1812) +++ trunk/nic3com.c Mon Jun 2 01:49:03 2014 (r1813) @@ -33,6 +33,7 @@ #define PCI_VENDOR_ID_3COM 0x10b7 +static uint32_t io_base_addr = 0; static uint32_t internal_conf; static uint16_t id; Modified: trunk/nicintel_spi.c ============================================================================== --- trunk/nicintel_spi.c Mon Jun 2 01:48:31 2014 (r1812) +++ trunk/nicintel_spi.c Mon Jun 2 01:49:03 2014 (r1813) @@ -179,7 +179,7 @@ if (!dev) return 1; - io_base_addr = pcidev_readbar(dev, PCI_BASE_ADDRESS_0); + uint32_t io_base_addr = pcidev_readbar(dev, PCI_BASE_ADDRESS_0); if (!io_base_addr) return 1; Modified: trunk/nicnatsemi.c ============================================================================== --- trunk/nicnatsemi.c Mon Jun 2 01:48:31 2014 (r1812) +++ trunk/nicnatsemi.c Mon Jun 2 01:49:03 2014 (r1813) @@ -30,6 +30,7 @@ #define BOOT_ROM_ADDR 0x50 #define BOOT_ROM_DATA 0x54 +static uint32_t io_base_addr = 0; const struct dev_entry nics_natsemi[] = { {0x100b, 0x0020, NT, "National Semiconductor", "DP83815/DP83816"}, {0x100b, 0x0022, NT, "National Semiconductor", "DP83820"}, Modified: trunk/nicrealtek.c ============================================================================== --- trunk/nicrealtek.c Mon Jun 2 01:48:31 2014 (r1812) +++ trunk/nicrealtek.c Mon Jun 2 01:49:03 2014 (r1813) @@ -28,6 +28,7 @@ #define PCI_VENDOR_ID_REALTEK 0x10ec #define PCI_VENDOR_ID_SMC1211 0x1113 +static uint32_t io_base_addr = 0; static int bios_rom_addr, bios_rom_data; const struct dev_entry nics_realtek[] = { Modified: trunk/ogp_spi.c ============================================================================== --- trunk/ogp_spi.c Mon Jun 2 01:48:31 2014 (r1812) +++ trunk/ogp_spi.c Mon Jun 2 01:49:03 2014 (r1813) @@ -132,7 +132,7 @@ if (!dev) return 1; - io_base_addr = pcidev_readbar(dev, PCI_BASE_ADDRESS_0); + uint32_t io_base_addr = pcidev_readbar(dev, PCI_BASE_ADDRESS_0); if (!io_base_addr) return 1; Modified: trunk/pcidev.c ============================================================================== --- trunk/pcidev.c Mon Jun 2 01:48:31 2014 (r1812) +++ trunk/pcidev.c Mon Jun 2 01:49:03 2014 (r1813) @@ -25,7 +25,6 @@ #include "programmer.h" #include "hwaccess.h" -uint32_t io_base_addr; struct pci_access *pacc; enum pci_bartype { Modified: trunk/programmer.h ============================================================================== --- trunk/programmer.h Mon Jun 2 01:48:31 2014 (r1812) +++ trunk/programmer.h Mon Jun 2 01:49:03 2014 (r1813) @@ -173,8 +173,7 @@ struct pci_dev; /* pcidev.c */ -// FIXME: These need to be local, not global -extern uint32_t io_base_addr; +// FIXME: This needs to be local, not global(?) extern struct pci_access *pacc; int pci_init_common(void); uintptr_t pcidev_readbar(struct pci_dev *dev, int bar);

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[commit] r1812 - trunk
by repository service 01 Jun '14

01 Jun '14

Author: stefanct Date: Mon Jun 2 01:48:31 2014 New Revision: 1812 URL: http://flashrom.org/trac/flashrom/changeset/1812 Log: Add IT8212F as programmer. This PCI PATA controller can use 3V parallel flash up to 128 kB. My card was identified as: PCI 1283:8212, subsystem 1283:0001. and labelled as: Innovision Multimedia LTD. EIO ATA133 RAID (DM-8401 Ver A) This particular card did not require setting of any GPIO signals to enable flash writing. My card has Pm39LV512 in PLCC32 package without socket. Rebased by Stefan (automatic cleanup, some PCI changes, changed enable bit handling). Committed with test state NT because the rebased version was not tested on real hardware (yet). Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Signed-off-by: Stefan Tauner <stefan.tauner(a)alumni.tuwien.ac.at> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Added: trunk/it8212.c (contents, props changed) Modified: trunk/Makefile trunk/flashrom.8.tmpl trunk/flashrom.c trunk/programmer.h Modified: trunk/Makefile ============================================================================== --- trunk/Makefile Mon Jun 2 00:36:30 2014 (r1811) +++ trunk/Makefile Mon Jun 2 01:48:31 2014 (r1812) @@ -197,6 +197,11 @@ else override CONFIG_ATAVIA = no endif +ifeq ($(CONFIG_IT8212), yes) +UNSUPPORTED_FEATURES += CONFIG_IT8212=yes +else +override CONFIG_IT8212 = no +endif ifeq ($(CONFIG_DRKAISER), yes) UNSUPPORTED_FEATURES += CONFIG_DRKAISER=yes else @@ -431,6 +436,9 @@ # Enable Linux spidev interface by default. We disable it on non-Linux targets. CONFIG_LINUX_SPI ?= yes +# Always enable ITE IT8212F PATA controllers for now. +CONFIG_IT8212 ?= yes + # Disable wiki printing by default. It is only useful if you have wiki access. CONFIG_PRINT_WIKI ?= no @@ -549,6 +557,12 @@ NEED_PCI := yes endif +ifeq ($(CONFIG_IT8212), yes) +FEATURE_CFLAGS += -D'CONFIG_IT8212=1' +PROGRAMMER_OBJS += it8212.o +NEED_PCI := yes +endif + ifeq ($(CONFIG_FT2232_SPI), yes) # This is a totally ugly hack. FEATURE_CFLAGS += $(shell LC_ALL=C grep -q "FTDISUPPORT := yes" .features && printf "%s" "-D'CONFIG_FT2232_SPI=1'") Modified: trunk/flashrom.8.tmpl ============================================================================== --- trunk/flashrom.8.tmpl Mon Jun 2 00:36:30 2014 (r1811) +++ trunk/flashrom.8.tmpl Mon Jun 2 01:48:31 2014 (r1812) @@ -194,6 +194,8 @@ .sp .BR "* atavia" " (for flash ROMs on VIA VT6421A SATA controllers)" .sp +.BR "* it8212" " (for flash ROMs on ITE IT8212F ATA/RAID controller)" +.sp .BR "* ft2232_spi" " (for SPI flash ROMs attached to an FT2232/FT4232H/FT232H family \ based USB SPI programmer), including the DLP Design DLP-USB1232H, \ FTDI FT2232H Mini-Module, FTDI FT4232H Mini-Module, openbiosprog-spi, Amontec \ @@ -591,7 +593,7 @@ .SS .BR "nic3com" , " nicrealtek" , " nicnatsemi" , " nicintel"\ , " nicintel_spi" , " gfxnvidia" , " ogp_spi" , " drkaiser" , " satasii"\ -, " satamv" , " atahpt" ", and " atavia " programmers +, " satamv" , " atahpt" ", " atavia " and " it8212 " programmers These programmers have an option to specify the PCI address of the card your want to use, which must be specified if more than one card supported by the selected programmer is installed in your system. The syntax is @@ -914,7 +916,7 @@ .B atahpt needs PCI configuration space access and raw I/O port access. .sp -.BR gfxnvidia " and " drkaiser +.BR gfxnvidia ", " drkaiser " and " it8212 need PCI configuration space access and raw memory access. .sp .B rayer_spi Modified: trunk/flashrom.c ============================================================================== --- trunk/flashrom.c Mon Jun 2 00:36:30 2014 (r1811) +++ trunk/flashrom.c Mon Jun 2 01:48:31 2014 (r1812) @@ -184,6 +184,18 @@ }, #endif +#if CONFIG_IT8212 == 1 + { + .name = "it8212", + .type = PCI, + .devs.dev = devs_it8212, + .init = it8212_init, + .map_flash_region = fallback_map, + .unmap_flash_region = fallback_unmap, + .delay = internal_delay, + }, +#endif + #if CONFIG_FT2232_SPI == 1 { .name = "ft2232_spi", Added: trunk/it8212.c ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/it8212.c Mon Jun 2 01:48:31 2014 (r1812) @@ -0,0 +1,86 @@ +/* + * This file is part of the flashrom project. + * + * Copyright (C) 2011 Carl-Daniel Hailfinger + * Copyright (C) 2012 Kyösti Mälkki <kyosti.malkki(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stdlib.h> +#include "flash.h" +#include "programmer.h" +#include "hwaccess.h" + +static uint8_t *it8212_bar = NULL; + +#define PCI_VENDOR_ID_ITE 0x1283 + +const struct dev_entry devs_it8212[] = { + {PCI_VENDOR_ID_ITE, 0x8212, OK, "ITE", "8212F PATA RAID"}, + + {}, +}; + +#define IT8212_MEMMAP_SIZE (128 * 1024) +#define IT8212_MEMMAP_MASK (IT8212_MEMMAP_SIZE - 1) + +static void it8212_chip_writeb(const struct flashctx *flash, uint8_t val, chipaddr addr); +static uint8_t it8212_chip_readb(const struct flashctx *flash, const chipaddr addr); +static const struct par_programmer par_programmer_it8212 = { + .chip_readb = it8212_chip_readb, + .chip_readw = fallback_chip_readw, + .chip_readl = fallback_chip_readl, + .chip_readn = fallback_chip_readn, + .chip_writeb = it8212_chip_writeb, + .chip_writew = fallback_chip_writew, + .chip_writel = fallback_chip_writel, + .chip_writen = fallback_chip_writen, +}; + +int it8212_init(void) +{ + if (rget_io_perms()) + return 1; + + struct pci_dev *dev = pcidev_init(devs_it8212, PCI_ROM_ADDRESS); + if (!dev) + return 1; + + /* Bit 0 is address decode enable, 17-31 the base address, everything else reserved/zero. */ + io_base_addr = pcidev_readbar(dev, PCI_ROM_ADDRESS) & 0xFFFFFFFE; + if (!io_base_addr) + return 1; + + it8212_bar = rphysmap("IT8212F flash", io_base_addr, IT8212_MEMMAP_SIZE); + if (it8212_bar == ERROR_PTR) + return 1; + + /* Restore ROM BAR decode state automatically at shutdown. */ + rpci_write_long(dev, PCI_ROM_ADDRESS, io_base_addr | 0x01); + + max_rom_decode.parallel = IT8212_MEMMAP_SIZE; + register_par_programmer(&par_programmer_it8212, BUS_PARALLEL); + return 0; +} + +static void it8212_chip_writeb(const struct flashctx *flash, uint8_t val, chipaddr addr) +{ + pci_mmio_writeb(val, it8212_bar + (addr & IT8212_MEMMAP_MASK)); +} + +static uint8_t it8212_chip_readb(const struct flashctx *flash, const chipaddr addr) +{ + return pci_mmio_readb(it8212_bar + (addr & IT8212_MEMMAP_MASK)); +} Modified: trunk/programmer.h ============================================================================== --- trunk/programmer.h Mon Jun 2 00:36:30 2014 (r1811) +++ trunk/programmer.h Mon Jun 2 01:48:31 2014 (r1812) @@ -57,6 +57,9 @@ #if CONFIG_ATAVIA == 1 PROGRAMMER_ATAVIA, #endif +#if CONFIG_IT8212 == 1 + PROGRAMMER_IT8212, +#endif #if CONFIG_FT2232_SPI == 1 PROGRAMMER_FT2232_SPI, #endif @@ -444,6 +447,12 @@ extern const struct dev_entry ata_via[]; #endif +/* it8212.c */ +#if CONFIG_IT8212 == 1 +int it8212_init(void); +extern const struct dev_entry devs_it8212[]; +#endif + /* ft2232_spi.c */ #if CONFIG_FT2232_SPI == 1 int ft2232_spi_init(void);

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flashrom June 2014