flashrom August 2013

flashrom@flashrom.org

29 participants
169 discussions

Report: ASUSTeK K55A K55A.407 read
by dpcimanager＠users.sourceforge.net 11 Aug '13

11 Aug '13

flashrom v0.9.6.1-r1698 on Darwin 12.4.0 (x86_64) flashrom is free software, get the source code at http://www.flashrom.org flashrom was built with libpci 3.2.0, LLVM Clang 4.2 (clang-425.0.28), little endian Command line (5 args): ~/Downloads/DPCIManager/DPCIManager.app/Contents/MacOS/flashrom -VV -r /var/folders/vz/v7vt3_bj2wd1f3_n9v7h0yhc0000gn/T/DPCI0qDZy6.rom -p internal Calibrating delay loop... OS timer resolution is 1 usecs, 357M loops per second, 10 myus = 11 us, 100 myus = 100 us, 1000 myus = 1013 us, 10000 myus = 10049 us, 4 myus = 4 us, OK. Initializing internal programmer Mapping low megabyte at 0x00000400, unaligned size 0xffc00. Mapping low megabyte, 0xffc00 bytes at unaligned 0x00000400. No coreboot table found. DMI string system-manufacturer: "ASUSTeK COMPUTER INC." DMI string system-product-name: "K55A" DMI string system-version: "1.0 " DMI string baseboard-manufacturer: "ASUSTeK COMPUTER INC." DMI string baseboard-product-name: "K55A" DMI string baseboard-version: "1.0 " DMI string chassis-type: "Notebook" Laptop detected via DMI. ======================================================================== WARNING! You seem to be running flashrom on an unsupported laptop. Laptops, notebooks and netbooks are difficult to support and we recommend to use the vendor flashing utility. The embedded controller (EC) in these machines often interacts badly with flashing. See the manpage and http://www.flashrom.org/Laptops for details. If flash is shared with the EC, erase is guaranteed to brick your laptop and write may brick your laptop. Read and probe may irritate your EC and cause fan failure, backlight failure and sudden poweroff. You have been warned. ======================================================================== Aborting. Error: Programmer initialization failed.

1 0

Re: [flashrom] [coreboot] Dualbios on GA-MA770-UD3
by Carl-Daniel Hailfinger 10 Aug '13

10 Aug '13

Hi Vadim, thanks for your mail. I have added the flashrom mailing list in CC: because we should develop a generic way to handle DualBIOS and similar techniques. On 09.04.2010 08:12, Vadim Girlin wrote: > I'm going to try coreboot on Gigabyte GA-MA770-UD3. > It's AMD 770 (RX780 / SB700). > > My motherboard supports hardware dual bios - with two chips on it. > I'm going to try flashing backup chip and boot from it. It seems to be > possible - I've tested it (flashing at least). Chips on this board could > be switched by changing bit 0 at undocumented register EF on LDN 7 of > IT8720. I can use slightly patched flashrom for accessing any chip I > want without any problems. And this is tested many times. > > My idea is to use backup chip for debugging - that always keeps my > chance to reboot from main bios chip. And removes the need for > desoldering etc. > > And second problem is that original bios is checking second chip - and > trying to recover it by flashing the bios from main chip on reboot? > rewriting coreboot. AFAICS this could be solved by including some > signatures etc. It seems to be easy to find out. May be someone is > working on this? > > BTW I can send the patch for flashrom - but I think that with > information I mentioned above somebody could make it much better than my > ugly hack. I hope the regs should be the same for all latest Gigabyte > MBs using IT8720/18 > It would be great if you could send that patch. It will help us make a flashrom design decision that works for all boards with multiple flash chips. By the way, some of us have good contacts at ITE, so we can ask ITE for details about the undocumented registers. Regards, Carl-Daniel -- http://www.hailfinger.org/

5 12

[PATCH] Add support for Fujitsu MBM29LV160BE/TE.
by Stefan Tauner 10 Aug '13

10 Aug '13

Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> --- flashchips.c | 64 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ flashchips.h | 2 ++ 2 files changed, 66 insertions(+) diff --git a/flashchips.c b/flashchips.c index a693290..9b331c7 100644 --- a/flashchips.c +++ b/flashchips.c @@ -4580,6 +4580,70 @@ const struct flashchip flashchips[] = { }, { + .vendor = "Fujitsu", + .name = "MBM29LV160BE", + .bustype = BUS_PARALLEL, + .manufacture_id = FUJITSU_ID, + .model_id = FUJITSU_MBM29LV160BE, + .total_size = 2 * 1024, + .page_size = 0, + .feature_bits = FEATURE_ADDR_SHIFTED | FEATURE_SHORT_RESET, + .tested = TEST_UNTESTED, + .probe = probe_m29f400bt, + .probe_timing = TIMING_IGNORED, + .block_erasers = + { + { + .eraseblocks = { + {16 * 1024, 1}, + {8 * 1024, 2}, + {32 * 1024, 1}, + {64 * 1024, 31}, + }, + .block_erase = block_erase_m29f400bt, + }, { + .eraseblocks = { {2048 * 1024, 1} }, + .block_erase = block_erase_chip_m29f400bt, + }, + }, + .write = write_m29f400bt, /* Supports a fast mode too */ + .read = read_memmapped, + .voltage = {3000, 3600}, /* 3.0-3.6V for type -70, others 2.7-3.6V */ + }, + + { + .vendor = "Fujitsu", + .name = "MBM29LV160TE", + .bustype = BUS_PARALLEL, + .manufacture_id = FUJITSU_ID, + .model_id = FUJITSU_MBM29LV160TE, + .total_size = 2 * 1024, + .page_size = 0, + .feature_bits = FEATURE_ADDR_SHIFTED | FEATURE_SHORT_RESET, + .tested = TEST_UNTESTED, + .probe = probe_m29f400bt, + .probe_timing = TIMING_IGNORED, + .block_erasers = + { + { + .eraseblocks = { + {64 * 1024, 31}, + {32 * 1024, 1}, + {8 * 1024, 2}, + {16 * 1024, 1}, + }, + .block_erase = block_erase_m29f400bt, + }, { + .eraseblocks = { {2048 * 1024, 1} }, + .block_erase = block_erase_chip_m29f400bt, + }, + }, + .write = write_m29f400bt, /* Supports a fast mode too */ + .read = read_memmapped, + .voltage = {3000, 3600}, /* 3.0-3.6V for type -70, others 2.7-3.6V */ + }, + + { .vendor = "GigaDevice", .name = "GD25LQ32", .bustype = BUS_SPI, diff --git a/flashchips.h b/flashchips.h index e19d200..a876f25 100644 --- a/flashchips.h +++ b/flashchips.h @@ -332,6 +332,8 @@ #define FUJITSU_MBM29LV400TC 0xB9 #define FUJITSU_MBM29LV800BA 0x5B /* Same as MBM29LV800BE */ #define FUJITSU_MBM29LV800TA 0xDA /* Same as MBM29LV800TE */ +#define FUJITSU_MBM29LV160BE 0x49 /* 16 b mode 0x2249 */ +#define FUJITSU_MBM29LV160TE 0xC4 /* 16 b mode 0x22C4 */ #define GIGADEVICE_ID 0xC8 /* GigaDevice */ #define GIGADEVICE_GD25T80 0x3114 -- Kind regards, Stefan Tauner

1 0

[PATCH 6/6] debug
by Stefan Tauner 10 Aug '13

10 Aug '13

Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> --- sb600spi.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/sb600spi.c b/sb600spi.c index df6ce14..13adad8 100644 --- a/sb600spi.c +++ b/sb600spi.c @@ -313,7 +313,7 @@ static int spi100_spi_send_command(struct flashctx *flash, unsigned int writecnt msg_pspew("Filling buffer: "); int count; for (count = 0; count < writecnt; count++) { - msg_pspew("[%02x]", writearr[count]); + msg_pspew("[%i %02x]", count, writearr[count]); mmio_writeb(writearr[count], sb600_spibar + 0x80 + count); } msg_pspew("\n"); @@ -323,7 +323,11 @@ static int spi100_spi_send_command(struct flashctx *flash, unsigned int writecnt msg_pspew("Reading buffer: "); for (count = 0; count < readcnt; count++) { readarr[count] = mmio_readb(sb600_spibar + 0x80 + (writecnt + count) % FIFO_SIZE_YANGTZE); - msg_pspew("[%02x]", readarr[count]); + msg_pspew("[%i %02x]", (writecnt + count) % FIFO_SIZE_YANGTZE, readarr[count]); + } + msg_pspew(" "); + for (; count < FIFO_SIZE_YANGTZE; count++) { + msg_pspew("[%i %02x]", (writecnt + count) % FIFO_SIZE_YANGTZE, mmio_readb(sb600_spibar + 0x80 + (writecnt + count) % FIFO_SIZE_YANGTZE)); } msg_pspew("\n"); -- Kind regards, Stefan Tauner

1 0

[PATCH 5/6] sbxxx: Add spispeed parameter.
by Stefan Tauner 10 Aug '13

10 Aug '13

Allow to set the SPI clock frequency on AMD chipsets with a programmer parameter. If the parameter is given (and matches a possible value), the SPI clock is set temporarily. Both registers are restored on programmer shutdown. Example: ./flashrom -p internal:spispeed="33 MHz" -V Possible values for spispeed are "16.5 MHz", "22 MHz", "33 MHz", "66 MHz", "100 MHZ" and "800 kHz" depending on the chipset generation. Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> --- flashrom.8 | 21 +++++++++++++++++++++ sb600spi.c | 23 +++++++++++++++++++++++ 2 files changed, 44 insertions(+) diff --git a/flashrom.8 b/flashrom.8 index dccfd1a..0c6ff2c 100644 --- a/flashrom.8 +++ b/flashrom.8 @@ -345,6 +345,27 @@ syntax. The user is responsible for supplying a suitable image or leaving out th a layout file. This limitation might be removed in the future when we understand the details better and have received enough feedback from users. Please report the outcome if you had to use this option to write a chip. .sp +An optional +.B spispeed +parameter specifies the frequency of the SPI bus where applicable (i.e.\& SB600 or later with an SPI flash chip +directly attached to the chipset). +Syntax is +.sp +.B " flashrom \-p internal:spispeed=frequency" +.sp +where +.B frequency +can be +.BR "'16.5\ MHz'" ", " "'22\ MHz'" ", " "'33\ MHz'" ", " "'66\ MHz'" ", " "'100\ MHZ'" ", or " "'800\ kHz'" "." +Support of individual frequencies depends on the generation of the chipset: +.sp +* SB6xx, SB7xx, SP5xxx: from 16.5 MHz up to and including 33 MHz +.sp +* SB8xx, SB9xx, Hudson: from 16.5 MHz up to and including 66 MHz +.sp +* Yangtze (with SPI 100 engine as found in Kabini and Tamesh): all of them +.sp +The default is to use 16.5 MHz and disable Fast Reads. .TP .B Intel chipsets .sp diff --git a/sb600spi.c b/sb600spi.c index eaafb48..df6ce14 100644 --- a/sb600spi.c +++ b/sb600spi.c @@ -385,6 +385,29 @@ static int handle_speed(struct pci_dev *dev) uint32_t tmp; int8_t spispeed_idx = 3; /* Default to 16.5 MHz */ + char *spispeed = extract_programmer_param("spispeed"); + if (spispeed != NULL) { + if (strcasecmp(spispeed, "reserved") != 0) { + int i; + for (i = 0; i < ARRAY_SIZE(spispeeds); i++) { + if (strcasecmp(spispeeds[i].name, spispeed) == 0) { + spispeed_idx = i; + break; + } + } + /* Only Yangtze supports the second half of indices; no 66 MHz before SB8xx. */ + if ((amd_gen < CHIPSET_YANGTZE && spispeed_idx > 3) || + (amd_gen < CHIPSET_SB89XX && spispeed_idx == 0)) + spispeed_idx = -1; + } + if (spispeed_idx < 0) { + msg_perr("Error: Invalid spispeed value: '%s'.\n", spispeed); + free(spispeed); + return 1; + } + free(spispeed); + } + /* bit 6xx 7xx/SP5100 8xx 9xx hudson1 hudson234 yangtze * 18 rsvd <- fastReadEnable ? <- ? SpiReadMode[0] * 29:30 rsvd <- <- ? <- ? SpiReadMode[2:1] -- Kind regards, Stefan Tauner

1 0

[PATCH 4/6] sbxxx: Add support for new AMD SPI controller.
by Stefan Tauner 10 Aug '13

10 Aug '13

This patch adds support for the "SPI 100" SPI engine in Yangtze FCHs (found in Kabini and Temash). Tested reading/writing on ASRock IMB-A180. Signed-off-by: Wei Hu <wei(a)aristanetworks.com> Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> --- programmer.h | 1 + sb600spi.c | 138 ++++++++++++++++++++++++++++++++++++++++++++++++++++++----- 2 files changed, 129 insertions(+), 10 deletions(-) diff --git a/programmer.h b/programmer.h index f03eac3..0845d61 100644 --- a/programmer.h +++ b/programmer.h @@ -494,6 +494,7 @@ enum spi_controller { SPI_CONTROLLER_IT85XX, SPI_CONTROLLER_IT87XX, SPI_CONTROLLER_SB600, + SPI_CONTROLLER_YANGTZE, SPI_CONTROLLER_VIA, SPI_CONTROLLER_WBSIO, #endif diff --git a/sb600spi.c b/sb600spi.c index ff7dbee..eaafb48 100644 --- a/sb600spi.c +++ b/sb600spi.c @@ -4,7 +4,8 @@ * Copyright (C) 2008 Wang Qingpei <Qingpei.Wang(a)amd.com> * Copyright (C) 2008 Joe Bao <Zheng.Bao(a)amd.com> * Copyright (C) 2008 Advanced Micro Devices, Inc. - * Copyright (C) 2009, 2010 Carl-Daniel Hailfinger + * Copyright (C) 2009, 2010, 2013 Carl-Daniel Hailfinger + * Copyright (C) 2013 Stefan Tauner * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -55,9 +56,12 @@ enum amd_chipset { static enum amd_chipset amd_gen = CHIPSET_AMD_UNKNOWN; #define FIFO_SIZE_OLD 8 +#define FIFO_SIZE_YANGTZE 71 static int sb600_spi_send_command(struct flashctx *flash, unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); +static int spi100_spi_send_command(struct flashctx *flash, unsigned int writecnt, unsigned int readcnt, + const unsigned char *writearr, unsigned char *readarr); static struct spi_programmer spi_programmer_sb600 = { .type = SPI_CONTROLLER_SB600, @@ -70,6 +74,17 @@ static struct spi_programmer spi_programmer_sb600 = { .write_aai = default_spi_write_aai, }; +static struct spi_programmer spi_programmer_yangtze = { + .type = SPI_CONTROLLER_YANGTZE, + .max_data_read = FIFO_SIZE_YANGTZE - 3, /* Apparently the big SPI 100 buffer is not a ring buffer. */ + .max_data_write = FIFO_SIZE_YANGTZE - 3, + .command = spi100_spi_send_command, + .multicommand = default_spi_send_multicommand, + .read = default_spi_read, + .write_256 = default_spi_write_256, + .write_aai = default_spi_write_aai, +}; + static void determine_generation(struct pci_dev *dev) { amd_gen = CHIPSET_AMD_UNKNOWN; @@ -276,6 +291,45 @@ static int sb600_spi_send_command(struct flashctx *flash, unsigned int writecnt, return 0; } +static int spi100_spi_send_command(struct flashctx *flash, unsigned int writecnt, + unsigned int readcnt, + const unsigned char *writearr, + unsigned char *readarr) +{ + /* First byte is cmd which can not be sent through the buffer. */ + unsigned char cmd = *writearr++; + writecnt--; + msg_pspew("%s, cmd=0x%02x, writecnt=%d, readcnt=%d\n", __func__, cmd, writecnt, readcnt); + mmio_writeb(cmd, sb600_spibar + 0); + + int ret = check_readwritecnt(flash, writecnt, readcnt); + if (ret != 0) + return ret; + + /* Use the extended TxByteCount and RxByteCount registers. */ + mmio_writeb(writecnt, sb600_spibar + 0x48); + mmio_writeb(readcnt, sb600_spibar + 0x4b); + + msg_pspew("Filling buffer: "); + int count; + for (count = 0; count < writecnt; count++) { + msg_pspew("[%02x]", writearr[count]); + mmio_writeb(writearr[count], sb600_spibar + 0x80 + count); + } + msg_pspew("\n"); + + execute_command(); + + msg_pspew("Reading buffer: "); + for (count = 0; count < readcnt; count++) { + readarr[count] = mmio_readb(sb600_spibar + 0x80 + (writecnt + count) % FIFO_SIZE_YANGTZE); + msg_pspew("[%02x]", readarr[count]); + } + msg_pspew("\n"); + + return 0; +} + struct spispeed { const char *const name; const int8_t speed; @@ -286,6 +340,10 @@ static const struct spispeed spispeeds[] = { { "33 MHz", 0x01 }, { "22 MHz", 0x02 }, { "16.5 MHz", 0x03 }, + { "100 MHz", 0x04 }, + { "Reserved", 0x05 }, + { "Reserved", 0x06 }, + { "800 kHz", 0x07 }, }; static int set_speed(struct pci_dev *dev, const struct spispeed *spispeed) @@ -294,7 +352,12 @@ static int set_speed(struct pci_dev *dev, const struct spispeed *spispeed) uint8_t speed = spispeed->speed; msg_pdbg("Setting SPI clock to %s (0x%x).\n", spispeed->name, speed); - if (amd_gen != CHIPSET_YANGTZE) { + if (amd_gen >= CHIPSET_YANGTZE) { + rmmio_writew((speed << 12) | (speed << 8) | (speed << 4) | speed, sb600_spibar + 0x22); + uint16_t tmp = mmio_readw(sb600_spibar + 0x22); + success = (((tmp >> 12) & 0xf) == speed && ((tmp >> 8) & 0xf) == speed && + ((tmp >> 4) & 0xf) == speed && ((tmp >> 0) & 0xf) == speed); + } else { rmmio_writeb((mmio_readb(sb600_spibar + 0xd) & ~(0x3 << 4)) | (speed << 4), sb600_spibar + 0xd); success = (speed == ((mmio_readb(sb600_spibar + 0xd) >> 4) & 0x3)); } @@ -306,6 +369,17 @@ static int set_speed(struct pci_dev *dev, const struct spispeed *spispeed) return 0; } +static int set_mode(struct pci_dev *dev, uint8_t read_mode) +{ + uint32_t tmp = mmio_readl(sb600_spibar + 0x00); + tmp &= ~(0x6 << 28 | 0x1 << 18); /* Clear mode bits */ + tmp |= ((read_mode & 0x6) << 28) | ((read_mode & 0x1) << 18); + rmmio_writel(tmp, sb600_spibar + 0x00); + if (tmp != mmio_readl(sb600_spibar + 0x00)) + return 1; + return 0; +} + static int handle_speed(struct pci_dev *dev) { uint32_t tmp; @@ -315,7 +389,47 @@ static int handle_speed(struct pci_dev *dev) * 18 rsvd <- fastReadEnable ? <- ? SpiReadMode[0] * 29:30 rsvd <- <- ? <- ? SpiReadMode[2:1] */ - if (amd_gen != CHIPSET_YANGTZE) { + if (amd_gen >= CHIPSET_YANGTZE) { + tmp = mmio_readb(sb600_spibar + 0x20); + msg_pdbg("UseSpi100 is %sabled\n", (tmp & 0x1) ? "en" : "dis"); + if ((tmp & 0x1) == 0) { + rmmio_writeb(tmp | 0x1, sb600_spibar + 0x20); + tmp = mmio_readb(sb600_spibar + 0x20) & 0x1; + if (tmp == 0) { + msg_perr("Enabling Spi100 failed.\n"); + return 1; + } + msg_pdbg("Enabling Spi100 succeeded.\n"); + } + + static const char *spireadmodes[] = { + "Normal (up to 33 MHz)", /* 0 */ + "Reserved", /* 1 */ + "Dual IO (1-1-2)", /* 2 */ + "Quad IO (1-1-4)", /* 3 */ + "Dual IO (1-2-2)", /* 4 */ + "Quad IO (1-4-4)", /* 5 */ + "Normal (up to 66 MHz)", /* 6 */ + "Fast Read", /* 7 */ + }; + tmp = mmio_readl(sb600_spibar + 0x00); + uint8_t read_mode = ((tmp >> 28) & 0x6) | ((tmp >> 18) & 0x1); + msg_pdbg("SpiReadMode=%s (%i)\n", spireadmodes[read_mode], read_mode); + if (read_mode != 6) { + read_mode = 6; /* Default to "Normal (up to 66 MHz)" */ + if (set_mode(dev, read_mode) != 0) { + msg_perr("Setting read mode to \"%s\" failed.\n", spireadmodes[read_mode]); + return 1; + } + msg_pdbg("Setting read mode to \"%s\" succeeded.\n", spireadmodes[read_mode]); + } + + tmp = mmio_readw(sb600_spibar + 0x22); /* SPI 100 Speed Config */ + msg_pdbg("NormSpeedNew is %s\n", spispeeds[(tmp >> 12) & 0xf].name); + msg_pdbg("FastSpeedNew is %s\n", spispeeds[(tmp >> 8) & 0xf].name); + msg_pdbg("AltSpeedNew is %s\n", spispeeds[(tmp >> 4) & 0xf].name); + msg_pdbg("TpmSpeedNew is %s\n", spispeeds[(tmp >> 0) & 0xf].name); + } else { if (amd_gen >= CHIPSET_SB89XX && amd_gen <= CHIPSET_HUDSON234) { bool fast_read = (mmio_readl(sb600_spibar + 0x00) >> 18) & 0x1; msg_pdbg("Fast Reads are %sabled\n", fast_read ? "en" : "dis"); @@ -411,12 +525,6 @@ int sb600_probe_spi(struct pci_dev *dev) amd_gen = CHIPSET_SB6XX; } - if (amd_gen == CHIPSET_YANGTZE) { - msg_perr("SPI on Kabini/Temash and newer chipsets are not yet supported.\n" - "Please try a newer version of flashrom.\n"); - return ERROR_NONFATAL; - } - /* Chipset support matrix for SPI Base_Addr (LPC PCI reg 0xa0) * bit 6xx 7xx/SP5100 8xx 9xx hudson1 hudson2+ yangtze * 3 rsvd <- <- ? <- ? RouteTpm2Spi @@ -431,6 +539,8 @@ int sb600_probe_spi(struct pci_dev *dev) msg_pdbg("SpiRomEnable=%i", (tmp >> 1) & 0x1); if (amd_gen == CHIPSET_SB7XX) msg_pdbg(", AltSpiCSEnable=%i, AbortEnable=%i", tmp & 0x1, (tmp >> 2) & 0x1); + else if (amd_gen == CHIPSET_YANGTZE) + msg_pdbg(", RouteTpm2Sp=%i", (tmp >> 3) & 0x1); tmp = pci_read_byte(dev, 0xba); msg_pdbg(", PrefetchEnSPIFromIMC=%i", (tmp & 0x4) >> 2); @@ -464,6 +574,8 @@ int sb600_probe_spi(struct pci_dev *dev) */ tmp = mmio_readl(sb600_spibar + 0x00); msg_pdbg("(0x%08" PRIx32 ") SpiArbEnable=%i", tmp, (tmp >> 19) & 0x1); + if (amd_gen == CHIPSET_YANGTZE) + msg_pdbg(", IllegalAccess=%i", (tmp >> 21) & 0x1); msg_pdbg(", SpiAccessMacRomEn=%i, SpiHostAccessRomEn=%i, ArbWaitCount=%i", (tmp >> 22) & 0x1, (tmp >> 23) & 0x1, (tmp >> 24) & 0x7); @@ -476,6 +588,7 @@ int sb600_probe_spi(struct pci_dev *dev) msg_pdbg(", DropOneClkOnRd/SpiClkGate=%i", (tmp >> 28) & 0x1); case CHIPSET_SB89XX: case CHIPSET_HUDSON234: + case CHIPSET_YANGTZE: msg_pdbg(", SpiBusy=%i", (tmp >> 31) & 0x1); default: break; } @@ -489,6 +602,7 @@ int sb600_probe_spi(struct pci_dev *dev) if (amd_gen >= CHIPSET_SB89XX) { tmp = mmio_readb(sb600_spibar + 0x1D); msg_pdbg("Using SPI_CS%d\n", tmp & 0x3); + /* FIXME: Handle SpiProtect* configuration on Yangtze. */ } /* Look for the SMBus device. */ @@ -536,7 +650,11 @@ int sb600_probe_spi(struct pci_dev *dev) if (handle_imc(dev) != 0) return ERROR_FATAL; - register_spi_programmer(&spi_programmer_sb600); + /* Starting with Yangtze the SPI controller got a bigger FIFO */ + if (amd_gen != CHIPSET_YANGTZE) + register_spi_programmer(&spi_programmer_sb600); + else + register_spi_programmer(&spi_programmer_yangtze); return 0; } -- Kind regards, Stefan Tauner

1 0

[PATCH 3/6] sbxxx: Cleanup.
by Stefan Tauner 10 Aug '13

10 Aug '13

- Move programmer definition to the top. - Rewrite array accesses to use indices instead of using pointer arithmetic. - Move length check and opcode extraction to a function. - Move IMC parameter handling into existing IMC handling function. - Split comparing and resetting the FIFO pointer. Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> --- sb600spi.c | 186 +++++++++++++++++++++++++++++-------------------------------- 1 file changed, 88 insertions(+), 98 deletions(-) diff --git a/sb600spi.c b/sb600spi.c index 2c1d400..ff7dbee 100644 --- a/sb600spi.c +++ b/sb600spi.c @@ -54,6 +54,22 @@ enum amd_chipset { }; static enum amd_chipset amd_gen = CHIPSET_AMD_UNKNOWN; +#define FIFO_SIZE_OLD 8 + +static int sb600_spi_send_command(struct flashctx *flash, unsigned int writecnt, unsigned int readcnt, + const unsigned char *writearr, unsigned char *readarr); + +static struct spi_programmer spi_programmer_sb600 = { + .type = SPI_CONTROLLER_SB600, + .max_data_read = FIFO_SIZE_OLD, + .max_data_write = FIFO_SIZE_OLD - 3, + .command = sb600_spi_send_command, + .multicommand = default_spi_send_multicommand, + .read = default_spi_read, + .write_256 = default_spi_write_256, + .write_aai = default_spi_write_aai, +}; + static void determine_generation(struct pci_dev *dev) { amd_gen = CHIPSET_AMD_UNKNOWN; @@ -133,38 +149,45 @@ static void reset_internal_fifo_pointer(void) static int compare_internal_fifo_pointer(uint8_t want) { - uint8_t tmp; - - tmp = mmio_readb(sb600_spibar + 0xd) & 0x07; - want &= 0x7; - if (want != tmp) { - msg_perr("FIFO pointer corruption! Pointer is %d, wanted %d\n", tmp, want); - msg_perr("Something else is accessing the flash chip and " - "causes random corruption.\nPlease stop all " - "applications and drivers and IPMI which access the " - "flash chip.\n"); + uint8_t have = mmio_readb(sb600_spibar + 0xd) & 0x07; + want %= FIFO_SIZE_OLD; + if (have != want) { + msg_perr("AMD SPI FIFO pointer corruption! Pointer is %d, wanted %d\n", have, want); + msg_perr("Something else is accessing the flash chip and causes random corruption.\n" + "Please stop all applications and drivers and IPMI which access the flash chip.\n"); return 1; } else { - msg_pspew("SB600 FIFO pointer is %d, wanted %d\n", tmp, want); + msg_pspew("AMD SPI FIFO pointer is %d, wanted %d\n", have, want); return 0; } } -static int reset_compare_internal_fifo_pointer(uint8_t want) +/* Check the number of bytes to be transmitted and extract opcode. */ +static int check_readwritecnt(struct flashctx *flash, unsigned int writecnt, unsigned int readcnt) { - int ret; + unsigned int maxwritecnt = flash->pgm->spi.max_data_write + 3; + if (writecnt > maxwritecnt) { + msg_pinfo("%s: SPI controller can not send %d bytes, it is limited to %d bytes\n", + __func__, writecnt, maxwritecnt); + return SPI_INVALID_LENGTH; + } - ret = compare_internal_fifo_pointer(want); - reset_internal_fifo_pointer(); - return ret; + unsigned int maxreadcnt = flash->pgm->spi.max_data_read + 3; + if (readcnt > maxreadcnt) { + msg_pinfo("%s: SPI controller can not receive %d bytes, it is limited to %d bytes\n", + __func__, readcnt, maxreadcnt); + return SPI_INVALID_LENGTH; + } + return 0; } static void execute_command(void) { + msg_pspew("Executing... "); mmio_writeb(mmio_readb(sb600_spibar + 2) | 1, sb600_spibar + 2); - while (mmio_readb(sb600_spibar + 2) & 1) ; + msg_pspew("done\n"); } static int sb600_spi_send_command(struct flashctx *flash, unsigned int writecnt, @@ -172,60 +195,45 @@ static int sb600_spi_send_command(struct flashctx *flash, unsigned int writecnt, const unsigned char *writearr, unsigned char *readarr) { - int count; - /* First byte is cmd which can not being sent through FIFO. */ + /* First byte is cmd which can not be sent through the FIFO. */ unsigned char cmd = *writearr++; - unsigned int readoffby1; - unsigned char readwrite; - writecnt--; + msg_pspew("%s, cmd=0x%02x, writecnt=%d, readcnt=%d\n", __func__, cmd, writecnt, readcnt); + mmio_writeb(cmd, sb600_spibar + 0); - msg_pspew("%s, cmd=%x, writecnt=%x, readcnt=%x\n", - __func__, cmd, writecnt, readcnt); - - if (readcnt > 8) { - msg_pinfo("%s, SB600 SPI controller can not receive %d bytes, " - "it is limited to 8 bytes\n", __func__, readcnt); - return SPI_INVALID_LENGTH; - } - - if (writecnt > 8) { - msg_pinfo("%s, SB600 SPI controller can not send %d bytes, " - "it is limited to 8 bytes\n", __func__, writecnt); - return SPI_INVALID_LENGTH; - } + int ret = check_readwritecnt(flash, writecnt, readcnt); + if (ret != 0) + return ret; - /* This is a workaround for a bug in SB600 and SB700. If we only send + /* This is a workaround for a bug in SPI controller. If we only send * an opcode and no additional data/address, the SPI controller will * read one byte too few from the chip. Basically, the last byte of * the chip response is discarded and will not end up in the FIFO. * It is unclear if the CS# line is set high too early as well. */ - readoffby1 = (writecnt) ? 0 : 1; - readwrite = (readcnt + readoffby1) << 4 | (writecnt); + unsigned int readoffby1 = (writecnt > 0) ? 0 : 1; + uint8_t readwrite = (readcnt + readoffby1) << 4 | (writecnt); mmio_writeb(readwrite, sb600_spibar + 1); - mmio_writeb(cmd, sb600_spibar + 0); - /* Before we use the FIFO, reset it first. */ reset_internal_fifo_pointer(); - - /* Send the write byte to FIFO. */ - msg_pspew("Writing: "); - for (count = 0; count < writecnt; count++, writearr++) { - msg_pspew("[%02x]", *writearr); - mmio_writeb(*writearr, sb600_spibar + 0xC); + msg_pspew("Filling FIFO: "); + int count; + for (count = 0; count < writecnt; count++) { + msg_pspew("[%02x]", writearr[count]); + mmio_writeb(writearr[count], sb600_spibar + 0xC); } msg_pspew("\n"); + if (compare_internal_fifo_pointer(writecnt)) + return SPI_PROGRAMMER_ERROR; /* - * We should send the data by sequence, which means we need to reset + * We should send the data in sequence, which means we need to reset * the FIFO pointer to the first byte we want to send. */ - if (reset_compare_internal_fifo_pointer(writecnt)) - return SPI_PROGRAMMER_ERROR; - - msg_pspew("Executing: \n"); + reset_internal_fifo_pointer(); execute_command(); + if (compare_internal_fifo_pointer(writecnt + readcnt)) + return SPI_PROGRAMMER_ERROR; /* * After the command executed, we should find out the index of the @@ -238,34 +246,30 @@ static int sb600_spi_send_command(struct flashctx *flash, unsigned int writecnt, * the opcode, the FIFO already stores the response from the chip. * Usually, the chip will respond with 0x00 or 0xff. */ - if (reset_compare_internal_fifo_pointer(writecnt + readcnt)) - return SPI_PROGRAMMER_ERROR; + reset_internal_fifo_pointer(); /* Skip the bytes we sent. */ msg_pspew("Skipping: "); for (count = 0; count < writecnt; count++) { - cmd = mmio_readb(sb600_spibar + 0xC); - msg_pspew("[%02x]", cmd); + msg_pspew("[%02x]", mmio_readb(sb600_spibar + 0xC)); } msg_pspew("\n"); if (compare_internal_fifo_pointer(writecnt)) return SPI_PROGRAMMER_ERROR; - msg_pspew("Reading: "); - for (count = 0; count < readcnt; count++, readarr++) { - *readarr = mmio_readb(sb600_spibar + 0xC); - msg_pspew("[%02x]", *readarr); + msg_pspew("Reading FIFO: "); + for (count = 0; count < readcnt; count++) { + readarr[count] = mmio_readb(sb600_spibar + 0xC); + msg_pspew("[%02x]", readarr[count]); } msg_pspew("\n"); - if (reset_compare_internal_fifo_pointer(readcnt + writecnt)) + if (compare_internal_fifo_pointer(writecnt+readcnt)) return SPI_PROGRAMMER_ERROR; if (mmio_readb(sb600_spibar + 1) != readwrite) { - msg_perr("Unexpected change in SB600 read/write count!\n"); - msg_perr("Something else is accessing the flash chip and " - "causes random corruption.\nPlease stop all " - "applications and drivers and IPMI which access the " - "flash chip.\n"); + msg_perr("Unexpected change in AMD SPI read/write count!\n"); + msg_perr("Something else is accessing the flash chip and causes random corruption.\n" + "Please stop all applications and drivers and IPMI which access the flash chip.\n"); return SPI_PROGRAMMER_ERROR; } @@ -327,12 +331,28 @@ static int handle_speed(struct pci_dev *dev) return set_speed(dev, &spispeeds[spispeed_idx]); } -static int sb600_handle_imc(struct pci_dev *dev, bool amd_imc_force) +static int handle_imc(struct pci_dev *dev) { /* Handle IMC everywhere but sb600 which does not have one. */ if (amd_gen == CHIPSET_SB6XX) return 0; + bool amd_imc_force = false; + char *arg = extract_programmer_param("amd_imc_force"); + if (arg && !strcmp(arg, "yes")) { + amd_imc_force = true; + msg_pspew("amd_imc_force enabled.\n"); + } else if (arg && !strlen(arg)) { + msg_perr("Missing argument for amd_imc_force.\n"); + free(arg); + return 1; + } else if (arg) { + msg_perr("Unknown argument for amd_imc_force: \"%s\" (not \"yes\").\n", arg); + free(arg); + return 1; + } + free(arg); + /* TODO: we should not only look at IntegratedImcPresent (LPC Dev 20, Func 3, 40h) but also at * IMCEnable(Strap) and Override EcEnable(Strap) (sb8xx, sb9xx?, a50: Misc_Reg: 80h-87h; * sb7xx, sp5100: PM_Reg: B0h-B1h) etc. */ @@ -360,38 +380,11 @@ static int sb600_handle_imc(struct pci_dev *dev, bool amd_imc_force) return amd_imc_shutdown(dev); } -static const struct spi_programmer spi_programmer_sb600 = { - .type = SPI_CONTROLLER_SB600, - .max_data_read = 8, - .max_data_write = 5, - .command = sb600_spi_send_command, - .multicommand = default_spi_send_multicommand, - .read = default_spi_read, - .write_256 = default_spi_write_256, - .write_aai = default_spi_write_aai, -}; - int sb600_probe_spi(struct pci_dev *dev) { struct pci_dev *smbus_dev; uint32_t tmp; uint8_t reg; - bool amd_imc_force = false; - - char *arg = extract_programmer_param("amd_imc_force"); - if (arg && !strcmp(arg, "yes")) { - amd_imc_force = true; - msg_pspew("amd_imc_force enabled.\n"); - } else if (arg && !strlen(arg)) { - msg_perr("Missing argument for amd_imc_force.\n"); - free(arg); - return ERROR_FATAL; - } else if (arg) { - msg_perr("Unknown argument for amd_imc_force: \"%s\" (not \"yes\").\n", arg); - free(arg); - return ERROR_FATAL; - } - free(arg); /* Read SPI_BaseAddr */ tmp = pci_read_long(dev, 0xa0); @@ -540,12 +533,9 @@ int sb600_probe_spi(struct pci_dev *dev) if (handle_speed(dev) != 0) return ERROR_FATAL; - if (sb600_handle_imc(dev, amd_imc_force) != 0) + if (handle_imc(dev) != 0) return ERROR_FATAL; - /* Bring the FIFO to a clean state. */ - reset_internal_fifo_pointer(); - register_spi_programmer(&spi_programmer_sb600); return 0; } -- Kind regards, Stefan Tauner

1 0

[PATCH 2/6] sbxxx: Set SPI clock to 16.5 MHz and disable fast reads.
by Stefan Tauner 10 Aug '13

10 Aug '13

Do not rely on broken firmware to set up the SPI configuration correctly. Some boards fail with flashrom because the firmware chose too high speeds for the alternate SPI mode which flashrom uses. Temporarily change the clock to the lowest common value of 16.5 MHz. Also, disable fast reads just to be safe. Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> --- sb600spi.c | 64 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++------ 1 file changed, 58 insertions(+), 6 deletions(-) diff --git a/sb600spi.c b/sb600spi.c index c9be44c..2c1d400 100644 --- a/sb600spi.c +++ b/sb600spi.c @@ -272,6 +272,61 @@ static int sb600_spi_send_command(struct flashctx *flash, unsigned int writecnt, return 0; } +struct spispeed { + const char *const name; + const int8_t speed; +}; + +static const struct spispeed spispeeds[] = { + { "66 MHz", 0x00 }, + { "33 MHz", 0x01 }, + { "22 MHz", 0x02 }, + { "16.5 MHz", 0x03 }, +}; + +static int set_speed(struct pci_dev *dev, const struct spispeed *spispeed) +{ + bool success = false; + uint8_t speed = spispeed->speed; + + msg_pdbg("Setting SPI clock to %s (0x%x).\n", spispeed->name, speed); + if (amd_gen != CHIPSET_YANGTZE) { + rmmio_writeb((mmio_readb(sb600_spibar + 0xd) & ~(0x3 << 4)) | (speed << 4), sb600_spibar + 0xd); + success = (speed == ((mmio_readb(sb600_spibar + 0xd) >> 4) & 0x3)); + } + + if (!success) { + msg_perr("Setting SPI clock failed.\n"); + return 1; + } + return 0; +} + +static int handle_speed(struct pci_dev *dev) +{ + uint32_t tmp; + int8_t spispeed_idx = 3; /* Default to 16.5 MHz */ + + /* bit 6xx 7xx/SP5100 8xx 9xx hudson1 hudson234 yangtze + * 18 rsvd <- fastReadEnable ? <- ? SpiReadMode[0] + * 29:30 rsvd <- <- ? <- ? SpiReadMode[2:1] + */ + if (amd_gen != CHIPSET_YANGTZE) { + if (amd_gen >= CHIPSET_SB89XX && amd_gen <= CHIPSET_HUDSON234) { + bool fast_read = (mmio_readl(sb600_spibar + 0x00) >> 18) & 0x1; + msg_pdbg("Fast Reads are %sabled\n", fast_read ? "en" : "dis"); + if (fast_read) { + msg_pdbg("Disabling them temporarily.\n"); + rmmio_writel(mmio_readl(sb600_spibar + 0x00) & ~(0x1 << 18), + sb600_spibar + 0x00); + } + } + tmp = (mmio_readb(sb600_spibar + 0xd) >> 4) & 0x3; + msg_pdbg("NormSpeed is %s\n", spispeeds[tmp].name); + } + return set_speed(dev, &spispeeds[spispeed_idx]); +} + static int sb600_handle_imc(struct pci_dev *dev, bool amd_imc_force) { /* Handle IMC everywhere but sb600 which does not have one. */ @@ -322,9 +377,6 @@ int sb600_probe_spi(struct pci_dev *dev) uint32_t tmp; uint8_t reg; bool amd_imc_force = false; - static const char *const speed_names[4] = { - "66/reserved", "33", "22", "16.5" - }; char *arg = extract_programmer_param("amd_imc_force"); if (arg && !strcmp(arg, "yes")) { @@ -441,9 +493,6 @@ int sb600_probe_spi(struct pci_dev *dev) return ERROR_NONFATAL; } - tmp = (mmio_readb(sb600_spibar + 0xd) >> 4) & 0x3; - msg_pdbg("NormSpeed is %s MHz\n", speed_names[tmp]); - if (amd_gen >= CHIPSET_SB89XX) { tmp = mmio_readb(sb600_spibar + 0x1D); msg_pdbg("Using SPI_CS%d\n", tmp & 0x3); @@ -488,6 +537,9 @@ int sb600_probe_spi(struct pci_dev *dev) return 0; } + if (handle_speed(dev) != 0) + return ERROR_FATAL; + if (sb600_handle_imc(dev, amd_imc_force) != 0) return ERROR_FATAL; -- Kind regards, Stefan Tauner

1 0

[PATCH 1/6] sbxxx: Add detection for the remaining AMD chipset families.
by Stefan Tauner 10 Aug '13

10 Aug '13

Also, correct prettyprinting of the registers of the various families, and abort if SpiAccessMacRomEn or SpiHostAccessRomEn prohibit full access. Tested reading/writing on ASRock IMB-A180, and chipset detection on one of each affected generation by Chris Goodrich from Sage. Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> --- sb600spi.c | 133 ++++++++++++++++++++++++++++++++++++++++++++++++------------- 1 file changed, 106 insertions(+), 27 deletions(-) diff --git a/sb600spi.c b/sb600spi.c index cb7c4ac..c9be44c 100644 --- a/sb600spi.c +++ b/sb600spi.c @@ -57,7 +57,28 @@ static enum amd_chipset amd_gen = CHIPSET_AMD_UNKNOWN; static void determine_generation(struct pci_dev *dev) { amd_gen = CHIPSET_AMD_UNKNOWN; - if (dev->device_id == 0x780e) { + msg_pdbg2("Trying to determine the generation of the SPI interface... "); + if (dev->device_id == 0x438d) { + amd_gen = CHIPSET_SB6XX; + msg_pdbg("SB6xx detected.\n"); + } else if (dev->device_id == 0x439d) { + struct pci_dev *smbus_dev = pci_dev_find(0x1002, 0x4385); + if (smbus_dev == NULL) + return; + uint8_t rev = pci_read_byte(smbus_dev, PCI_REVISION_ID); + if (rev >= 0x39 && rev <= 0x3D) { + amd_gen = CHIPSET_SB7XX; + msg_pdbg("SB7xx/SP5100 detected.\n"); + } else if (rev >= 0x40 && rev <= 0x42) { + amd_gen = CHIPSET_SB89XX; + msg_pdbg("SB8xx/SB9xx/Hudson-1 detected.\n"); + } else { + msg_pwarn("SB device found but SMBus revision 0x%02x does not match known values.\n" + "Assuming SB8xx/SB9xx/Hudson-1. Please send a log to flashrom(a)flashrom.org\n", + rev); + amd_gen = CHIPSET_SB89XX; + } + } else if (dev->device_id == 0x780e) { /* The PCI ID of the LPC bridge doesn't change between Hudson-2/3/4 and Yangtze (Kabini/Temash) * although they use different SPI interfaces. */ #ifdef USE_YANGTZE_HEURISTICS @@ -94,7 +115,11 @@ static void determine_generation(struct pci_dev *dev) "the output of lspci -nnvx, thanks!.\n", rev); } #endif - } + } else + msg_pwarn("%s: Unknown LPC device %" PRIx16 ":%" PRIx16 ".\n" + "Please report this to flashrom(a)flashrom.org and include this log and\n" + "the output of lspci -nnvx, thanks!\n", + __func__, dev->vendor_id, dev->device_id); } static void reset_internal_fifo_pointer(void) @@ -250,7 +275,7 @@ static int sb600_spi_send_command(struct flashctx *flash, unsigned int writecnt, static int sb600_handle_imc(struct pci_dev *dev, bool amd_imc_force) { /* Handle IMC everywhere but sb600 which does not have one. */ - if (dev->device_id == 0x438d) + if (amd_gen == CHIPSET_SB6XX) return 0; /* TODO: we should not only look at IntegratedImcPresent (LPC Dev 20, Func 3, 40h) but also at @@ -334,6 +359,12 @@ int sb600_probe_spi(struct pci_dev *dev) sb600_spibar += tmp & 0xfff; determine_generation(dev); + if (amd_gen == CHIPSET_AMD_UNKNOWN) { + /* FIXME: Eventually this should be a fatal error, but until we are certain to have covered all + * IDs actually found in the wild, try to mimmick the previous behavior. */ + msg_pwarn("Could not determine chipset generation. Assuming SB6xx."); + amd_gen = CHIPSET_SB6XX; + } if (amd_gen == CHIPSET_YANGTZE) { msg_perr("SPI on Kabini/Temash and newer chipsets are not yet supported.\n" @@ -341,35 +372,83 @@ int sb600_probe_spi(struct pci_dev *dev) return ERROR_NONFATAL; } - tmp = pci_read_long(dev, 0xa0); - msg_pdbg("AltSpiCSEnable=%i, SpiRomEnable=%i, " - "AbortEnable=%i\n", tmp & 0x1, (tmp & 0x2) >> 1, - (tmp & 0x4) >> 2); - tmp = (pci_read_byte(dev, 0xba) & 0x4) >> 2; - msg_pdbg("PrefetchEnSPIFromIMC=%i, ", tmp); - - tmp = pci_read_byte(dev, 0xbb); - /* FIXME: Set bit 3,6,7 if not already set. - * Set bit 5, otherwise SPI accesses are pointless in LPC mode. - * See doc 42413 AMD SB700/710/750 RPR. + /* Chipset support matrix for SPI Base_Addr (LPC PCI reg 0xa0) + * bit 6xx 7xx/SP5100 8xx 9xx hudson1 hudson2+ yangtze + * 3 rsvd <- <- ? <- ? RouteTpm2Spi + * 2 rsvd AbortEnable rsvd ? <- ? <- + * 1 rsvd SpiRomEnable <- ? <- ? <- + * 0 rsvd AltSpiCSEnable<1> rsvd ? <- ? <- + * + * <1> It is unknown if that was ever working. On later chipsets the CS config is at memmapped 0x1D. */ - msg_pdbg("PrefetchEnSPIFromHost=%i, SpiOpEnInLpcMode=%i\n", - tmp & 0x1, (tmp & 0x20) >> 5); - tmp = mmio_readl(sb600_spibar); - /* FIXME: If SpiAccessMacRomEn or SpiHostAccessRomEn are zero on - * SB700 or later, reads and writes will be corrupted. Abort in this - * case. Make sure to avoid this check on SB600. + if (amd_gen >= CHIPSET_SB7XX) { + tmp = pci_read_long(dev, 0xa0); + msg_pdbg("SpiRomEnable=%i", (tmp >> 1) & 0x1); + if (amd_gen == CHIPSET_SB7XX) + msg_pdbg(", AltSpiCSEnable=%i, AbortEnable=%i", tmp & 0x1, (tmp >> 2) & 0x1); + + tmp = pci_read_byte(dev, 0xba); + msg_pdbg(", PrefetchEnSPIFromIMC=%i", (tmp & 0x4) >> 2); + + tmp = pci_read_byte(dev, 0xbb); + /* FIXME: Set bit 3,6,7 if not already set. + * Set bit 5, otherwise SPI accesses are pointless in LPC mode. + * See doc 42413 AMD SB700/710/750 RPR. + */ + if (amd_gen == CHIPSET_SB7XX) + msg_pdbg(", SpiOpEnInLpcMode=%i", (tmp >> 5) & 0x1); + msg_pdbg(", PrefetchEnSPIFromHost=%i\n", tmp & 0x1); + } + + /* Chipset support matrix for SPI_Cntrl0 (spibar + 0x0) + * bit 6xx 7xx/SP5100 8xx 9xx hudson1 hudson2+ yangtze + * 17 rsvd <- <- ? <- ? <- + * 18 rsvd <- fastReadEnable<1> ? <- ? SpiReadMode[0]<1> + * 19 SpiArbEnable <- <- ? <- ? <- + * 20 (FifoPtrClr) <- <- ? <- ? <- + * 21 (FifoPtrInc) <- <- ? <- ? IllegalAccess + * 22 SpiAccessMacRomEn <- <- ? <- ? <- + * 23 SpiHostAccessRomEn <- <- ? <- ? <- + * 24:26 ArbWaitCount <- <- ? <- ? <- + * 27 SpiBridgeDisable <- <- ? <- ? rsvd + * 28 rsvd DropOneClkOnRd = SPIClkGate ? <- ? <- + * 29:30 rsvd <- <- ? <- ? SpiReadMode[2:1]<1> + * 31 rsvd <- SpiBusy ? <- ? <- + * + * <1> see handle_speed */ - msg_pdbg("(0x%08" PRIx32 ") fastReadEnable=%u, SpiArbEnable=%i, SpiAccessMacRomEn=%i, " - "SpiHostAccessRomEn=%i, ArbWaitCount=%i, " - "SpiBridgeDisable=%i, DropOneClkOnRd=%i\n", - tmp, (tmp >> 18) & 0x1, - (tmp >> 19) & 0x1, (tmp >> 22) & 0x1, - (tmp >> 23) & 0x1, (tmp >> 24) & 0x7, - (tmp >> 27) & 0x1, (tmp >> 28) & 0x1); + tmp = mmio_readl(sb600_spibar + 0x00); + msg_pdbg("(0x%08" PRIx32 ") SpiArbEnable=%i", tmp, (tmp >> 19) & 0x1); + + msg_pdbg(", SpiAccessMacRomEn=%i, SpiHostAccessRomEn=%i, ArbWaitCount=%i", + (tmp >> 22) & 0x1, (tmp >> 23) & 0x1, (tmp >> 24) & 0x7); + + if (amd_gen != CHIPSET_YANGTZE) + msg_pdbg(", SpiBridgeDisable=%i", (tmp >> 27) & 0x1); + + switch (amd_gen) { + case CHIPSET_SB7XX: + msg_pdbg(", DropOneClkOnRd/SpiClkGate=%i", (tmp >> 28) & 0x1); + case CHIPSET_SB89XX: + case CHIPSET_HUDSON234: + msg_pdbg(", SpiBusy=%i", (tmp >> 31) & 0x1); + default: break; + } + msg_pdbg("\n"); + + if (((tmp >> 22) & 0x1) == 0 || ((tmp >> 23) & 0x1) == 0) { + msg_perr("ERROR: State of SpiAccessMacRomEn or SpiHostAccessRomEn prohibits full access.\n"); + return ERROR_NONFATAL; + } + tmp = (mmio_readb(sb600_spibar + 0xd) >> 4) & 0x3; msg_pdbg("NormSpeed is %s MHz\n", speed_names[tmp]); + if (amd_gen >= CHIPSET_SB89XX) { + tmp = mmio_readb(sb600_spibar + 0x1D); + msg_pdbg("Using SPI_CS%d\n", tmp & 0x3); + } + /* Look for the SMBus device. */ smbus_dev = pci_dev_find(0x1002, 0x4385); if (!smbus_dev) { -- Kind regards, Stefan Tauner

1 0

[PATCH 0/6] sbxxx patches 2.0
by Stefan Tauner 10 Aug '13

10 Aug '13

I completely rewrote it *again* :) Apparently the SPI 100 controller in Yangtze is quite different to the existing interface. I spend quite some time on figuring out why the FIFO ring buffer does not seem to work: my diagnose is that it is not a ring buffer at all. I have no idea why they call it FIFO either... we have full indexed access to it. Whatever... these patches should work fine on Kabini (tested on the A180-H). Tests on any other board especially older generations are very welcomed! Stefan Tauner (6): sbxxx: Add detection for the remaining AMD chipset families. sbxxx: Set SPI clock to 16.5 MHz and disable fast reads. sbxxx: Cleanup. sbxxx: Add support for new AMD SPI controller. sbxxx: Add spispeed parameter. debug flashrom.8 | 21 +++ programmer.h | 1 + sb600spi.c | 538 ++++++++++++++++++++++++++++++++++++++++++++--------------- 3 files changed, 424 insertions(+), 136 deletions(-) -- Kind regards, Stefan Tauner

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

2012

2011

2010

2009

flashrom August 2013