flashrom August 2013

flashrom@flashrom.org

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169 discussions

ECS G41T-M7 flashrom -V output log
by Olcay Korkmaz 09 Aug '13

09 Aug '13

Hello, flashrom v0.9.6.1-r1564 on Linux 3.8.0-28-generic (x86_64) flashrom was built with libpci 3.1.9, GCC 4.7.3, little endian Command line (5 args): ./flashrom -p internal -V -o g41t.txt Calibrating delay loop... OS timer resolution is 1 usecs, 2770M loops per second, 10 myus = 11 us, 100 myus = 99 us, 1000 myus = 1001 us, 10000 myus = 9992 us, 4 myus = 5 us, OK. Initializing internal programmer No coreboot table found. DMI string system-manufacturer: "ECS" DMI string system-product-name: "G41T-M7" DMI string system-version: "1.0" DMI string baseboard-manufacturer: "ECS" DMI string baseboard-product-name: "G41T-M7" DMI string baseboard-version: "1.0" DMI string chassis-type: "Desktop" Found ITE Super I/O, ID 0x8718 on port 0x2e Found chipset "Intel ICH7/ICH7R" with PCI ID 8086:27b8. Enabling flash write... 0xfff80000/0xffb80000 FWH IDSEL: 0x0 0xfff00000/0xffb00000 FWH IDSEL: 0x0 0xffe80000/0xffa80000 FWH IDSEL: 0x1 0xffe00000/0xffa00000 FWH IDSEL: 0x1 0xffd80000/0xff980000 FWH IDSEL: 0x2 0xffd00000/0xff900000 FWH IDSEL: 0x2 0xffc80000/0xff880000 FWH IDSEL: 0x3 0xffc00000/0xff800000 FWH IDSEL: 0x3 0xff700000/0xff300000 FWH IDSEL: 0x4 0xff600000/0xff200000 FWH IDSEL: 0x5 0xff500000/0xff100000 FWH IDSEL: 0x6 0xff400000/0xff000000 FWH IDSEL: 0x7 0xfff80000/0xffb80000 FWH decode enabled 0xfff00000/0xffb00000 FWH decode enabled 0xffe80000/0xffa80000 FWH decode disabled 0xffe00000/0xffa00000 FWH decode disabled 0xffd80000/0xff980000 FWH decode disabled 0xffd00000/0xff900000 FWH decode disabled 0xffc80000/0xff880000 FWH decode disabled 0xffc00000/0xff800000 FWH decode disabled 0xff700000/0xff300000 FWH decode disabled 0xff600000/0xff200000 FWH decode disabled 0xff500000/0xff100000 FWH decode disabled 0xff400000/0xff000000 FWH decode disabled Maximum FWH chip size: 0x100000 bytes BIOS Lock Enable: disabled, BIOS Write Enable: disabled, BIOS_CNTL is 0x0 Root Complex Register Block address = 0xfed1c000 GCS = 0x240464: BIOS Interface Lock-Down: disabled, Boot BIOS Straps: 0x1 (SPI) Top Swap : not enabled SPIBAR = 0xfed1c000 + 0x3020 0x00: 0x0004 (SPIS) 0x02: 0x4140 (SPIC) 0x04: 0x00000000 (SPIA) 0x08: 0x000020c2 (SPID0) 0x0c: 0x00000000 (SPID0+4) 0x10: 0x00000000 (SPID1) 0x14: 0x00000000 (SPID1+4) 0x18: 0x00000000 (SPID2) 0x1c: 0x00000000 (SPID2+4) 0x20: 0x00000000 (SPID3) 0x24: 0x00000000 (SPID3+4) 0x28: 0x00000000 (SPID4) 0x2c: 0x00000000 (SPID4+4) 0x30: 0x00000000 (SPID5) 0x34: 0x00000000 (SPID5+4) 0x38: 0x00000000 (SPID6) 0x3c: 0x00000000 (SPID6+4) 0x40: 0x00000000 (SPID7) 0x44: 0x00000000 (SPID7+4) 0x50: 0x00000000 (BBAR) 0x54: 0x0004 (PREOP) 0x56: 0x543b (OPTYPE) 0x58: 0x05d80302 (OPMENU) 0x5c: 0x0006019f (OPMENU+4) 0x60: 0x00000000 (PBR0) 0x64: 0x00000000 (PBR1) 0x68: 0x00000000 (PBR2) Programming OPCODES... program_opcodes: preop=5006 optype=463b opmenu=05d80302c79f0190 done OP Type Pre-OP op[0]: 0x02, write w/ addr, none op[1]: 0x03, read w/ addr, none op[2]: 0xd8, write w/ addr, none op[3]: 0x05, read w/o addr, none op[4]: 0x90, read w/ addr, none op[5]: 0x01, write w/o addr, none op[6]: 0x9f, read w/o addr, none op[7]: 0xc7, write w/o addr, none Pre-OP 0: 0x06, Pre-OP 1: 0x50 SPI Read Configuration: prefetching disabled, caching enabled, OK. No IT87* serial flash segment enabled. The following protocols are supported: SPI. Probing for AMIC A25L05PT, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L05PU, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L10PT, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L10PU, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L20PT, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L20PU, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L40PT, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L40PU, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L80P, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L16PT, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L16PU, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L512, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L010, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L020, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L040, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L080, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L016, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L032, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25LQ032, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT25DF021, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT25DF041A, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT25DF081, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT25DF081A, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT25DF161, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT25DF321, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT25DF321A, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT25DF641(A), 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT25DQ161, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT25F512B, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT25FS010, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT25FS040, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT26DF041, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT26DF081A, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT26DF161, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT26DF161A, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT26F004, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT45CS1282, 16896 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT45DB011D, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT45DB021D, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT45DB041D, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT45DB081D, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT45DB161D, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT45DB321C, 4224 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT45DB321D, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT45DB642D, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for EMST F25L008A, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B05, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B05T, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B10, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B10T, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B20, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B20T, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B40, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B40T, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B80, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B80T, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B16T, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B32, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B32T, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B64, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B64T, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25F05, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25F10, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25F20, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25F40, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25F80, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25F16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25F32, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25Q40, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25Q80(A), 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25Q16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25Q32(A/B), 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25Q64, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25Q128, 16384 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25QH16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25QH32, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for GigaDevice GD25Q20, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for GigaDevice GD25Q40, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for GigaDevice GD25Q80, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for GigaDevice GD25Q16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for GigaDevice GD25Q32, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for GigaDevice GD25Q64, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for GigaDevice GD25Q128, 16384 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Macronix MX25L512, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Macronix MX25L1005, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Macronix MX25L2005, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Macronix MX25L4005, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Macronix MX25L8005, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Chip status register is 00 Chip status register: Status Register Write Disable (SRWD) is not set Chip status register: Bit 6 is not set Chip status register: Block Protect 3 (BP3) is not set Chip status register: Block Protect 2 (BP2) is not set Chip status register: Block Protect 1 (BP1) is not set Chip status register: Block Protect 0 (BP0) is not set Chip status register: Write Enable Latch (WEL) is not set Chip status register: Write In Progress (WIP/BUSY) is not set Found Macronix flash chip "MX25L8005" (1024 kB, SPI) at physical address 0xfff00000. Probing for Macronix MX25L1605, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Macronix MX25L1635D, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Macronix MX25L1635E, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Macronix MX25L3205, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Macronix MX25L3235D, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Macronix MX25L6405, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Macronix MX25L12805, 16384 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Numonyx M25PE10, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Numonyx M25PE20, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Numonyx M25PE40, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Numonyx M25PE80, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Numonyx M25PE16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Numonyx N25Q064, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for PMC Pm25LV010, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for PMC Pm25LV016B, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for PMC Pm25LV020, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for PMC Pm25LV040, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for PMC Pm25LV080B, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for PMC Pm25LV512, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Sanyo LF25FW203A, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Spansion S25FL004A, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Spansion S25FL008A, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Spansion S25FL016A, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Spansion S25FL032A, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Spansion S25FL064A, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for SST SST25LF040A, 512 kB: program_opcodes: preop=5006 optype=462b opmenu=05ab0302c79f0190 on-the-fly OPCODE (0xAB) re-programmed, op-pos=2 probe_spi_res2: id1 0x13, id2 0x13 Probing for SST SST25LF080A, 1024 kB: probe_spi_res2: id1 0x13, id2 0x13 Probing for SST SST25VF010, 128 kB: probe_spi_rems: id1 0xc2, id2 0x13 Probing for SST SST25VF016B, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for SST SST25VF032B, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for SST SST25VF064C, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for SST SST25VF040, 512 kB: probe_spi_rems: id1 0xc2, id2 0x13 Probing for SST SST25VF040B, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for SST SST25VF040B.REMS, 512 kB: probe_spi_rems: id1 0xc2, id2 0x13 Probing for SST SST25VF080B, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for ST M25P05-A, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for ST M25P05, 64 kB: Ignoring RES in favour of RDID. Probing for ST M25P10-A, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for ST M25P10, 128 kB: Ignoring RES in favour of RDID. Probing for ST M25P20, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for ST M25P40, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for ST M25P40-old, 512 kB: Ignoring RES in favour of RDID. Probing for ST M25P80, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for ST M25P16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for ST M25P32, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for ST M25P64, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for ST M25P128, 16384 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for ST M25PX16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for ST M25PX32, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for ST M25PX64, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Winbond W25Q80, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Winbond W25Q16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Winbond W25Q32, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Winbond W25Q64, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Winbond W25Q128, 16384 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Winbond W25X10, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Winbond W25X20, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Winbond W25X40, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Winbond W25X80, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Winbond W25X16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Winbond W25X32, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Winbond W25X64, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Unknown SFDP-capable chip, 0 kB: program_opcodes: preop=5006 optype=462b opmenu=055a0302c79f0190 on-the-fly OPCODE (0x5A) re-programmed, op-pos=2 SFDP revision = 1.0 SFDP number of parameter headers is 3 (NPH = 2). SFDP parameter table header 0/2: ID 0x00, version 1.0 Length 8 B, Parameter Table Pointer 0x000020 Length of the mandatory JEDEC SFDP parameter table is wrong (8 B), skipping it. SFDP parameter table header 1/2: ID 0x01, version 1.0 Length 1020 B, Parameter Table Pointer 0xffffff SFDP Parameter Table 1 supposedly overflows addressable SFDP area. This most probably indicates a corrupt SFDP parameter table header. Skipping it. SFDP parameter table header 2/2: ID 0x02, version 1.0 Length 8 B, Parameter Table Pointer 0x000030 Probing for AMIC unknown AMIC SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel unknown Atmel SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon unknown Eon SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Macronix unknown Macronix SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for PMC unknown PMC SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for SST unknown SST SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for ST unknown ST SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Sanyo unknown Sanyo SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Generic unknown SPI chip (RDID), 0 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Generic unknown SPI chip (REMS), 0 kB: probe_spi_rems: id1 0xc2, id2 0x13 Found Macronix flash chip "MX25L8005" (1024 kB, SPI). No operations were specified. Restoring MMIO space at 0x7f73669c2070 Restoring MMIO space at 0x7f73669c207c Restoring MMIO space at 0x7f73669c2078 Restoring MMIO space at 0x7f73669c2076 Restoring MMIO space at 0x7f73669c2074 Restoring PCI config space for 00:1f:0 reg 0xdc -- Olcay K.

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Re: [flashrom] [PATCH 3/4] sbxxx: Add support for new AMD SPI controller.
by Stefan Tauner 09 Aug '13

09 Aug '13

On Fri, 9 Aug 2013 12:59:03 -0700 Wei Hu <wei(a)aristanetworks.com> wrote: > Stefan, > > I pulled your latest code from > https://github.com/stefanct/flashrom/tree/amd. However it's still > reading bad bits at 16.5 MHz. Here's a log from -VV trying to erase > the flash. yes, it is... because I am using the FIFO as ring buffer, but apparently the hardware does not wrap. I am testing this right now because I still don't want to believe that any engineer would build a 71 B long buffer that does not wrap for this kind of application... The fix is rather easy, but it is address length-specific and hence inelegant :) -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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Re: [flashrom] [PATCH 3/4] sbxxx: Add support for new AMD SPI controller.
by Stefan Tauner 09 Aug '13

09 Aug '13

On Fri, 9 Aug 2013 00:22:05 -0700 Wei Hu <wei(a)aristanetworks.com> wrote: > On Thu, Aug 8, 2013 at 11:41 PM, Stefan Tauner > <stefan.tauner(a)student.tuwien.ac.at> wrote: > >> 1. Your patch defaults SPI clock to 16.5 MHz, which didn't work. I > >> also found none of 22, 33, 100 MHz worked. Only passing -p > >> internal:spispeed="66 MHz" worked. > > > > Please be more specific and/or attach logs. Did the parsing of the > > value not work or did the actual register changes not work? > > Will attach logs tomorrow when I get to work. To make parsing work I > had to pass values in quotes like "66 MHz" etc. because you were > matching the full name. After figuring this part out the actual > register changes failed at > msg_perr("Setting SPI clock failed.\n"); I have figured it out... I have used the wrong integer types most of the time, sorry. I have this fixed locally, but want to test it more and review the whole thing before sending another such nightmare :) But I can send you the fix in private if you need it faster than that. The change that requires to use quotes now was necessary because of the addition of the "800 kHz" value in Yangtze. Eventually we will add a generic frequency parser, but until then please just use the quotes. -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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Re: [flashrom] [PATCH 3/4] sbxxx: Add support for new AMD SPI controller.
by Stefan Tauner 09 Aug '13

09 Aug '13

On Thu, 8 Aug 2013 17:15:01 -0700 Wei Hu <wei(a)aristanetworks.com> wrote: > Thanks for your great work. I just tested it on AMD Olive Hill, and > found a few issues. > > 1. Your patch defaults SPI clock to 16.5 MHz, which didn't work. I > also found none of 22, 33, 100 MHz worked. Only passing -p > internal:spispeed="66 MHz" worked. Please be more specific and/or attach logs. Did the parsing of the value not work or did the actual register changes not work? > 2. Reading is much faster than my/Carl's patch, but some bits were > incorrect. The speedup must have come from your use of the now longer > FIFO, but why is it reading bad values? Yes, the speedup is from the new FIFO, and I think your problems stems from the 66 MHz. -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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Re: [flashrom] [PATCH 3/4] sbxxx: Add support for new AMD SPI controller.
by Wei Hu 08 Aug '13

08 Aug '13

It looks like running your patch disturbed the SPI controller's internal state. I'm not able to write to flash using either your patch or the old patch now, as during chip erasing, flashrom expected 0xff but read something else. On Thu, Aug 8, 2013 at 5:15 PM, Wei Hu <wei(a)aristanetworks.com> wrote: > Stefan, > > Thanks for your great work. I just tested it on AMD Olive Hill, and > found a few issues. > > 1. Your patch defaults SPI clock to 16.5 MHz, which didn't work. I > also found none of 22, 33, 100 MHz worked. Only passing -p > internal:spispeed="66 MHz" worked. > > 2. Reading is much faster than my/Carl's patch, but some bits were > incorrect. The speedup must have come from your use of the now longer > FIFO, but why is it reading bad values?

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Re: [flashrom] [PATCH 3/4] sbxxx: Add support for new AMD SPI controller.
by Wei Hu 08 Aug '13

08 Aug '13

Stefan, Thanks for your great work. I just tested it on AMD Olive Hill, and found a few issues. 1. Your patch defaults SPI clock to 16.5 MHz, which didn't work. I also found none of 22, 33, 100 MHz worked. Only passing -p internal:spispeed="66 MHz" worked. 2. Reading is much faster than my/Carl's patch, but some bits were incorrect. The speedup must have come from your use of the now longer FIFO, but why is it reading bad values?

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Re: [flashrom] [PATCH 3/4] sbxxx: Add support for new AMD SPI controller.
by Wei Hu 08 Aug '13

08 Aug '13

On Thu, Aug 8, 2013 at 3:55 PM, Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> wrote: > + /* Starting with Yangtze the SPI controller got a bigger FIFO */ > + if (amd_gen == CHIPSET_YANGTZE) { > + spi_programmer_sb600.max_data_read = 71; > + spi_programmer_sb600.max_data_read = 71 - 3; > + } Wow this looks great! What are you doing here? Also, can we increase max_data_write?

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[PATCH 4/4] sbxxx: Add spispeed parameter.
by Stefan Tauner 08 Aug '13

08 Aug '13

TODO: manpage + commit message Allow to set the SPI clock frequency on SB600 et al. with a programmer parameter. If the parameter is given (and matches a possible value), the SPI clock is set temporarily. Both registers are restored on programmer shutdown. Example: ./flashrom -p internal:spispeed="33 MHz" -V Possible values for spispeed are "66/reserved", "33", "22", "16.5". Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> --- flashrom.8 | 14 ++++++++++++++ sb600spi.c | 32 ++++++++++++++++++++++++++++++++ 2 files changed, 46 insertions(+) diff --git a/flashrom.8 b/flashrom.8 index dccfd1a..8b5e09c 100644 --- a/flashrom.8 +++ b/flashrom.8 @@ -345,6 +345,20 @@ syntax. The user is responsible for supplying a suitable image or leaving out th a layout file. This limitation might be removed in the future when we understand the details better and have received enough feedback from users. Please report the outcome if you had to use this option to write a chip. .sp +An optional +.B spispeed +parameter specifies the frequency of the SPI bus where applicable (i.e.\& SB600 or later with SPI flash chip +directly attached to the chipset). +Syntax is +.sp +.B " flashrom \-p internal:spispeed=frequency" +.sp +where +.B frequency +can be +.BR 16.5 ", " 22 ", " 33 " or " 66/reserved " +(in MHz). The default is to not change the preset value. The use of this parameter also disables Fast Reads. +.sp .TP .B Intel chipsets .sp diff --git a/sb600spi.c b/sb600spi.c index 98238c2..330ad9a 100644 --- a/sb600spi.c +++ b/sb600spi.c @@ -350,6 +350,29 @@ static int handle_speed(struct pci_dev *dev) uint8_t tmp; uint8_t spispeed_idx = 3; /* Default to 16.5 MHz */ + char *spispeed = extract_programmer_param("spispeed"); + if (spispeed != NULL) { + if (strcasecmp(spispeed, "reserved") != 0) { + int i; + for (i = 0; i < ARRAY_SIZE(spispeeds); i++) { + if (strcasecmp(spispeeds[i].name, spispeed) == 0) { + spispeed_idx = i; + break; + } + } + /* Only Yangtze supports the second half of indices; no 66 MHz before SB8xx. */ + if ((amd_gen < CHIPSET_YANGTZE && spispeed_idx > 3) || + (amd_gen < CHIPSET_SB89XX && spispeed_idx == 0)) + spispeed_idx = -1; + } + if (spispeed_idx < 0) { + msg_perr("Error: Invalid spispeed value: '%s'.\n", spispeed); + free(spispeed); + return 1; + } + free(spispeed); + } + /* bit 6xx 7xx/SP5100 8xx 9xx hudson1 hudson234 yangtze * 18 rsvd <- fastReadEnable ? <- ? SpiReadMode[0] * 29:30 rsvd <- <- ? <- ? SpiReadMode[2:1] @@ -370,6 +393,15 @@ static int handle_speed(struct pci_dev *dev) msg_pdbg("SpiReadMode=%s (%i)\n", spireadmodes[read_mode], read_mode); tmp = mmio_readb(sb600_spibar + 0x20); msg_pdbg("UseSpi100 is %sabled\n", (tmp & 0x1) ? "en" : "dis"); + if ((tmp & 0x1) == 0) { + mmio_writeb(tmp | 0x1, sb600_spibar + 0x20); + tmp = mmio_readb(sb600_spibar + 0x20) & 0x1; + if (tmp == 0) { + msg_perr("Enabling Spi100 failed.\n"); + return 1; + } + msg_pdbg("Enabling Spi100 succeeded.\n"); + } tmp = mmio_readw(sb600_spibar + 0x22); /* SPI100 Speed Config */ msg_pdbg("NormSpeedNew is %s\n", spispeeds[(tmp >> 12) & 0xf].name); msg_pdbg("FastSpeedNew is %s\n", spispeeds[(tmp >> 8) & 0xf].name); -- Kind regards, Stefan Tauner

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[PATCH 3/4] sbxxx: Add support for new AMD SPI controller.
by Stefan Tauner 08 Aug '13

08 Aug '13

This patch adds support for the "SPI 100" SPI engine in Yangtze FCHs (found in Kabini and Temash). BTW it also rewrites sb600spi.c completely. Tested reading/writing on ASRock IMB-A180. Signed-off-by: Wei Hu <wei(a)aristanetworks.com> Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> --- sb600spi.c | 349 ++++++++++++++++++++++++++++++++++++------------------------- 1 file changed, 208 insertions(+), 141 deletions(-) diff --git a/sb600spi.c b/sb600spi.c index 9ab7a58..98238c2 100644 --- a/sb600spi.c +++ b/sb600spi.c @@ -4,7 +4,8 @@ * Copyright (C) 2008 Wang Qingpei <Qingpei.Wang(a)amd.com> * Copyright (C) 2008 Joe Bao <Zheng.Bao(a)amd.com> * Copyright (C) 2008 Advanced Micro Devices, Inc. - * Copyright (C) 2009, 2010 Carl-Daniel Hailfinger + * Copyright (C) 2009, 2010, 2013 Carl-Daniel Hailfinger + * Copyright (C) 2013 Stefan Tauner * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -131,40 +132,148 @@ static void reset_internal_fifo_pointer(void) msg_pspew("reset\n"); } +static int check_internal_fifo_pointer(uint8_t have, uint8_t want) +{ + if (have != want) { + msg_perr("AMD SPI FIFO pointer corruption! Pointer is %d, wanted %d\n", have, want); + msg_perr("Something else is accessing the flash chip and causes random corruption.\n" + "Please stop all applications and drivers and IPMI which access the flash chip.\n"); + return 1; + } + msg_pspew("AMD SPI FIFO pointer is %d, wanted %d\n", have, want); + return 0; +} + + static int compare_internal_fifo_pointer(uint8_t want) { - uint8_t tmp; + uint8_t tmp = mmio_readb(sb600_spibar + 0xd) & 0x7; + want &= 0x7; /* Modulo FIFO length */ + return check_internal_fifo_pointer(tmp, want); +} - tmp = mmio_readb(sb600_spibar + 0xd) & 0x07; - want &= 0x7; - if (want != tmp) { - msg_perr("FIFO pointer corruption! Pointer is %d, wanted %d\n", tmp, want); - msg_perr("Something else is accessing the flash chip and " - "causes random corruption.\nPlease stop all " - "applications and drivers and IPMI which access the " - "flash chip.\n"); - return 1; +/* Check and set the number of bytes to be transmitted. */ +static int set_bytecounts(unsigned int writecnt, unsigned int readcnt) +{ + unsigned int maxwritecnt, maxreadcnt; + + if (amd_gen >= CHIPSET_YANGTZE) + maxreadcnt = maxwritecnt = 70; + else + maxreadcnt = maxwritecnt = 8; + + if (writecnt > maxwritecnt) { + msg_pinfo("%s: SPI controller can not send %d bytes, it is limited to %d bytes\n", + __func__, writecnt, maxwritecnt); + return SPI_INVALID_LENGTH; + } + + if (readcnt > maxreadcnt) { + msg_pinfo("%s: SPI controller can not receive %d bytes, it is limited to %d bytes\n", + __func__, readcnt, maxreadcnt); + return SPI_INVALID_LENGTH; + } + + if (amd_gen >= CHIPSET_YANGTZE) { + /* Use the extended TxByteCount and RxByteCount register (and the bigger FIFO later). */ + mmio_writeb(writecnt, sb600_spibar + 0x48); + mmio_writeb(readcnt, sb600_spibar + 0x4b); } else { - msg_pspew("SB600 FIFO pointer is %d, wanted %d\n", tmp, want); - return 0; + /* This is a workaround for a bug in SB600 and SB700. If we only send + * an opcode and no additional data/address, the SPI controller will + * read one byte too few from the chip. Basically, the last byte of + * the chip response is discarded and will not end up in the FIFO. + * It is unclear if the CS# line is set high too early as well. + */ + unsigned int readoffby1 = (writecnt) ? 0 : 1; + uint8_t readwrite = (readcnt + readoffby1) << 4 | (writecnt); + mmio_writeb(readwrite, sb600_spibar + 1); } + return 0; } -static int reset_compare_internal_fifo_pointer(uint8_t want) +static int fill_fifo(const uint8_t *writearr, unsigned int writecnt) { - int ret; - - ret = compare_internal_fifo_pointer(want); - reset_internal_fifo_pointer(); - return ret; + int count; + if (amd_gen >= CHIPSET_YANGTZE) { + msg_pspew("Filling FIFO: "); + for (count = 0; count < writecnt; count++) { + msg_pspew("[%02x]", writearr[count]); + mmio_writeb(writearr[count], sb600_spibar + 0x80 + count); + } + msg_pspew("\n"); + } else { + reset_internal_fifo_pointer(); + msg_pspew("Filling FIFO: "); + for (count = 0; count < writecnt; count++) { + msg_pspew("[%02x]", writearr[count]); + mmio_writeb(writearr[count], sb600_spibar + 0xC); + } + msg_pspew("\n"); + if (compare_internal_fifo_pointer(writecnt)) + return SPI_PROGRAMMER_ERROR; + } + return 0; } -static void execute_command(void) +static int execute_command(unsigned int writecnt, unsigned int readcnt) { + /* + * We should send the data in sequence, which means we need to reset + * the FIFO pointer to the first byte we want to send. + */ + reset_internal_fifo_pointer(); + msg_pspew("Executing... \n"); mmio_writeb(mmio_readb(sb600_spibar + 2) | 1, sb600_spibar + 2); - while (mmio_readb(sb600_spibar + 2) & 1) ; + msg_pspew("done\n"); + if (compare_internal_fifo_pointer(writecnt + readcnt)) + return SPI_PROGRAMMER_ERROR; + return 0; +} + +static int read_fifo(int skip, uint8_t *data, int len) +{ + int count; + if (amd_gen >= CHIPSET_YANGTZE) { + msg_pspew("Reading: "); + for (count = 0; count < len; count++) { + data[count] = mmio_readb(sb600_spibar + 0x80 + (skip + count) % 70); + msg_pspew("[%02x]", data[count]); + } + } else { + /* + * After the command executed, we should find out the index of the + * received byte. Here we just reset the FIFO pointer and skip the + * writecnt. + * It would be possible to increase the FIFO pointer by one instead + * of reading and discarding one byte from the FIFO. + * The FIFO is implemented on top of an 8 byte ring buffer and the + * buffer is never cleared. For every byte that is shifted out after + * the opcode, the FIFO already stores the response from the chip. + * Usually, the chip will respond with 0x00 or 0xff. + */ + reset_internal_fifo_pointer(); + + msg_pspew("Skipping: "); + for (count = 0; count < skip; count++) { + msg_pspew("[%02x]", mmio_readb(sb600_spibar + 0xC)); + } + msg_pspew("\n"); + if (compare_internal_fifo_pointer(skip)) + return SPI_PROGRAMMER_ERROR; + + msg_pspew("Reading: "); + for (count = 0; count < len; count++) { + data[count] = mmio_readb(sb600_spibar + 0xC); + msg_pspew("[%02x]", data[count]); + } + msg_pspew("\n"); + if (compare_internal_fifo_pointer(skip+len)) + return SPI_PROGRAMMER_ERROR; + } + return 0; } static int sb600_spi_send_command(struct flashctx *flash, unsigned int writecnt, @@ -172,102 +281,27 @@ static int sb600_spi_send_command(struct flashctx *flash, unsigned int writecnt, const unsigned char *writearr, unsigned char *readarr) { - int count; /* First byte is cmd which can not being sent through FIFO. */ unsigned char cmd = *writearr++; - unsigned int readoffby1; - unsigned char readwrite; - writecnt--; - - msg_pspew("%s, cmd=%x, writecnt=%x, readcnt=%x\n", - __func__, cmd, writecnt, readcnt); - - if (readcnt > 8) { - msg_pinfo("%s, SB600 SPI controller can not receive %d bytes, " - "it is limited to 8 bytes\n", __func__, readcnt); - return SPI_INVALID_LENGTH; - } - - if (writecnt > 8) { - msg_pinfo("%s, SB600 SPI controller can not send %d bytes, " - "it is limited to 8 bytes\n", __func__, writecnt); - return SPI_INVALID_LENGTH; - } - - /* This is a workaround for a bug in SB600 and SB700. If we only send - * an opcode and no additional data/address, the SPI controller will - * read one byte too few from the chip. Basically, the last byte of - * the chip response is discarded and will not end up in the FIFO. - * It is unclear if the CS# line is set high too early as well. - */ - readoffby1 = (writecnt) ? 0 : 1; - readwrite = (readcnt + readoffby1) << 4 | (writecnt); - mmio_writeb(readwrite, sb600_spibar + 1); + msg_pspew("%s, cmd=%x, writecnt=%x, readcnt=%x\n", __func__, cmd, writecnt, readcnt); mmio_writeb(cmd, sb600_spibar + 0); - /* Before we use the FIFO, reset it first. */ - reset_internal_fifo_pointer(); + int ret = set_bytecounts(writecnt, readcnt); + if (ret != 0) + return ret; - /* Send the write byte to FIFO. */ - msg_pspew("Writing: "); - for (count = 0; count < writecnt; count++, writearr++) { - msg_pspew("[%02x]", *writearr); - mmio_writeb(*writearr, sb600_spibar + 0xC); - } - msg_pspew("\n"); + ret = fill_fifo(writearr, writecnt); + if (ret != 0) + return ret; - /* - * We should send the data by sequence, which means we need to reset - * the FIFO pointer to the first byte we want to send. - */ - if (reset_compare_internal_fifo_pointer(writecnt)) - return SPI_PROGRAMMER_ERROR; - - msg_pspew("Executing: \n"); - execute_command(); - - /* - * After the command executed, we should find out the index of the - * received byte. Here we just reset the FIFO pointer and skip the - * writecnt. - * It would be possible to increase the FIFO pointer by one instead - * of reading and discarding one byte from the FIFO. - * The FIFO is implemented on top of an 8 byte ring buffer and the - * buffer is never cleared. For every byte that is shifted out after - * the opcode, the FIFO already stores the response from the chip. - * Usually, the chip will respond with 0x00 or 0xff. - */ - if (reset_compare_internal_fifo_pointer(writecnt + readcnt)) - return SPI_PROGRAMMER_ERROR; + ret = execute_command(writecnt, readcnt); + if (ret != 0) + return ret; - /* Skip the bytes we sent. */ - msg_pspew("Skipping: "); - for (count = 0; count < writecnt; count++) { - cmd = mmio_readb(sb600_spibar + 0xC); - msg_pspew("[%02x]", cmd); - } - msg_pspew("\n"); - if (compare_internal_fifo_pointer(writecnt)) - return SPI_PROGRAMMER_ERROR; - - msg_pspew("Reading: "); - for (count = 0; count < readcnt; count++, readarr++) { - *readarr = mmio_readb(sb600_spibar + 0xC); - msg_pspew("[%02x]", *readarr); - } - msg_pspew("\n"); - if (reset_compare_internal_fifo_pointer(readcnt + writecnt)) - return SPI_PROGRAMMER_ERROR; - - if (mmio_readb(sb600_spibar + 1) != readwrite) { - msg_perr("Unexpected change in SB600 read/write count!\n"); - msg_perr("Something else is accessing the flash chip and " - "causes random corruption.\nPlease stop all " - "applications and drivers and IPMI which access the " - "flash chip.\n"); - return SPI_PROGRAMMER_ERROR; - } + ret = read_fifo(writecnt, readarr, readcnt); + if (ret != 0) + return ret; return 0; } @@ -282,6 +316,10 @@ static const struct spispeed spispeeds[] = { { "33 MHz", 0x01 }, { "22 MHz", 0x02 }, { "16.5 MHz", 0x03 }, + { "100 MHz", 0x04 }, + { "Reserved", 0x05 }, + { "Reserved", 0x06 }, + { "800 kHz", 0x07 }, }; static int set_speed(struct pci_dev *dev, const struct spispeed *spispeed) @@ -290,7 +328,12 @@ static int set_speed(struct pci_dev *dev, const struct spispeed *spispeed) uint8_t speed = spispeed->speed; msg_pdbg("Setting SPI clock to %s (0x%x).\n", spispeed->name, speed); - if (amd_gen != CHIPSET_YANGTZE) { + if (amd_gen >= CHIPSET_YANGTZE) { + rmmio_writew((speed << 12) | (speed << 8) | (speed << 4) | speed, sb600_spibar + 0x22); + uint8_t tmp = (mmio_readb(sb600_spibar + 0x22) >> 4); + success = (((tmp >> 12) & 0xf) == speed && ((tmp >> 8) & 0xf) == speed && + ((tmp >> 4) & 0xf) == speed && ((tmp >> 0) & 0xf) == speed); + } else { rmmio_writeb((mmio_readb(sb600_spibar + 0xd) & ~(0x3 << 4)) | (speed << 4), sb600_spibar + 0xd); success = (speed == ((mmio_readb(sb600_spibar + 0xd) >> 4) & 0x3)); } @@ -311,7 +354,28 @@ static int handle_speed(struct pci_dev *dev) * 18 rsvd <- fastReadEnable ? <- ? SpiReadMode[0] * 29:30 rsvd <- <- ? <- ? SpiReadMode[2:1] */ - if (amd_gen != CHIPSET_YANGTZE) { + if (amd_gen >= CHIPSET_YANGTZE) { + static const char *spireadmodes[] = { + "Normal (up to 33 MHz)", + "Reserved", + "Dual IO (1-1-2)", + "Quad IO (1-1-4)", + "Dual IO (1-2-2)", + "Quad IO (1-4-4)", + "Normal (up to 66 MHz)", + "Fast Read", + }; + tmp = mmio_readb(sb600_spibar + 0x00); + uint8_t read_mode = ((tmp >> 28) & 0x6) | ((tmp >> 18) & 0x1); + msg_pdbg("SpiReadMode=%s (%i)\n", spireadmodes[read_mode], read_mode); + tmp = mmio_readb(sb600_spibar + 0x20); + msg_pdbg("UseSpi100 is %sabled\n", (tmp & 0x1) ? "en" : "dis"); + tmp = mmio_readw(sb600_spibar + 0x22); /* SPI100 Speed Config */ + msg_pdbg("NormSpeedNew is %s\n", spispeeds[(tmp >> 12) & 0xf].name); + msg_pdbg("FastSpeedNew is %s\n", spispeeds[(tmp >> 8) & 0xf].name); + msg_pdbg("AltSpeedNew is %s\n", spispeeds[(tmp >> 4) & 0xf].name); + msg_pdbg("TpmSpeedNew is %s\n", spispeeds[(tmp >> 0) & 0xf].name); + } else { if (amd_gen >= CHIPSET_SB89XX && amd_gen <= CHIPSET_HUDSON234) { bool fast_read = (mmio_readl(sb600_spibar + 0x00) >> 18) & 0x1; msg_pdbg("Fast Reads are %sabled\n", fast_read ? "en" : "dis"); @@ -327,13 +391,28 @@ static int handle_speed(struct pci_dev *dev) return set_speed(dev, &spispeeds[spispeed_idx]); } - -static int sb600_handle_imc(struct pci_dev *dev, bool amd_imc_force) +static int handle_imc(struct pci_dev *dev) { /* Handle IMC everywhere but sb600 which does not have one. */ - if (dev->device_id == 0x438d) + if (amd_gen == CHIPSET_SB6XX) return 0; + bool amd_imc_force = false; + char *arg = extract_programmer_param("amd_imc_force"); + if (arg && !strcmp(arg, "yes")) { + amd_imc_force = true; + msg_pspew("amd_imc_force enabled.\n"); + } else if (arg && !strlen(arg)) { + msg_perr("Missing argument for amd_imc_force.\n"); + free(arg); + return 1; + } else if (arg) { + msg_perr("Unknown argument for amd_imc_force: \"%s\" (not \"yes\").\n", arg); + free(arg); + return 1; + } + free(arg); + /* TODO: we should not only look at IntegratedImcPresent (LPC Dev 20, Func 3, 40h) but also at * IMCEnable(Strap) and Override EcEnable(Strap) (sb8xx, sb9xx?, a50: Misc_Reg: 80h-87h; * sb7xx, sp5100: PM_Reg: B0h-B1h) etc. */ @@ -361,7 +440,7 @@ static int sb600_handle_imc(struct pci_dev *dev, bool amd_imc_force) return amd_imc_shutdown(dev); } -static const struct spi_programmer spi_programmer_sb600 = { +static struct spi_programmer spi_programmer_sb600 = { .type = SPI_CONTROLLER_SB600, .max_data_read = 8, .max_data_write = 5, @@ -377,22 +456,6 @@ int sb600_probe_spi(struct pci_dev *dev) struct pci_dev *smbus_dev; uint32_t tmp; uint8_t reg; - bool amd_imc_force = false; - - char *arg = extract_programmer_param("amd_imc_force"); - if (arg && !strcmp(arg, "yes")) { - amd_imc_force = true; - msg_pspew("amd_imc_force enabled.\n"); - } else if (arg && !strlen(arg)) { - msg_perr("Missing argument for amd_imc_force.\n"); - free(arg); - return ERROR_FATAL; - } else if (arg) { - msg_perr("Unknown argument for amd_imc_force: \"%s\" (not \"yes\").\n", arg); - free(arg); - return ERROR_FATAL; - } - free(arg); /* Read SPI_BaseAddr */ tmp = pci_read_long(dev, 0xa0); @@ -419,12 +482,6 @@ int sb600_probe_spi(struct pci_dev *dev) amd_gen = CHIPSET_SB6XX; } - if (amd_gen == CHIPSET_YANGTZE) { - msg_perr("SPI on Kabini/Temash and newer chipsets are not yet supported.\n" - "Please try a newer version of flashrom.\n"); - return ERROR_NONFATAL; - } - /* Chipset support matrix for SPI Base_Addr (LPC PCI reg 0xa0) * bit 6xx 7xx/SP5100 8xx 9xx hudson1 hudson234 yangtze * 3 rsvd <- <- ? <- ? RouteTpm2Spi @@ -437,6 +494,8 @@ int sb600_probe_spi(struct pci_dev *dev) msg_pdbg("SpiRomEnable=%i", (tmp >> 1) & 0x1); if (amd_gen == CHIPSET_SB7XX) msg_pdbg(", AltSpiCSEnable=%i, AbortEnable=%i", tmp & 0x1, (tmp >> 2) & 0x1); + else if (amd_gen == CHIPSET_YANGTZE) + msg_pdbg(", RouteTpm2Sp=%i", (tmp >> 3) & 0x1); tmp = pci_read_byte(dev, 0xba); msg_pdbg(", PrefetchEnSPIFromIMC=%i", (tmp & 0x4) >> 2); @@ -470,15 +529,21 @@ int sb600_probe_spi(struct pci_dev *dev) */ tmp = mmio_readl(sb600_spibar + 0x00); msg_pdbg("(0x%08" PRIx32 ") SpiArbEnable=%i", tmp, (tmp >> 19) & 0x1); + if (amd_gen == CHIPSET_YANGTZE) + msg_pdbg(", IllegalAccess=%i", (tmp >> 21) & 0x1); msg_pdbg(", SpiAccessMacRomEn=%i, SpiHostAccessRomEn=%i, ArbWaitCount=%i", (tmp >> 22) & 0x1, (tmp >> 23) & 0x1, (tmp >> 24) & 0x7); + if (amd_gen != CHIPSET_YANGTZE) + msg_pdbg(", SpiBridgeDisable=%i", (tmp >> 27) & 0x1); + switch (amd_gen) { case CHIPSET_SB7XX: msg_pdbg(", DropOneClkOnRd/SpiClkGate=%i", (tmp >> 28) & 0x1); case CHIPSET_SB89XX: case CHIPSET_HUDSON234: + case CHIPSET_YANGTZE: msg_pdbg(", SpiBusy=%i", (tmp >> 31) & 0x1); default: break; } @@ -531,12 +596,14 @@ int sb600_probe_spi(struct pci_dev *dev) if (handle_speed(dev) != 0) return ERROR_FATAL; - if (sb600_handle_imc(dev, amd_imc_force) != 0) + if (handle_imc(dev) != 0) return ERROR_FATAL; - /* Bring the FIFO to a clean state. */ - reset_internal_fifo_pointer(); - + /* Starting with Yangtze the SPI controller got a bigger FIFO */ + if (amd_gen == CHIPSET_YANGTZE) { + spi_programmer_sb600.max_data_read = 71; + spi_programmer_sb600.max_data_read = 71 - 3; + } register_spi_programmer(&spi_programmer_sb600); return 0; } -- Kind regards, Stefan Tauner

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[PATCH 2/4] sbxxx: Set SPI clock to 16.5 MHz and disable fast reads.
by Stefan Tauner 08 Aug '13

08 Aug '13

Do not rely on broken firmware to set up the SPI configuration correctly. Some boards fail with flashrom because the firmware chose too high speeds for the alternate SPI mode which flashrom uses. Temporarily change the clock to the lowest common value of 16.5 MHz. Also, disable fast reads just to be safe. Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> --- sb600spi.c | 65 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++------ 1 file changed, 59 insertions(+), 6 deletions(-) diff --git a/sb600spi.c b/sb600spi.c index 754148b..9ab7a58 100644 --- a/sb600spi.c +++ b/sb600spi.c @@ -272,6 +272,62 @@ static int sb600_spi_send_command(struct flashctx *flash, unsigned int writecnt, return 0; } +struct spispeed { + const char *const name; + const int8_t speed; +}; + +static const struct spispeed spispeeds[] = { + { "66 MHz", 0x00 }, + { "33 MHz", 0x01 }, + { "22 MHz", 0x02 }, + { "16.5 MHz", 0x03 }, +}; + +static int set_speed(struct pci_dev *dev, const struct spispeed *spispeed) +{ + bool success = false; + uint8_t speed = spispeed->speed; + + msg_pdbg("Setting SPI clock to %s (0x%x).\n", spispeed->name, speed); + if (amd_gen != CHIPSET_YANGTZE) { + rmmio_writeb((mmio_readb(sb600_spibar + 0xd) & ~(0x3 << 4)) | (speed << 4), sb600_spibar + 0xd); + success = (speed == ((mmio_readb(sb600_spibar + 0xd) >> 4) & 0x3)); + } + + if (!success) { + msg_perr("Setting SPI clock failed.\n"); + return 1; + } + return 0; +} + +static int handle_speed(struct pci_dev *dev) +{ + uint8_t tmp; + uint8_t spispeed_idx = 3; /* Default to 16.5 MHz */ + +/* bit 6xx 7xx/SP5100 8xx 9xx hudson1 hudson234 yangtze + * 18 rsvd <- fastReadEnable ? <- ? SpiReadMode[0] + * 29:30 rsvd <- <- ? <- ? SpiReadMode[2:1] + */ + if (amd_gen != CHIPSET_YANGTZE) { + if (amd_gen >= CHIPSET_SB89XX && amd_gen <= CHIPSET_HUDSON234) { + bool fast_read = (mmio_readl(sb600_spibar + 0x00) >> 18) & 0x1; + msg_pdbg("Fast Reads are %sabled\n", fast_read ? "en" : "dis"); + if (fast_read) { + msg_pdbg("Disabling them temporarily.\n"); + rmmio_writel(mmio_readl(sb600_spibar + 0x00) & ~(0x1 << 18), + sb600_spibar + 0x00); + } + } + tmp = (mmio_readb(sb600_spibar + 0xd) >> 4) & 0x3; + msg_pdbg("NormSpeed is %s\n", spispeeds[tmp].name); + } + return set_speed(dev, &spispeeds[spispeed_idx]); +} + + static int sb600_handle_imc(struct pci_dev *dev, bool amd_imc_force) { /* Handle IMC everywhere but sb600 which does not have one. */ @@ -322,9 +378,6 @@ int sb600_probe_spi(struct pci_dev *dev) uint32_t tmp; uint8_t reg; bool amd_imc_force = false; - static const char *const speed_names[4] = { - "66/reserved", "33", "22", "16.5" - }; char *arg = extract_programmer_param("amd_imc_force"); if (arg && !strcmp(arg, "yes")) { @@ -436,9 +489,6 @@ int sb600_probe_spi(struct pci_dev *dev) return ERROR_NONFATAL; } - tmp = (mmio_readb(sb600_spibar + 0xd) >> 4) & 0x3; - msg_pdbg("NormSpeed is %s MHz\n", speed_names[tmp]); - /* Look for the SMBus device. */ smbus_dev = pci_dev_find(0x1002, 0x4385); if (!smbus_dev) { @@ -478,6 +528,9 @@ int sb600_probe_spi(struct pci_dev *dev) return 0; } + if (handle_speed(dev) != 0) + return ERROR_FATAL; + if (sb600_handle_imc(dev, amd_imc_force) != 0) return ERROR_FATAL; -- Kind regards, Stefan Tauner

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flashrom August 2013